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https://github.com/brain-hackers/u-boot-brain
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power: regulator: add driver for ANATOP regulator
Anatop is an integrated regulator inside i.MX6 SoC. There are 3 digital regulators which controls PU, CORE (ARM), and SOC. And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB). This patch adds the Anatop regulator driver. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This commit is contained in:
Ying-Chun Liu (PaulLiu)
Tom Rini
parent
ec611871f3
commit
6ab0286ae1
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@ -312,6 +312,16 @@ config DM_REGULATOR_STPMIC1
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by the PMIC device. This driver is controlled by a device tree node
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which includes voltage limits.
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config DM_REGULATOR_ANATOP
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bool "Enable driver for ANATOP regulators"
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depends on DM_REGULATOR
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select REGMAP
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select SYSCON
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help
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Enable support for the Freescale i.MX on-chip ANATOP LDO
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regulators. It is recommended that this option be enabled on
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i.MX6 platform.
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config SPL_DM_REGULATOR_STPMIC1
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bool "Enable driver for STPMIC1 regulators in SPL"
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depends on SPL_DM_REGULATOR && PMIC_STPMIC1
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@ -31,3 +31,4 @@ obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o
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obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
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obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o
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278
drivers/power/regulator/anatop_regulator.c
Normal file
278
drivers/power/regulator/anatop_regulator.c
Normal file
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@ -0,0 +1,278 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2021 Linaro
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <dm/device-internal.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
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#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
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#define LDO_POWER_GATE 0x00
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#define LDO_FET_FULL_ON 0x1f
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#define BIT_WIDTH_MAX 32
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#define ANATOP_REGULATOR_STEP 25000
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#define MIN_DROPOUT_UV 125000
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struct anatop_regulator {
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const char *name;
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struct regmap *regmap;
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struct udevice *supply;
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u32 control_reg;
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u32 vol_bit_shift;
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u32 vol_bit_width;
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u32 min_bit_val;
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u32 min_voltage;
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u32 max_voltage;
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u32 delay_reg;
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u32 delay_bit_shift;
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u32 delay_bit_width;
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};
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static u32 anatop_get_bits(struct udevice *dev, u32 addr, int bit_shift,
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int bit_width)
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{
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const struct anatop_regulator *anatop_reg = dev_get_plat(dev);
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int err;
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u32 val, mask;
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if (bit_width == BIT_WIDTH_MAX)
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mask = ~0;
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else
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mask = (1 << bit_width) - 1;
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err = regmap_read(anatop_reg->regmap, addr, &val);
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if (err) {
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dev_dbg(dev, "cannot read reg (%d)\n", err);
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return err;
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}
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val = (val >> bit_shift) & mask;
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return val;
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}
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static int anatop_set_bits(struct udevice *dev, u32 addr, int bit_shift,
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int bit_width, u32 data)
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{
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const struct anatop_regulator *anatop_reg = dev_get_plat(dev);
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int err;
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u32 val, mask;
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if (bit_width == 32)
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mask = ~0;
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else
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mask = (1 << bit_width) - 1;
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err = regmap_read(anatop_reg->regmap, addr, &val);
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if (err) {
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dev_dbg(dev, "cannot read reg (%d)\n", err);
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return err;
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}
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val = val & ~(mask << bit_shift);
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err = regmap_write(anatop_reg->regmap,
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addr, (data << bit_shift) | val);
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if (err) {
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dev_dbg(dev, "cannot write reg (%d)\n", err);
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return err;
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}
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return 0;
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}
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static int anatop_get_voltage(struct udevice *dev)
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{
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const struct anatop_regulator *anatop_reg = dev_get_plat(dev);
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u32 sel;
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u32 val;
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if (!anatop_reg->control_reg)
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return -ENOSYS;
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val = anatop_get_bits(dev,
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anatop_reg->control_reg,
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anatop_reg->vol_bit_shift,
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anatop_reg->vol_bit_width);
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sel = val - anatop_reg->min_bit_val;
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return sel * ANATOP_REGULATOR_STEP + anatop_reg->min_voltage;
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}
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static int anatop_set_voltage(struct udevice *dev, int uV)
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{
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const struct anatop_regulator *anatop_reg = dev_get_plat(dev);
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u32 val;
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u32 sel;
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int ret;
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dev_dbg(dev, "uv %d, min %d, max %d\n", uV, anatop_reg->min_voltage,
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anatop_reg->max_voltage);
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if (uV < anatop_reg->min_voltage)
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return -EINVAL;
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if (!anatop_reg->control_reg)
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return -ENOSYS;
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sel = DIV_ROUND_UP(uV - anatop_reg->min_voltage,
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ANATOP_REGULATOR_STEP);
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if (sel * ANATOP_REGULATOR_STEP + anatop_reg->min_voltage >
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anatop_reg->max_voltage)
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return -EINVAL;
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val = anatop_reg->min_bit_val + sel;
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dev_dbg(dev, "calculated val %d\n", val);
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if (anatop_reg->supply) {
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ret = regulator_set_value(anatop_reg->supply,
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uV + MIN_DROPOUT_UV);
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if (ret)
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return ret;
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}
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ret = anatop_set_bits(dev,
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anatop_reg->control_reg,
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anatop_reg->vol_bit_shift,
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anatop_reg->vol_bit_width,
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val);
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return ret;
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}
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static const struct dm_regulator_ops anatop_regulator_ops = {
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.set_value = anatop_set_voltage,
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.get_value = anatop_get_voltage,
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};
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static int anatop_regulator_probe(struct udevice *dev)
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{
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struct anatop_regulator *anatop_reg;
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struct dm_regulator_uclass_plat *uc_pdata;
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struct udevice *syscon;
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int ret = 0;
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u32 val;
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anatop_reg = dev_get_plat(dev);
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uc_pdata = dev_get_uclass_plat(dev);
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anatop_reg->name = ofnode_read_string(dev_ofnode(dev),
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"regulator-name");
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if (!anatop_reg->name)
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return log_msg_ret("regulator-name", -EINVAL);
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ret = device_get_supply_regulator(dev, "vin-supply",
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&anatop_reg->supply);
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if (ret != -ENODEV) {
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if (ret)
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return log_msg_ret("get vin-supply", ret);
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ret = regulator_set_enable(anatop_reg->supply, true);
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if (ret)
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return ret;
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}
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ret = dev_read_u32(dev,
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"anatop-reg-offset",
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&anatop_reg->control_reg);
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if (ret)
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return log_msg_ret("anatop-reg-offset", ret);
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ret = dev_read_u32(dev,
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"anatop-vol-bit-width",
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&anatop_reg->vol_bit_width);
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if (ret)
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return log_msg_ret("anatop-vol-bit-width", ret);
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ret = dev_read_u32(dev,
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"anatop-vol-bit-shift",
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&anatop_reg->vol_bit_shift);
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if (ret)
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return log_msg_ret("anatop-vol-bit-shift", ret);
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ret = dev_read_u32(dev,
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"anatop-min-bit-val",
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&anatop_reg->min_bit_val);
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if (ret)
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return log_msg_ret("anatop-min-bit-val", ret);
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ret = dev_read_u32(dev,
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"anatop-min-voltage",
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&anatop_reg->min_voltage);
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if (ret)
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return log_msg_ret("anatop-min-voltage", ret);
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ret = dev_read_u32(dev,
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"anatop-max-voltage",
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&anatop_reg->max_voltage);
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if (ret)
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return log_msg_ret("anatop-max-voltage", ret);
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/* read LDO ramp up setting, only for core reg */
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dev_read_u32(dev, "anatop-delay-reg-offset",
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&anatop_reg->delay_reg);
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dev_read_u32(dev, "anatop-delay-bit-width",
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&anatop_reg->delay_bit_width);
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dev_read_u32(dev, "anatop-delay-bit-shift",
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&anatop_reg->delay_bit_shift);
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syscon = dev_get_parent(dev);
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if (!syscon) {
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dev_dbg(dev, "unable to find syscon device\n");
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return -ENOENT;
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}
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anatop_reg->regmap = syscon_get_regmap(syscon);
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if (IS_ERR(anatop_reg->regmap)) {
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dev_dbg(dev, "unable to find regmap (%ld)\n",
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PTR_ERR(anatop_reg->regmap));
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return -ENOENT;
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}
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/* check whether need to care about LDO ramp up speed */
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if (anatop_reg->delay_bit_width) {
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/*
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* the delay for LDO ramp up time is
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* based on the register setting, we need
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* to calculate how many steps LDO need to
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* ramp up, and how much delay needed. (us)
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*/
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val = anatop_get_bits(dev,
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anatop_reg->delay_reg,
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anatop_reg->delay_bit_shift,
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anatop_reg->delay_bit_width);
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uc_pdata->ramp_delay = (LDO_RAMP_UP_UNIT_IN_CYCLES << val)
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/ LDO_RAMP_UP_FREQ_IN_MHZ + 1;
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}
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return 0;
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}
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static const struct udevice_id of_anatop_regulator_match_tbl[] = {
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{ .compatible = "fsl,anatop-regulator", },
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{ /* end */ }
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};
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U_BOOT_DRIVER(anatop_regulator) = {
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.name = "anatop_regulator",
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.id = UCLASS_REGULATOR,
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.ops = &anatop_regulator_ops,
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.of_match = of_anatop_regulator_match_tbl,
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.plat_auto = sizeof(struct anatop_regulator),
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.probe = anatop_regulator_probe,
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};
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