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fsl-ddr: Fix two bugs in the ddr infrastructure
1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com>
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@ -302,12 +302,15 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
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*/
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*/
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wr_lat = 0;
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wr_lat = 0;
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#elif defined(CONFIG_FSL_DDR2)
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#elif defined(CONFIG_FSL_DDR2)
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wr_lat = cas_latency + additive_latency - 1;
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wr_lat = cas_latency - 1;
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#else
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#else
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#error "Fix WR_LAT for DDR3"
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#error "Fix WR_LAT for DDR3"
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#endif
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#endif
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rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
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rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
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#if defined(CONFIG_FSL_DDR2)
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rd_to_pre += additive_latency;
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#endif
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wr_data_delay = popts->write_data_delay;
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wr_data_delay = popts->write_data_delay;
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cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
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cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
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four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
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four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
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