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pci: pci_mvebu: Disable config access to PCI host bridge ports
This patch changes the PCI config routines in the Armada XP / 38x driver to not allow access to the PCIe root ports. While updating the Armada XP based theadorable to the latest mainline and testing it with the DM PCI driver I noticed, that the PCI root bridge was being configured incorrectly. Resulting in the PCIe Intel WiFi was not working correctly in Linux. With this patch applied, all PCIe devices work without any issues in Linux again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc>
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@ -153,28 +153,21 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
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u32 reg;
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u32 reg;
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u32 data;
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u32 data;
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debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
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debug("PCIE CFG read: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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/* Only allow one other device besides the local one on the local bus */
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/* Don't access the local host controller via this API */
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if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
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if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
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if (local_dev == 0 && PCI_DEV(bdf) != 1) {
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debug("- skipping host controller\n");
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debug("- out of range\n");
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*valuep = pci_get_ff(size);
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/*
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return 0;
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* If local dev is 0, the first other dev can
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}
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* only be 1
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*/
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/* If local dev is 0, the first other dev can only be 1 */
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*valuep = pci_get_ff(size);
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if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
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return 0;
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debug("- out of range\n");
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} else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
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*valuep = pci_get_ff(size);
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debug("- out of range\n");
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return 0;
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/*
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* If local dev is not 0, the first other dev can
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* only be 0
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*/
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*valuep = pci_get_ff(size);
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return 0;
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}
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}
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}
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/* write address */
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/* write address */
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@ -196,25 +189,20 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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int local_dev = PCI_DEV(pcie->dev);
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int local_dev = PCI_DEV(pcie->dev);
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u32 data;
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u32 data;
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debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
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debug("PCIE CFG write: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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/* Only allow one other device besides the local one on the local bus */
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/* Don't access the local host controller via this API */
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if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
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if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
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if (local_dev == 0 && PCI_DEV(bdf) != 1) {
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debug("- skipping host controller\n");
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/*
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return 0;
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* If local dev is 0, the first other dev can
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}
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* only be 1
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*/
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/* If local dev is 0, the first other dev can only be 1 */
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return 0;
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if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
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} else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
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debug("- out of range\n");
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/*
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return 0;
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* If local dev is not 0, the first other dev can
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* only be 0
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*/
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return 0;
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}
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}
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}
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writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
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writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
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