From 34b1a510e872baa0512562a72069c06c340e88fd Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 21 May 2019 22:03:12 +0200 Subject: [PATCH 1/4] gpio: dwapb_gpio: fix broken dev->node commit 1b898ffc040b ("gpio: dwapb_gpio: convert to livetree") introduced a bug in that dev->node of the gpio chip was accidentally set to the of_node of its bank subnode. What it meant to do was assign subdev->node, not dev->node. While this doesn't affect too many use cases, iterating over the gpio chip's properties doesn't work any more after that, so fix this. Fixes: commit 1b898ffc040b ("gpio: dwapb_gpio: convert to livetree") Signed-off-by: Simon Goldschmidt --- drivers/gpio/dwapb_gpio.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index 04a2381acd..2eb1547b4f 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -185,12 +185,11 @@ static int gpio_dwapb_bind(struct udevice *dev) plat->name = ofnode_get_name(node); } - ret = device_bind(dev, dev->driver, plat->name, - plat, -1, &subdev); + ret = device_bind_ofnode(dev, dev->driver, plat->name, + plat, node, &subdev); if (ret) return ret; - dev->node = node; bank++; } From 501be470324795df3dea0647cce6072cb89d926e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 21 Mar 2019 23:05:38 +0100 Subject: [PATCH 2/4] ARM: socfpga: Pull PL310 clearing into common code Pull the PL310 clearing code into common code, so it can be reused by Arria10. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 54 +++++++++++++++++++++ arch/arm/mach-socfpga/spl_gen5.c | 57 ----------------------- 3 files changed, 55 insertions(+), 57 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index c3ca8cdf3b..27d0b6a370 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); #endif void do_bridge_reset(int enable, unsigned int mask); +void socfpga_pl310_clear(void); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index db1983dc31..49dadd4c3d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -70,6 +70,60 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } + +void socfpga_pl310_clear(void) +{ + u32 mask = 0xff, ena = 0; + + icache_enable(); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x0, &pl310->pl310_tag_latency_ctrl); + writel(0x10, &pl310->pl310_data_latency_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + ena = readl(&pl310->pl310_ctrl); + ena |= L2X0_CTRL_EN; + + /* + * Invalidate the PL310 L2 cache. Keep the invalidation code + * entirely in L1 I-cache to avoid any bus traffic through + * the L2. + */ + asm volatile( + ".align 5 \n" + " b 3f \n" + "1: str %1, [%4] \n" + " dsb \n" + " isb \n" + " str %0, [%2] \n" + " dsb \n" + " isb \n" + "2: ldr %0, [%2] \n" + " cmp %0, #0 \n" + " bne 2b \n" + " str %0, [%3] \n" + " dsb \n" + " isb \n" + " b 4f \n" + "3: b 1b \n" + "4: nop \n" + : "+r"(mask), "+r"(ena) + : "r"(&pl310->pl310_inv_way), + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) + : "memory", "cc"); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} #endif #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 1a60cdc897..87b76b47de 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -25,8 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; @@ -63,60 +60,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif -static void socfpga_pl310_clear(void) -{ - u32 mask = 0xff, ena = 0; - - icache_enable(); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x111, &pl310->pl310_tag_latency_ctrl); - writel(0x121, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); - - /* Enable the L2 cache */ - ena = readl(&pl310->pl310_ctrl); - ena |= L2X0_CTRL_EN; - - /* - * Invalidate the PL310 L2 cache. Keep the invalidation code - * entirely in L1 I-cache to avoid any bus traffic through - * the L2. - */ - asm volatile( - ".align 5 \n" - " b 3f \n" - "1: str %1, [%4] \n" - " dsb \n" - " isb \n" - " str %0, [%2] \n" - " dsb \n" - " isb \n" - "2: ldr %0, [%2] \n" - " cmp %0, #0 \n" - " bne 2b \n" - " str %0, [%3] \n" - " dsb \n" - " isb \n" - " b 4f \n" - "3: b 1b \n" - "4: nop \n" - : "+r"(mask), "+r"(ena) - : "r"(&pl310->pl310_inv_way), - "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) - : "memory", "cc"); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); From 476abb72e084c8ebbba206ac1c52c6536a103d4a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 Mar 2019 22:25:57 +0100 Subject: [PATCH 3/4] ARM: socfpga: Clear PL310 early in SPL On SoCFPGA A10 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/mach-socfpga/spl_a10.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index b466307f98..b820cb0673 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -110,6 +110,7 @@ void board_init_f(ulong dummy) socfpga_init_security_policies(); socfpga_sdram_remap_zero(); + socfpga_pl310_clear(); /* Assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all(); From ca9387e8b1e276e17244010620319cc8bbd1c655 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Fri, 24 May 2019 20:14:17 +0800 Subject: [PATCH 4/4] Arm: dts: socfpga: Remove invalid property from chose node Finding bitstream from cff-file is no longer valid after bitstream is built into FIT image and loaded by generic firmware loader. Remove cff-file as this is legacy implementation from A10 downstream. Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi index 0446fd441e..60c419251b 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi @@ -16,10 +16,6 @@ #size-cells = <1>; model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ - chosen { - cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */ - }; - /* Clock sources */ clocks { #address-cells = <1>;