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https://github.com/brain-hackers/u-boot-brain
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powerpc/85xx:Make debug exception vector accessible
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. 1) While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. 2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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@ -1,5 +1,5 @@
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/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc
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* Copyright 2009-2012 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -53,6 +53,36 @@ void setup_ifc(void)
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asm volatile("isync;msync;tlbwe;isync");
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#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
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/*
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* TLB entry for debuggging in AS1
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* Create temporary TLB entry in AS0 to handle debug exception
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* As on debug exception MSR is cleared i.e. Address space is changed
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* to 0. A TLB entry (in AS0) is required to handle debug exception generated
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* in AS1.
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*
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* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
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* bacause flash's physical address is going to change as
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* CONFIG_SYS_FLASH_BASE_PHYS.
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*/
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_mas0 = MAS0_TLBSEL(1) |
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MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
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_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
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MAS1_TSIZE(BOOKE_PAGESZ_4M);
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_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
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_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
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_mas7 = FSL_BOOKE_MAS7(flash_phys);
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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mtspr(MAS7, _mas7);
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asm volatile("isync;msync;tlbwe;isync");
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#endif
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/* Change flash's physical address */
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out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
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out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
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out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
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@ -182,6 +182,72 @@ l2_disabled:
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andi. r1,r3,L1CSR0_DCE@l
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beq 2b
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#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
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/*
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* TLB entry for debuggging in AS1
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* Create temporary TLB entry in AS0 to handle debug exception
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* As on debug exception MSR is cleared i.e. Address space is changed
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* to 0. A TLB entry (in AS0) is required to handle debug exception generated
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* in AS1.
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*/
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lis r6,FSL_BOOKE_MAS0(1,
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CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
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ori r6,r6,FSL_BOOKE_MAS0(1,
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CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
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#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
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/*
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* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
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* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
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* and this window is outside of 4K boot window.
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*/
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lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
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ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
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lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
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(MAS2_I|MAS2_G))@h
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ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
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(MAS2_I|MAS2_G))@l
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/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
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lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
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ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
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#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
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lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
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ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
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lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
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ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
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lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))@h
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ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))@l
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#else
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/*
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* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
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* because "nexti" will resize TLB to 4K
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*/
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lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
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ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
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lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
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ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
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(MAS2_I))@l
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lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))@h
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ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))@l
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#endif
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mtspr MAS0,r6
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mtspr MAS1,r7
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mtspr MAS2,r8
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mtspr MAS3,r9
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tlbwe
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isync
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#endif
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/*
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* Ne need to setup interrupt vector for NAND SPL
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* because NAND SPL never compiles it.
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@ -1375,17 +1441,24 @@ relocate_code:
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7: sync /* Wait for all icbi to complete on bus */
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isync
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/*
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* Re-point the IVPR at RAM
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*/
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mtspr IVPR,r10
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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addi r0,r10,in_ram - _start + _START_OFFSET
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/*
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* As IVPR is going to point RAM address,
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* Make sure IVOR15 has valid opcode to support debugger
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*/
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mtspr IVOR15,r0
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/*
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* Re-point the IVPR at RAM
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*/
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mtspr IVPR,r10
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mtlr r0
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blr /* NEVER RETURNS! */
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.globl in_ram
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