From 94a16b8e70ba8102d8abb0c9bc64b11e19d4bd55 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:31 +0200 Subject: [PATCH 1/5] ARM: socfpga: vining_fpga: Rename VINING|FPGA The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 2 +- arch/arm/mach-socfpga/Kconfig | 10 +++++----- board/{samtec => softing}/vining_fpga/MAINTAINERS | 0 board/{samtec => softing}/vining_fpga/Makefile | 0 .../vining_fpga/qts/iocsr_config.h | 0 .../vining_fpga/qts/pinmux_config.h | 0 .../{samtec => softing}/vining_fpga/qts/pll_config.h | 0 .../vining_fpga/qts/sdram_config.h | 0 board/{samtec => softing}/vining_fpga/socfpga.c | 0 configs/socfpga_vining_fpga_defconfig | 6 +++--- include/configs/socfpga_vining_fpga.h | 12 ++++++------ 11 files changed, 15 insertions(+), 15 deletions(-) rename board/{samtec => softing}/vining_fpga/MAINTAINERS (100%) rename board/{samtec => softing}/vining_fpga/Makefile (100%) rename board/{samtec => softing}/vining_fpga/qts/iocsr_config.h (100%) rename board/{samtec => softing}/vining_fpga/qts/pinmux_config.h (100%) rename board/{samtec => softing}/vining_fpga/qts/pll_config.h (100%) rename board/{samtec => softing}/vining_fpga/qts/sdram_config.h (100%) rename board/{samtec => softing}/vining_fpga/socfpga.c (100%) diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index ac57f41cb5..be52fbf43d 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -8,7 +8,7 @@ #include / { - model = "samtec VIN|ING FPGA"; + model = "Softing VIN|ING FPGA"; compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 45de153aa5..fc0a54214f 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -100,8 +100,8 @@ config TARGET_SOCFPGA_IS1 bool "IS1 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 -config TARGET_SOCFPGA_SAMTEC_VINING_FPGA - bool "samtec VIN|ING FPGA (Cyclone V)" +config TARGET_SOCFPGA_SOFTING_VINING_FPGA + bool "Softing VIN|ING FPGA (Cyclone V)" select BOARD_LATE_INIT select TARGET_SOCFPGA_CYCLONE5 @@ -145,7 +145,7 @@ config SYS_BOARD default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK - default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -155,7 +155,7 @@ config SYS_VENDOR default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES - default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO @@ -178,6 +178,6 @@ config SYS_CONFIG_NAME default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK - default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA endif diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/softing/vining_fpga/MAINTAINERS similarity index 100% rename from board/samtec/vining_fpga/MAINTAINERS rename to board/softing/vining_fpga/MAINTAINERS diff --git a/board/samtec/vining_fpga/Makefile b/board/softing/vining_fpga/Makefile similarity index 100% rename from board/samtec/vining_fpga/Makefile rename to board/softing/vining_fpga/Makefile diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h similarity index 100% rename from board/samtec/vining_fpga/qts/iocsr_config.h rename to board/softing/vining_fpga/qts/iocsr_config.h diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/softing/vining_fpga/qts/pinmux_config.h similarity index 100% rename from board/samtec/vining_fpga/qts/pinmux_config.h rename to board/softing/vining_fpga/qts/pinmux_config.h diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h similarity index 100% rename from board/samtec/vining_fpga/qts/pll_config.h rename to board/softing/vining_fpga/qts/pll_config.h diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h similarity index 100% rename from board/samtec/vining_fpga/qts/sdram_config.h rename to board/softing/vining_fpga/qts/sdram_config.h diff --git a/board/samtec/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c similarity index 100% rename from board/samtec/vining_fpga/socfpga.c rename to board/softing/vining_fpga/socfpga.c diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index c52afddd20..faa4a17de5 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y +CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -35,7 +35,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set @@ -86,7 +86,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="samtec" +CONFIG_USB_GADGET_MANUFACTURER="softing" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 232536a763..ef3221e1c8 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2015 Marek Vasut + * Copyright (C) 2015-2019 Marek Vasut */ -#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__ -#define __CONFIG_SAMTEC_VINING_FPGA_H__ +#ifndef __CONFIG_SOFTING_VINING_FPGA_H__ +#define __CONFIG_SOFTING_VINING_FPGA_H__ #include @@ -50,8 +50,8 @@ "1m(u-boot)," \ "64k(env1)," \ "64k(env2)," \ - "256k(samtec1)," \ - "256k(samtec2)," \ + "256k(softing1)," \ + "256k(softing2)," \ "-(rcvrfs)\0" /* Recovery */ \ "mtdparts_1=ff705000.spi.1:" \ "32m(rootfs)," \ @@ -150,4 +150,4 @@ /* The rest of the configuration is shared */ #include -#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */ +#endif /* __CONFIG_SOFTING_VINING_FPGA_H__ */ From 4a9f633e3d13dbeb6a88de13074c48ec63210f5c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:32 +0200 Subject: [PATCH 2/5] ARM: socfpga: vining_fpga: Update DT Pick minor changes from the downstream DT, disable MMC, add GMAC0 node and adjust PHY skew settings for GMAC1. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- .../dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 15 ++++++++++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index db55a4ecad..44bedd8b67 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -20,7 +20,7 @@ }; &mmc { - u-boot,dm-pre-reloc; + status = "disabled"; }; &qspi { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index be52fbf43d..3fb6e14372 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR X11) /* - * Copyright (C) 2015 Marek Vasut + * Copyright (C) 2015-2019 Marek Vasut */ #include "socfpga_cyclone5.dtsi" @@ -65,6 +65,11 @@ }; }; +&gmac0 { + status = "disabled"; + phy-mode = "gmii"; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; @@ -84,10 +89,14 @@ rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <1560>; + txc-skew-ps = <1860>; rxdv-skew-ps = <0>; - rxc-skew-ps = <1200>; + rxc-skew-ps = <1860>; }; }; }; From 76f0f010086aad0847e846633688262655c4a9d4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:33 +0200 Subject: [PATCH 3/5] ARM: socfpga: vining_fpga: Update generated headers Update headers generated by quartus to the latest version. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- board/softing/vining_fpga/qts/iocsr_config.h | 140 +++++++++--------- board/softing/vining_fpga/qts/pinmux_config.h | 6 +- board/softing/vining_fpga/qts/pll_config.h | 12 +- board/softing/vining_fpga/qts/sdram_config.h | 12 +- 4 files changed, 82 insertions(+), 88 deletions(-) diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h index 1fe2a09e56..8c78aecdd3 100644 --- a/board/softing/vining_fpga/qts/iocsr_config.h +++ b/board/softing/vining_fpga/qts/iocsr_config.h @@ -139,9 +139,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x07900000, 0x08020000, 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, + 0xD4380000, + 0xE0003000, + 0x00C00350, 0x00000000, 0x00000021, 0x82000004, @@ -153,10 +153,10 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x03C80000, 0x05400000, 0x03C80000, - 0xE4400000, - 0x00001800, - 0x00600391, - 0x800E4400, + 0x6A1C0000, + 0x70001800, + 0x006001A8, + 0x8006A1C0, 0x00000001, 0x40000002, 0x02A00000, @@ -167,11 +167,11 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x01E40000, 0x02A00000, 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, + 0x350E0000, + 0x38000C00, + 0x003000D4, + 0xC00350E0, + 0x0D438000, 0x20000300, 0x00040000, 0x50670000, @@ -200,9 +200,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x15000000, 0x0F200000, 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, + 0xC0000000, + 0x018006A1, + 0x001A8700, 0x007F8006, 0x00000000, 0x0A800001, @@ -213,11 +213,11 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x07900000, 0x08020000, 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, + 0xD4380000, + 0xE0003000, + 0x00C00350, 0x00000FF0, - 0x72200000, + 0x350E0000, 0x80000C00, 0x05400000, 0x02480000, @@ -228,9 +228,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x05400000, 0x03C80000, 0x6A1C0000, - 0x00001800, - 0x00600391, - 0x800E4400, + 0x70001800, + 0x006001A8, + 0x8006A1C0, 0x1A870001, 0x40000600, 0x02A00040, @@ -241,11 +241,11 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x01E40000, 0x02A00000, 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, + 0x350E0000, + 0x38000C00, + 0x003000D4, + 0xC00350E0, + 0x0D438000, 0x20000300, 0x00040000, 0x50670000, @@ -262,9 +262,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x01A00040, 0x280D0002, 0x5140680A, - 0x02490340, - 0xD012481A, - 0x0680A280, + 0x01450340, + 0xD00A281A, + 0x0680E380, 0x10040000, 0x00200000, 0x10040000, @@ -274,9 +274,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x15000000, 0x0F200000, 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, + 0xC0000000, + 0x018006A1, + 0x001A8700, 0x007F8006, 0x00000000, 0x99300001, @@ -304,8 +304,8 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x5506A000, 0x00E1D400, 0x00000000, - 0xC880090C, - 0x00003001, + 0xD438090C, + 0x00003000, 0x90400000, 0x00000000, 0x2020C243, @@ -325,22 +325,22 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00104120, 0x00000200, 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, 0x00D00000, 0x14864000, 0x59647A05, - 0x8A28A3D5, + 0x8A28A3DD, 0xF6D1451E, 0x034AD348, 0x821A0000, 0x0000D000, 0x05140680, - 0xD569A47A, + 0xDD59647A, 0x1E8A28A3, 0x48F6D145, - 0x00035292, + 0x00034AD3, 0x00080200, 0x00001000, 0x00080200, @@ -393,27 +393,27 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x0000F200, 0x00000000, 0x00000482, - 0x00120800, - 0x00600391, + 0x70120800, + 0x006001A8, 0x80000000, 0x00104120, 0x00000200, 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, 0x00D00000, 0x14864000, 0x59647A05, - 0x8A28A3D5, - 0xF4D1451E, + 0x8A28A3DD, + 0xF6D1451E, 0x034AD348, 0x821A0186, 0x0000D000, 0x00000680, - 0xD569A47A, - 0x1EF228A3, - 0x48F4D145, + 0xDD59647A, + 0x1E8A28A3, + 0x48F6D145, 0x00034AD3, 0x00080200, 0x00001000, @@ -452,8 +452,8 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x5506A000, 0x00E1D400, 0x00000000, - 0xC880090C, - 0x00003001, + 0xD438090C, + 0x00003000, 0x90400000, 0x00000000, 0x2020C243, @@ -473,21 +473,21 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00104120, 0x00000200, 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, 0x00D00000, - 0x0C864000, - 0x59647A03, - 0xCB2CA3DD, - 0xF6D9651E, + 0x14864000, + 0x59647A05, + 0x8A28A3DD, + 0xF6D1451E, 0x034AD348, 0x821A0000, 0x0000D000, 0x00000680, 0xDD59647A, 0x1E8A28A3, - 0x48F6D965, + 0x48F6D145, 0x00034AD3, 0x00080200, 0x00001000, @@ -547,19 +547,19 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00104120, 0x00000200, 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F16080, - 0x1A041404, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, 0x00D00000, - 0x04864000, - 0x69A47A01, - 0xF228A3D5, - 0xF4D1451E, - 0x03529248, + 0x14864000, + 0x59647A05, + 0x8A28A3DD, + 0xF6D1451E, + 0x034AD348, 0x821A0000, 0x0000D000, 0x00000680, - 0xD559647A, + 0xDD59647A, 0x1E8A28A3, 0x48F6D145, 0x00034AD3, diff --git a/board/softing/vining_fpga/qts/pinmux_config.h b/board/softing/vining_fpga/qts/pinmux_config.h index 40b89123ec..f73ccbbabe 100644 --- a/board/softing/vining_fpga/qts/pinmux_config.h +++ b/board/softing/vining_fpga/qts/pinmux_config.h @@ -198,12 +198,12 @@ const u8 sys_mgr_init_table[] = { 0, /* NANDUSEFPGA */ 0, /* UART0USEFPGA */ 0, /* RGMII1USEFPGA */ - 1, /* SPIS0USEFPGA */ + 0, /* SPIS0USEFPGA */ 0, /* CAN0USEFPGA */ 0, /* I2C0USEFPGA */ 0, /* SDMMCUSEFPGA */ 0, /* QSPIUSEFPGA */ - 1, /* SPIS1USEFPGA */ + 0, /* SPIS1USEFPGA */ 1, /* RGMII0USEFPGA */ 0, /* UART1USEFPGA */ 0, /* CAN1USEFPGA */ @@ -211,7 +211,7 @@ const u8 sys_mgr_init_table[] = { 0, /* I2C3USEFPGA */ 0, /* I2C2USEFPGA */ 0, /* I2C1USEFPGA */ - 0, /* SPIM1USEFPGA */ + 1, /* SPIM1USEFPGA */ 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ }; diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h index 5d2a08ba00..fa04618336 100644 --- a/board/softing/vining_fpga/qts/pll_config.h +++ b/board/softing/vining_fpga/qts/pll_config.h @@ -13,7 +13,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 @@ -53,7 +53,7 @@ #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 #define CONFIG_HPS_CLK_OSC1_HZ 25000000 @@ -63,18 +63,12 @@ #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 #define CONFIG_HPS_CLK_EMAC1_HZ 250000000 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 488281 #define CONFIG_HPS_CLK_SDMMC_HZ 1953125 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_QSPI_HZ 320000000 #define CONFIG_HPS_CLK_SPIM_HZ 200000000 #define CONFIG_HPS_CLK_CAN0_HZ 12500000 #define CONFIG_HPS_CLK_CAN1_HZ 12500000 diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h index de9f0e4153..ec067eb473 100644 --- a/board/softing/vining_fpga/qts/sdram_config.h +++ b/board/softing/vining_fpga/qts/sdram_config.h @@ -47,7 +47,7 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 @@ -62,15 +62,15 @@ #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 @@ -149,7 +149,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b4 #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32 From 110861992f1ed1c21e0abd60f71e7f59c2462a0b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:34 +0200 Subject: [PATCH 4/5] ARM: socfpga: vining_fpga: Update environment Update board environment to match the one used in deployment. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- configs/socfpga_vining_fpga_defconfig | 2 +- include/configs/socfpga_vining_fpga.h | 106 ++++++++++++++++++++------ 2 files changed, 83 insertions(+), 25 deletions(-) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index faa4a17de5..a9c594e219 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -9,7 +9,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; else setenv bootdelay 5 ; setenv boottype norm ; fi" +CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; elif test -n \"$force_boottype\" ; then setenv bootdelay 1 ; setenv boottype \"$force_boottype\" ; setenv force_boottype ; saveenv ; else setenv bootdelay 5 ; setenv boottype norm ; fi" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index ef3221e1c8..debf3ea94b 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -11,8 +11,9 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ /* Booting Linux */ -#define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb" +#define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTCOMMAND "run selboot" +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -30,8 +31,11 @@ * B: GPIO 78 ... the button between USB A ports * * The logic: - * if button B is not pressed, boot normal Linux system immediatelly - * if button B is pressed, wait $bootdelay and boot recovery system + * if button B is pressed, boot recovery system after 10 seconds + * if force_boottype is set, boot system depending on the value in the + * $force_boottype variable after 1 second + * if button B is not pressed and force_boottype is not set, boot normal + * Linux system after 5 seconds */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -41,21 +45,36 @@ "bootscript=boot.scr\0" \ "ubimtdnr=5\0" \ "ubimtd=rootfs\0" \ - "ubipart=ubi0:rootfs\0" \ + "ubipart=ubi0:vining-fpga-rootfs\0" \ "ubisfcs=1\0" /* Default is flash at CS#1 */ \ "netdev=eth0\0" \ - "hostname=vining_fpga\0" \ + "hostname=vining_fpga\0" \ "kernel_addr_r=0x10000000\0" \ - "mtdparts_0=ff705000.spi.0:" \ + "fdt_addr_r=0x20000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0" \ + "mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */ \ "1m(u-boot)," \ "64k(env1)," \ "64k(env2)," \ "256k(softing1)," \ "256k(softing2)," \ "-(rcvrfs)\0" /* Recovery */ \ - "mtdparts_1=ff705000.spi.1:" \ - "32m(rootfs)," \ + "mtdparts_0_256m=ff705000.spi.0:" /* 256MiB(+256MiB) config */ \ + "1m(u-boot)," \ + "64k(env1)," \ + "64k(env2)," \ + "256k(softing1)," \ + "256k(softing2)," \ + "14720k(rcvrfs)," /* Recovery */ \ + "64m(rootfs)," /* Root */ \ + "-(userfs)\0" /* User */ \ + "mtdparts_1_128m=ff705000.spi.1:" /* 16MiB+128MiB SF config */ \ + "64m(rootfs)," \ "-(userfs)\0" \ + "mtdparts_1_256m=ff705000.spi.1:" /* 256MiB+256MiB SF config */ \ + "-(userfs2)\0" \ "update_filename=u-boot-with-spl-dtb.sfp\0" \ "update_qspi_offset=0x0\0" \ "update_qspi=" /* Update the QSPI firmware */ \ @@ -64,6 +83,23 @@ "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ "fi ; " \ "fi\0" \ + "sf_identify=" \ + "setenv sf_size_0 ; setenv sf_size_1 ; " \ + "sf probe 0:0 && setenv sf_size_0 ${sf_size} ; " \ + "sf probe 0:1 && setenv sf_size_1 ${sf_size} ; " \ + "if test -z \"${sf_size_1}\" ; then " \ + /* 1x256MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_256m} ; " \ + "setenv mtdparts_1 ; " \ + "elif test \"${sf_size_0}\" = \"1000000\" ; then " \ + /* 16MiB+128MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_16m} ; " \ + "setenv mtdparts_1 ${mtdparts_1_128m} ; " \ + "else " \ + /* 256MiB+256MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_256m} ; " \ + "setenv mtdparts_1 ${mtdparts_1_256m} ; " \ + "fi\0" \ "fpga_filename=output_file.rbf\0" \ "load_fpga=" /* Load FPGA bitstream */ \ "if tftp ${fpga_filename} ; then " \ @@ -80,7 +116,11 @@ "addmisc=" \ "setenv bootargs ${bootargs} ${miscargs}\0" \ "addmtd=" \ - "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \ + "if test -z \"${sf_size_1}\" ; then " \ + "setenv mtdparts \"${mtdparts_0}\" ; " \ + "else " \ + "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \ + "fi ; " \ "setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ "addargs=run addcons addmtd addmisc\0" \ "ubiload=" \ @@ -102,29 +142,47 @@ "setenv ubimtdnr 5 ; " \ "setenv mtdparts mtdparts=${mtdparts_0} ; " \ "setenv mtdids nor0=ff705000.spi.0 ; " \ - "setenv ubipart ubi0:rootfs ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ "else " \ - "setenv ubisfcs 1 ; " \ - "setenv ubimtd rootfs ; " \ - "setenv ubimtdnr 6 ; " \ - "setenv mtdparts mtdparts=${mtdparts_1} ; " \ - "setenv mtdids nor0=ff705000.spi.1 ; " \ - "setenv ubipart ubi0:rootfs ; " \ + "if test \"${sf_size_0}\" = \"1000000\" ; then "\ + /* 16MiB+128MiB SF */ \ + "setenv ubisfcs 1 ; " \ + "setenv ubimtd rootfs ; " \ + "setenv ubimtdnr 6 ; " \ + "setenv mtdparts mtdparts=${mtdparts_1} ; " \ + "setenv mtdids nor0=ff705000.spi.1 ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ + "else " \ + /* 256MiB(+256MiB) SF */ \ + "setenv ubisfcs 0 ; " \ + "setenv ubimtd rootfs ; " \ + "setenv ubimtdnr 6 ; " \ + "setenv mtdparts mtdparts=${mtdparts_0} ; " \ + "setenv mtdids nor0=ff705000.spi.0 ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ + "fi ; " \ "fi ; " \ "sf probe 0:${ubisfcs}\0" \ + "boot_kernel=" \ + "if test -z \"${sf_size_1}\" ; then " /* 1x256MiB SF */ \ + "imxtract ${kernel_addr_r} fdt@1 ${fdt_addr_r} && " \ + "fdt addr ${fdt_addr_r} && " \ + "fdt resize && " \ + "fdt set /soc/spi@ff705000/n25q00@1 status disabled && " \ + "bootm ${kernel_addr_r}:kernel@1 - ${fdt_addr_r} ; " \ + "else " \ + "bootm ${kernel_addr_r} ; " \ + "fi\0" \ "ubi_ubi=" \ - "run ubi_sfsel ubiload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run ubi_sfsel ubiload ubiargs addargs boot_kernel\0" \ "ubi_nfs=" \ - "run ubiload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run ubiload nfsargs addip addargs boot_kernel\0" \ "net_ubi=" \ - "run netload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run netload ubiargs addargs boot_kernel\0" \ "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run netload nfsargs addip addargs boot_kernel\0" \ "selboot=" /* Select from where to boot. */ \ + "run sf_identify ; " \ "if test \"${bootmode}\" = \"qspi\" ; then " \ "led all off ; " \ "if test \"${boottype}\" = \"rcvr\" ; then " \ From e6281b8ab07e0d64be3f5f829d5a3d3a08390daa Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:35 +0200 Subject: [PATCH 5/5] ARM: socfpga: vining_fpga: Extract eth1 MAC from EEPROM The EEPROM contains eth1 MAC address as well, use it. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- board/softing/vining_fpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index 1e095a4e7d..3f597fb99e 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -87,6 +87,8 @@ int misc_init_r(void) /* Set ethernet address from EEPROM. */ if (!env_get("ethaddr") && is_valid_ethaddr(&data[0x62])) eth_env_set_enetaddr("ethaddr", &data[0x62]); + if (!env_get("eth1addr") && is_valid_ethaddr(&data[0x6a])) + eth_env_set_enetaddr("eth1addr", &data[0x6a]); return 0; }