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armv7: fsl: remove sata support
Remove the old implementation in order to enable DM for sata Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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@ -10,7 +10,6 @@ obj-y += timer.o
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obj-y += fsl_epu.o
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obj-y += soc.o
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obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
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obj-$(CONFIG_SPL) += spl.o
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@ -1,41 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <ahci.h>
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#include <scsi.h>
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/* port register default value */
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#define AHCI_PORT_PHY_1_CFG 0xa003fffe
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#define AHCI_PORT_PHY_2_CFG 0x28183414
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#define AHCI_PORT_PHY_3_CFG 0x0e080e06
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#define AHCI_PORT_PHY_4_CFG 0x064a080b
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#define AHCI_PORT_PHY_5_CFG 0x2aa86470
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#define AHCI_PORT_TRANS_CFG 0x08000029
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#define SATA_ECC_REG_ADDR 0x20220520
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#define SATA_ECC_DISABLE 0x00020000
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int ls1021a_sata_init(void)
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{
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struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
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out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
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#endif
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
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out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
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out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
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out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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ahci_init((void __iomem *)AHCI_BASE_ADDR);
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scsi_scan(false);
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return 0;
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}
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@ -389,33 +389,6 @@ struct ccsr_serdes {
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u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
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};
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/* AHCI (sata) register map */
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struct ccsr_ahci {
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u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
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u32 pcfg; /* port config */
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u32 ppcfg; /* port phy1 config */
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u32 pp2c; /* port phy2 config */
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u32 pp3c; /* port phy3 config */
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u32 pp4c; /* port phy4 config */
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u32 pp5c; /* port phy5 config */
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u32 paxic; /* port AXI config */
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u32 axicc; /* AXI cache control */
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u32 axipc; /* AXI PROT control */
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u32 ptc; /* port Trans Config */
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u32 pts; /* port Trans Status */
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u32 plc; /* port link config */
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u32 plc1; /* port link config1 */
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u32 plc2; /* port link config2 */
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u32 pls; /* port link status */
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u32 pls1; /* port link status1 */
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u32 pcmdc; /* port CMD config */
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u32 ppcs; /* port phy control status */
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u32 pberr; /* port 0/1 BIST error */
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u32 cmds; /* port 0/1 CMD status error */
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};
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#define RCPM_POWMGTCSR 0x130
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#define RCPM_POWMGTCSR_SERDES_PW 0x80000000
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#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
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@ -1,10 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#ifndef __FSL_SATA_H_
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#define __FSL_SATA_H_
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int ls1021a_sata_init(void);
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#endif
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@ -11,7 +11,6 @@
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_sata.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <fsl_immap.h>
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@ -206,10 +205,6 @@ int board_init(void)
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_SCSI_AHCI_PLAT
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ls1021a_sata_init();
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#endif
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return 0;
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}
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#endif
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@ -11,7 +11,6 @@
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_sata.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <fsl_csu.h>
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@ -362,9 +361,6 @@ int config_serdes_mux(void)
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_SCSI_AHCI_PLAT
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ls1021a_sata_init();
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#endif
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#ifdef CONFIG_CHAIN_OF_TRUST
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fsl_setenv_chain_of_trust();
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#endif
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@ -11,7 +11,6 @@
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_sata.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <fsl_csu.h>
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@ -556,9 +555,6 @@ void spl_board_init(void)
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_SCSI_AHCI_PLAT
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ls1021a_sata_init();
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#endif
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#ifdef CONFIG_CHAIN_OF_TRUST
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fsl_setenv_chain_of_trust();
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#endif
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