ram: stm32mp1: migrate trace to dev or log macro
Define LOG_CATEGORY, use dev_ macro when it is possible and migrate other trace to log_ macro. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrick Delaunay
Patrick Delaunay
parent
997f7dab9d
commit
66b3b9db69
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@ -3,6 +3,8 @@
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY UCLASS_RAM
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#include <common.h>
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#include <clk.h>
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#include <log.h>
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@ -311,17 +313,17 @@ static void set_reg(const struct ddr_info *priv,
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u32 base_addr = get_base_addr(priv, base);
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const struct reg_desc *desc = ddr_registers[type].desc;
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debug("init %s\n", ddr_registers[type].name);
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log_debug("init %s\n", ddr_registers[type].name);
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for (i = 0; i < ddr_registers[type].size; i++) {
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ptr = (unsigned int *)(base_addr + desc[i].offset);
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if (desc[i].par_offset == INVALID_OFFSET) {
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pr_err("invalid parameter offset for %s", desc[i].name);
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log_err("invalid parameter offset for %s", desc[i].name);
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} else {
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value = *((u32 *)((u32)param +
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desc[i].par_offset));
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writel(value, ptr);
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debug("[0x%x] %s= 0x%08x\n",
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(u32)ptr, desc[i].name, value);
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log_debug("[0x%x] %s= 0x%08x\n",
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(u32)ptr, desc[i].name, value);
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}
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}
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}
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@ -564,16 +566,16 @@ static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
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DDRPHYC_PGSR_RVERR |
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DDRPHYC_PGSR_RVEIRR),
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1000000);
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debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
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(u32)&phy->pgsr, pgsr, ret);
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log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
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(u32)&phy->pgsr, pgsr, ret);
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}
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void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
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{
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pir |= DDRPHYC_PIR_INIT;
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writel(pir, &phy->pir);
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debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
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(u32)&phy->pir, pir, readl(&phy->pir));
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log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
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(u32)&phy->pir, pir, readl(&phy->pir));
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/* need to wait 10 configuration clock before start polling */
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udelay(10);
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@ -603,7 +605,7 @@ static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
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panic("Timeout initialising DRAM : DDR->swstat = %x\n",
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swstat);
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debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
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log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
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}
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/* wait quasi dynamic register update */
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@ -634,7 +636,7 @@ static void wait_operating_mode(struct ddr_info *priv, int mode)
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if (ret)
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panic("Timeout DRAM : DDR->stat = %x\n", stat);
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debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
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log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
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}
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void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
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@ -706,9 +708,9 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
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panic("ddr power init failed\n");
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start:
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debug("name = %s\n", config->info.name);
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debug("speed = %d kHz\n", config->info.speed);
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debug("size = 0x%x\n", config->info.size);
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log_debug("name = %s\n", config->info.name);
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log_debug("speed = %d kHz\n", config->info.speed);
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log_debug("size = 0x%x\n", config->info.size);
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/*
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* 1. Program the DWC_ddr_umctl2 registers
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* 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
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@ -745,8 +747,8 @@ start:
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/* 1.5. initialize registers ddr_umctl2 */
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/* Stop uMCTL2 before PHY is ready */
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clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
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debug("[0x%08x] dfimisc = 0x%08x\n",
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(u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
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log_debug("[0x%08x] dfimisc = 0x%08x\n",
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(u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
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set_reg(priv, REG_REG, &config->c_reg);
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set_reg(priv, REG_TIMING, &config->c_timing);
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@ -809,9 +811,9 @@ start:
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wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
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if (config->p_cal_present) {
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debug("DDR DQS training skipped.\n");
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log_debug("DDR DQS training skipped.\n");
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} else {
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debug("DDR DQS training : ");
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log_debug("DDR DQS training : ");
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/* 8. Disable Auto refresh and power down by setting
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* - RFSHCTL3.dis_au_refresh = 1
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* - PWRCTL.powerdown_en = 0
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@ -3,6 +3,8 @@
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* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY UCLASS_RAM
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#include <common.h>
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#include <command.h>
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#include <console.h>
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@ -404,7 +406,7 @@ bool stm32mp1_ddr_interactive(void *priv,
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#endif
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}
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debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
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log_debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
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if (next_step < 0)
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return false;
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@ -3,6 +3,8 @@
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY UCLASS_RAM
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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@ -12,6 +14,7 @@
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include "stm32mp1_ddr.h"
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static const char *const clkname[] = {
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@ -37,7 +40,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
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ret = clk_enable(&clk);
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if (ret) {
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printf("error for %s : %d\n", clkname[idx], ret);
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log_err("error for %s : %d\n", clkname[idx], ret);
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return ret;
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}
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}
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@ -45,13 +48,13 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
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priv->clk = clk;
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ddrphy_clk = clk_get_rate(&priv->clk);
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debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
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mem_speed, (u32)(ddrphy_clk / 1000));
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log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
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mem_speed, (u32)(ddrphy_clk / 1000));
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/* max 10% frequency delta */
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ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
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if (ddr_clk > (mem_speed * 100)) {
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pr_err("DDR expected freq %d kHz, current is %d kHz\n",
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mem_speed, (u32)(ddrphy_clk / 1000));
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log_err("DDR expected freq %d kHz, current is %d kHz\n",
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mem_speed, (u32)(ddrphy_clk / 1000));
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return -EINVAL;
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}
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@ -118,7 +121,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
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config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
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config.info.name = ofnode_read_string(node, "st,mem-name");
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if (!config.info.name) {
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debug("%s: no st,mem-name\n", __func__);
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dev_dbg(dev, "no st,mem-name\n");
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return -EINVAL;
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}
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printf("RAM: %s\n", config.info.name);
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@ -128,12 +131,12 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
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(void *)((u32)&config +
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param[idx].offset),
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param[idx].size);
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debug("%s: %s[0x%x] = %d\n", __func__,
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param[idx].name, param[idx].size, ret);
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dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
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param[idx].name, param[idx].size, ret);
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if (ret &&
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(ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
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pr_err("%s: Cannot read %s, error=%d\n",
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__func__, param[idx].name, ret);
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dev_err(dev, "Cannot read %s, error=%d\n",
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param[idx].name, ret);
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return -EINVAL;
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}
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if (param[idx].present) {
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@ -153,7 +156,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
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ret = clk_get_by_name(dev, "axidcg", &axidcg);
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if (ret) {
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debug("%s: Cannot found axidcg\n", __func__);
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dev_dbg(dev, "%s: Cannot found axidcg\n", __func__);
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return -EINVAL;
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}
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clk_disable(&axidcg); /* disable clock gating during init */
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@ -163,13 +166,13 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
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clk_enable(&axidcg); /* enable clock gating */
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/* check size */
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debug("%s : get_ram_size(%x, %x)\n", __func__,
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(u32)priv->info.base, (u32)STM32_DDR_SIZE);
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dev_dbg(dev, "get_ram_size(%x, %x)\n",
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(u32)priv->info.base, (u32)STM32_DDR_SIZE);
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priv->info.size = get_ram_size((long *)priv->info.base,
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STM32_DDR_SIZE);
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debug("%s : %x\n", __func__, (u32)priv->info.size);
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dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size);
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/* check memory access for all memory */
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if (config.info.size != priv->info.size) {
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@ -186,12 +189,11 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
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struct regmap *map;
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int ret;
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debug("STM32MP1 DDR probe\n");
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priv->dev = dev;
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ret = regmap_init_mem(dev_ofnode(dev), &map);
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if (ret)
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return ret;
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return log_ret(ret);
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priv->ctl = regmap_get_range(map, 0);
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priv->phy = regmap_get_range(map, 1);
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@ -203,7 +205,9 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
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#if !defined(CONFIG_TFABOOT) && \
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(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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priv->info.size = 0;
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return stm32mp1_ddr_setup(dev);
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ret = stm32mp1_ddr_setup(dev);
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return log_ret(ret);
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#else
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ofnode node = stm32mp1_ddr_get_ofnode(dev);
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priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
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@ -2,6 +2,9 @@
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/*
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* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY UCLASS_RAM
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#include <common.h>
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#include <console.h>
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#include <init.h>
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@ -197,8 +200,8 @@ static u32 databus(u32 *address)
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/* Read it back (immediately is okay for this test). */
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read_value = readl(address);
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debug("%x: %x <=> %x\n",
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(u32)address, read_value, pattern);
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log_debug("%x: %x <=> %x\n",
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(u32)address, read_value, pattern);
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if (read_value != pattern)
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return pattern;
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@ -252,8 +255,8 @@ static u32 *addressbus(u32 *address, u32 nb_bytes)
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for (offset = 1; (offset & mask) != 0; offset <<= 1) {
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read_value = readl(&address[offset]);
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debug("%x: %x <=> %x\n",
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(u32)&address[offset], read_value, pattern);
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log_debug("%x: %x <=> %x\n",
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(u32)&address[offset], read_value, pattern);
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if (read_value != pattern)
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return &address[offset];
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}
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@ -363,8 +366,8 @@ static enum test_result databuswalk0(struct stm32mp1_ddrctl *ctl,
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data = readl(addr + 4 * i);
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if (~(1 << i) != data) {
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error |= 1 << i;
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debug("%x: error %x expected %x => error:%x\n",
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addr + 4 * i, data, ~(1 << i), error);
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log_debug("%x: error %x expected %x => error:%x\n",
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addr + 4 * i, data, ~(1 << i), error);
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}
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}
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if (test_loop_end(&loop, nb_loop, 1000))
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@ -403,8 +406,8 @@ static enum test_result databuswalk1(struct stm32mp1_ddrctl *ctl,
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data = readl(addr + 4 * i);
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if ((1 << i) != data) {
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error |= 1 << i;
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debug("%x: error %x expected %x => error:%x\n",
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addr + 4 * i, data, (1 << i), error);
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log_debug("%x: error %x expected %x => error:%x\n",
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addr + 4 * i, data, (1 << i), error);
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}
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}
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if (test_loop_end(&loop, nb_loop, 1000))
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@ -2,6 +2,9 @@
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/*
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* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY UCLASS_RAM
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#include <common.h>
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#include <console.h>
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#include <clk.h>
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@ -227,8 +230,7 @@ static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
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index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
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& DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
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pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
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__func__, addr, readl(addr), index);
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log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index);
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return index;
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}
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@ -470,13 +472,13 @@ static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
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for (bit_i = 0; bit_i < 8; bit_i++) {
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set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
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index = DQ_unit_index(phy, byte, bit_i);
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pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
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byte, bit_i, deskew_delay[byte][bit_i],
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index, index - 3);
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log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
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byte, bit_i, deskew_delay[byte][bit_i],
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index, index - 3);
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printf("Byte %d, bit %d, DQ delay = %d",
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byte, bit_i, deskew_delay[byte][bit_i]);
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if (deskew_non_converge[byte][bit_i] == 1)
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pr_debug(" - not converged : still more skew");
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log_debug(" - not converged : still more skew");
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printf("\n");
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}
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}
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@ -536,7 +538,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
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/* Config the BIST block */
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config_BIST(ctl, phy);
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pr_debug("BIST Config done.\n");
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log_debug("BIST Config done.\n");
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/* Train each byte */
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for (datx8 = 0; datx8 < nb_bytes; datx8++) {
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@ -545,9 +547,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
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datx8 + 1, nb_bytes, error);
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return TEST_FAILED;
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}
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pr_debug("\n======================\n");
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pr_debug("Start deskew byte %d .\n", datx8);
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pr_debug("======================\n");
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log_debug("\n======================\n");
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log_debug("Start deskew byte %d .\n", datx8);
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log_debug("======================\n");
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/* Enable Byte (DXNGCR, bit DXEN) */
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setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
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@ -584,7 +586,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
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* Else, look for Pass init condition
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*/
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if (!success) {
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pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
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log_debug("Fail at init condtion. Let's look for a good init condition.\n");
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success = 0; /* init */
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/* Make sure we start with a PASS condition before
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* looking for a fail condition.
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|
@ -592,7 +594,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
*/
|
||||
|
||||
/* escape if we find a PASS */
|
||||
pr_debug("increase Phase idx\n");
|
||||
log_debug("increase Phase idx\n");
|
||||
while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
|
||||
DQS_phase_delay(phy, datx8, phase_idx);
|
||||
BIST_test(phy, datx8, &result);
|
||||
|
|
@ -618,7 +620,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
* we have hold violation, lets try reduce DQS_unit
|
||||
* Delay
|
||||
*/
|
||||
pr_debug("Still fail. Try decrease DQS Unit delay\n");
|
||||
log_debug("Still fail. Try decrease DQS Unit delay\n");
|
||||
|
||||
phase_idx = 0;
|
||||
dqs_unit_delay_index = 0;
|
||||
|
|
@ -665,9 +667,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
return TEST_FAILED;
|
||||
}
|
||||
|
||||
pr_debug("there is a pass region for phase idx %d\n",
|
||||
phase_idx);
|
||||
pr_debug("Step1: Find the first failing condition\n");
|
||||
log_debug("there is a pass region for phase idx %d\n",
|
||||
phase_idx);
|
||||
log_debug("Step1: Find the first failing condition\n");
|
||||
/* Look for the first failing condition by PHASE stepping.
|
||||
* This part of the algo can finish without converging.
|
||||
*/
|
||||
|
|
@ -692,9 +694,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
* stepping (minimal delay)
|
||||
*/
|
||||
if (!success) {
|
||||
pr_debug("Fail region (PHASE) found phase idx %d\n",
|
||||
phase_idx);
|
||||
pr_debug("Let's look for first success by DQS Unit steps\n");
|
||||
log_debug("Fail region (PHASE) found phase idx %d\n",
|
||||
phase_idx);
|
||||
log_debug("Let's look for first success by DQS Unit steps\n");
|
||||
/* This part, the algo always converge */
|
||||
phase_idx--;
|
||||
|
||||
|
|
@ -721,7 +723,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
/*+1 to get back to current condition */
|
||||
last_right_ok.unit = dqs_unit_delay_index + 1;
|
||||
last_right_ok.bits_delay = 0xFFFFFFFF;
|
||||
pr_debug("Found %d\n", dqs_unit_delay_index);
|
||||
log_debug("Found %d\n", dqs_unit_delay_index);
|
||||
} else {
|
||||
/* the last OK condition is then with the
|
||||
* previous phase_idx.
|
||||
|
|
@ -735,8 +737,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
*/
|
||||
last_right_ok.unit = 1;
|
||||
last_right_ok.bits_delay = 0xFFFFFFFF;
|
||||
pr_debug("Not Found : try previous phase %d\n",
|
||||
phase_idx - 1);
|
||||
log_debug("Not Found : try previous phase %d\n",
|
||||
phase_idx - 1);
|
||||
|
||||
DQS_phase_delay(phy, datx8, phase_idx - 1);
|
||||
dqs_unit_delay_index = 0;
|
||||
|
|
@ -749,8 +751,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
BIST_test(phy, datx8, &result);
|
||||
success = result.test_result;
|
||||
dqs_unit_delay_index++;
|
||||
pr_debug("dqs_unit_delay_index = %d, result = %d\n",
|
||||
dqs_unit_delay_index, success);
|
||||
log_debug("dqs_unit_delay_index = %d, result = %d\n",
|
||||
dqs_unit_delay_index, success);
|
||||
}
|
||||
|
||||
if (!success) {
|
||||
|
|
@ -758,7 +760,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
dqs_unit_delay_index - 1;
|
||||
} else {
|
||||
last_right_ok.unit = 0;
|
||||
pr_debug("ERROR: failed region not FOUND");
|
||||
log_debug("ERROR: failed region not FOUND");
|
||||
}
|
||||
}
|
||||
} else {
|
||||
|
|
@ -775,7 +777,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
last_right_ok.phase = MAX_DQS_PHASE_IDX;
|
||||
last_right_ok.unit = MAX_DQS_UNIT_IDX;
|
||||
last_right_ok.bits_delay = 0xFFFFFFFF;
|
||||
pr_debug("Can't find the a fail condition\n");
|
||||
log_debug("Can't find the a fail condition\n");
|
||||
}
|
||||
|
||||
/* step 2:
|
||||
|
|
@ -787,9 +789,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
*/
|
||||
printf("Byte %d, DQS unit = %d, phase = %d\n",
|
||||
datx8, last_right_ok.unit, last_right_ok.phase);
|
||||
pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
|
||||
last_right_ok.unit, last_right_ok.phase,
|
||||
last_right_ok.bits_delay);
|
||||
log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
|
||||
last_right_ok.unit, last_right_ok.phase,
|
||||
last_right_ok.bits_delay);
|
||||
|
||||
/* Restore the last_right_ok condtion. */
|
||||
DQS_unit_delay(phy, datx8, last_right_ok.unit);
|
||||
|
|
@ -812,7 +814,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
datx8 + 1, nb_bytes, error);
|
||||
return error;
|
||||
}
|
||||
pr_debug("deskewing bit %d:\n", bit_i);
|
||||
log_debug("deskewing bit %d:\n", bit_i);
|
||||
success = 1; /* init */
|
||||
/* Set all DQDLYn to maximum value.
|
||||
* Only bit_i will be down-delayed
|
||||
|
|
@ -855,10 +857,10 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
* at one bit.
|
||||
*/
|
||||
fail_found = 1;
|
||||
pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
|
||||
bit_i, bit_i_delay_index + 1,
|
||||
datx8, bit_i,
|
||||
deskew_delay[datx8][bit_i]);
|
||||
log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
|
||||
bit_i, bit_i_delay_index + 1,
|
||||
datx8, bit_i,
|
||||
deskew_delay[datx8][bit_i]);
|
||||
} else {
|
||||
/* if we can find a success condition by
|
||||
* back-delaying this bit, just set the delay
|
||||
|
|
@ -870,20 +872,20 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
* in the report.
|
||||
*/
|
||||
deskew_non_converge[datx8][bit_i] = 1;
|
||||
pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
|
||||
bit_i, datx8, bit_i,
|
||||
deskew_delay[datx8][bit_i]);
|
||||
log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
|
||||
bit_i, datx8, bit_i,
|
||||
deskew_delay[datx8][bit_i]);
|
||||
}
|
||||
}
|
||||
pr_debug("**********byte %d tuning complete************\n",
|
||||
datx8);
|
||||
log_debug("**********byte %d tuning complete************\n",
|
||||
datx8);
|
||||
/* If we can't find any failure by back delaying DQ lines,
|
||||
* hold the default values
|
||||
*/
|
||||
if (!fail_found) {
|
||||
for (bit_i = 0; bit_i < 8; bit_i++)
|
||||
deskew_delay[datx8][bit_i] = 0;
|
||||
pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
|
||||
log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
|
||||
}
|
||||
|
||||
apply_deskew_results(phy, datx8, deskew_delay,
|
||||
|
|
@ -986,7 +988,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
|
|||
dqs_unit_delay_index_pass = dqs_unit_delay_index;
|
||||
success = 0;
|
||||
|
||||
pr_debug("STEP0: Find Init delay\n");
|
||||
log_debug("STEP0: Find Init delay\n");
|
||||
/* STEP0: Find Init delay: a delay that put the system
|
||||
* in a "Pass" condition then (TODO) update
|
||||
* dqs_unit_delay_index_pass & phase_idx_pass
|
||||
|
|
@ -1035,7 +1037,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
|
|||
byte + 1, nb_bytes, error);
|
||||
return TEST_FAILED;
|
||||
}
|
||||
pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
|
||||
log_debug("STEP1: Find LEFT PHASE DQS Bound\n");
|
||||
/* STEP1: Find LEFT PHASE DQS Bound */
|
||||
while ((phase_idx >= 0) &&
|
||||
(phase_idx <= MAX_DQS_PHASE_IDX) &&
|
||||
|
|
@ -1069,7 +1071,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
|
|||
byte + 1, nb_bytes, error);
|
||||
return TEST_FAILED;
|
||||
}
|
||||
pr_debug("STEP2: Find UNIT left bound\n");
|
||||
log_debug("STEP2: Find UNIT left bound\n");
|
||||
/* STEP2: Find UNIT left bound */
|
||||
while ((dqs_unit_delay_index >= 0) &&
|
||||
!left_unit_bound_found) {
|
||||
|
|
@ -1097,7 +1099,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
|
|||
byte + 1, nb_bytes, error);
|
||||
return TEST_FAILED;
|
||||
}
|
||||
pr_debug("STEP3: Find PHase right bound\n");
|
||||
log_debug("STEP3: Find PHase right bound\n");
|
||||
/* STEP3: Find PHase right bound, start with "pass"
|
||||
* condition
|
||||
*/
|
||||
|
|
@ -1135,7 +1137,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
|
|||
byte + 1, nb_bytes, error);
|
||||
return TEST_FAILED;
|
||||
}
|
||||
pr_debug("STEP4: Find UNIT right bound\n");
|
||||
log_debug("STEP4: Find UNIT right bound\n");
|
||||
/* STEP4: Find UNIT right bound */
|
||||
while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
|
||||
!right_unit_bound_found) {
|
||||
|
|
@ -1174,12 +1176,12 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
|
|||
if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
|
||||
eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
|
||||
eye_training_val[byte][1]++;
|
||||
pr_debug("** found phase : %d - %d & unit %d - %d\n",
|
||||
right_bound.phase, left_bound.phase,
|
||||
right_bound.unit, left_bound.unit);
|
||||
pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
|
||||
eye_training_val[byte][0],
|
||||
eye_training_val[byte][1]);
|
||||
log_debug("** found phase : %d - %d & unit %d - %d\n",
|
||||
right_bound.phase, left_bound.phase,
|
||||
right_bound.unit, left_bound.unit);
|
||||
log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
|
||||
eye_training_val[byte][0],
|
||||
eye_training_val[byte][1]);
|
||||
} else {
|
||||
/* PPPPPPPPPP, we're already good.
|
||||
* Set nominal values.
|
||||
|
|
@ -1280,11 +1282,11 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
|
|||
* or pppppff or ffppppp
|
||||
*/
|
||||
if (left_bound_found || right_bound_found) {
|
||||
pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
|
||||
left_bound_found,
|
||||
right_bound_idx[0], left_bound_idx[0],
|
||||
right_bound_found,
|
||||
right_bound_idx[1], left_bound_idx[1]);
|
||||
log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
|
||||
left_bound_found,
|
||||
right_bound_idx[0], left_bound_idx[0],
|
||||
right_bound_found,
|
||||
right_bound_idx[1], left_bound_idx[1]);
|
||||
dqs_gate_values[byte][0] =
|
||||
(right_bound_idx[0] + left_bound_idx[0]) / 2;
|
||||
dqs_gate_values[byte][1] =
|
||||
|
|
@ -1319,14 +1321,14 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
|
|||
left_bound_idx[0];
|
||||
}
|
||||
}
|
||||
pr_debug("*******calculating mid region: system latency: %d phase: %d********\n",
|
||||
dqs_gate_values[byte][0],
|
||||
dqs_gate_values[byte][1]);
|
||||
pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
|
||||
log_debug("*******calculating mid region: system latency: %d phase: %d********\n",
|
||||
dqs_gate_values[byte][0],
|
||||
dqs_gate_values[byte][1]);
|
||||
log_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
|
||||
}
|
||||
} else {
|
||||
/* if intermitant, restore defaut values */
|
||||
pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
|
||||
log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
|
||||
dqs_gate_values[byte][0] = 0;
|
||||
dqs_gate_values[byte][1] = 2;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue