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https://github.com/brain-hackers/u-boot-brain
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dts: mtmips: update reset controller node for mt7628
This patch updates reset controller node for mt7628 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
parent
f7ae6b682c
commit
6658ebc96a
@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/mt7628-clk.h>
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#include <dt-bindings/reset/mt7628-reset.h>
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/ {
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#address-cells = <1>;
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@ -17,11 +18,6 @@
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};
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};
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resetc: reset-controller {
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compatible = "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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@ -57,6 +53,12 @@
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u-boot,dm-pre-reloc;
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};
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rstctrl: rstctrl@0x34 {
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reg = <0x34 0x4>;
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compatible = "mediatek,mtmips-reset";
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#reset-cells = <1>;
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};
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pinctrl: pinctrl@60 {
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compatible = "mediatek,mt7628-pinctrl";
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reg = <0x3c 0x2c>, <0x1300 0x100>;
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@ -211,7 +213,7 @@
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compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
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reg = <0x100 0x30>;
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resets = <&resetc 8>;
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resets = <&rstctrl MT7628_TIMER_RST>;
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reset-names = "wdt";
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interrupt-parent = <&intc>;
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@ -225,7 +227,7 @@
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interrupt-controller;
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#interrupt-cells = <1>;
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resets = <&resetc 9>;
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resets = <&rstctrl MT7628_INT_RST>;
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reset-names = "intc";
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interrupt-parent = <&cpuintc>;
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@ -248,6 +250,9 @@
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compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
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reg = <0x600 0x100>;
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resets = <&rstctrl MT7628_PIO_RST>;
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reset-names = "pio";
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interrupt-parent = <&intc>;
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interrupts = <6>;
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@ -276,6 +281,10 @@
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spi0: spi@b00 {
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x40>;
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resets = <&rstctrl MT7628_SPI_RST>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -291,7 +300,7 @@
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clocks = <&clkctrl CLK_UART0>;
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resets = <&resetc 12>;
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resets = <&rstctrl MT7628_UART0_RST>;
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reset-names = "uart0";
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interrupt-parent = <&intc>;
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@ -309,7 +318,7 @@
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clocks = <&clkctrl CLK_UART1>;
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resets = <&resetc 19>;
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resets = <&rstctrl MT7628_UART1_RST>;
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reset-names = "uart1";
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interrupt-parent = <&intc>;
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@ -327,7 +336,7 @@
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clocks = <&clkctrl CLK_UART2>;
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resets = <&resetc 20>;
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resets = <&rstctrl MT7628_UART2_RST>;
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reset-names = "uart2";
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interrupt-parent = <&intc>;
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@ -342,6 +351,9 @@
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reg = <0x10100000 0x10000
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0x10110000 0x8000>;
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resets = <&rstctrl MT7628_EPHY_RST>;
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reset-names = "ephy";
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syscon = <&sysc>;
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};
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@ -353,8 +365,8 @@
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ralink,sysctl = <&sysc>;
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resets = <&resetc 22 &resetc 25>;
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reset-names = "host", "device";
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resets = <&rstctrl MT7628_UPHY_RST>;
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reset-names = "phy";
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clocks = <&clkctrl CLK_UPHY>;
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clock-names = "cg";
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