mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-27 23:20:26 +09:00
Merge branch '2021-03-19-assorted-fixes'
- NVMe cache fixes, API bugfix with !CONFIG_SYS_64BIT_LBA, ahci mediatek fix when debugging, ti-sysc uclass fix, sl28 MMC boot fix
This commit is contained in:
commit
65f2e55b57
@ -70,7 +70,7 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
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CONFIG_I2C_DEFAULT_BUS_NUMBER=0
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CONFIG_I2C_DEFAULT_BUS_NUMBER=0
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CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX=y
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CONFIG_DM_MMC=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
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CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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@ -21,6 +21,7 @@
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#include <sata.h>
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#include <sata.h>
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#include <scsi.h>
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#include <scsi.h>
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#include <syscon.h>
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#include <syscon.h>
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#include <dm/device_compat.h>
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#define SYS_CFG 0x14
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#define SYS_CFG 0x14
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#define SYS_CFG_SATA_MSK GENMASK(31, 30)
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#define SYS_CFG_SATA_MSK GENMASK(31, 30)
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@ -148,12 +148,6 @@ clocks_err:
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return err;
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return err;
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}
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}
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UCLASS_DRIVER(ti_sysc) = {
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.id = UCLASS_SIMPLE_BUS,
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.name = "ti_sysc",
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.post_bind = dm_scan_fdt_dev
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};
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U_BOOT_DRIVER(ti_sysc) = {
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U_BOOT_DRIVER(ti_sysc) = {
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.name = "ti_sysc",
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.name = "ti_sysc",
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.id = UCLASS_SIMPLE_BUS,
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.id = UCLASS_SIMPLE_BUS,
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@ -22,6 +22,8 @@
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#define NVME_AQ_DEPTH 2
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#define NVME_AQ_DEPTH 2
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#define NVME_SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
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#define NVME_SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
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#define NVME_CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
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#define NVME_CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
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#define NVME_CQ_ALLOCATION ALIGN(NVME_CQ_SIZE(NVME_Q_DEPTH), \
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ARCH_DMA_MINALIGN)
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#define ADMIN_TIMEOUT 60
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#define ADMIN_TIMEOUT 60
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#define IO_TIMEOUT 30
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#define IO_TIMEOUT 30
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#define MAX_PRP_POOL 512
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#define MAX_PRP_POOL 512
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@ -144,8 +146,14 @@ static __le16 nvme_get_cmd_id(void)
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static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index)
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static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index)
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{
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{
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u64 start = (ulong)&nvmeq->cqes[index];
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/*
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u64 stop = start + sizeof(struct nvme_completion);
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* Single CQ entries are always smaller than a cache line, so we
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* can't invalidate them individually. However CQ entries are
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* read only by the CPU, so it's safe to always invalidate all of them,
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* as the cache line should never become dirty.
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*/
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ulong start = (ulong)&nvmeq->cqes[0];
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ulong stop = start + NVME_CQ_ALLOCATION;
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invalidate_dcache_range(start, stop);
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invalidate_dcache_range(start, stop);
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@ -241,7 +249,7 @@ static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev,
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return NULL;
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return NULL;
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memset(nvmeq, 0, sizeof(*nvmeq));
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memset(nvmeq, 0, sizeof(*nvmeq));
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nvmeq->cqes = (void *)memalign(4096, NVME_CQ_SIZE(depth));
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nvmeq->cqes = (void *)memalign(4096, NVME_CQ_ALLOCATION);
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if (!nvmeq->cqes)
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if (!nvmeq->cqes)
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goto free_nvmeq;
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goto free_nvmeq;
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memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(depth));
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memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(depth));
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@ -339,7 +347,7 @@ static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
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nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
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nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
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memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(nvmeq->q_depth));
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memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(nvmeq->q_depth));
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flush_dcache_range((ulong)nvmeq->cqes,
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flush_dcache_range((ulong)nvmeq->cqes,
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(ulong)nvmeq->cqes + NVME_CQ_SIZE(nvmeq->q_depth));
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(ulong)nvmeq->cqes + NVME_CQ_ALLOCATION);
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dev->online_queues++;
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dev->online_queues++;
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}
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}
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@ -481,6 +489,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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dma_addr_t dma_addr, u32 *result)
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dma_addr_t dma_addr, u32 *result)
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{
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{
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struct nvme_command c;
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struct nvme_command c;
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int ret;
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memset(&c, 0, sizeof(c));
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memset(&c, 0, sizeof(c));
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c.features.opcode = nvme_admin_get_features;
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c.features.opcode = nvme_admin_get_features;
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@ -488,12 +497,20 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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c.features.prp1 = cpu_to_le64(dma_addr);
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c.features.prp1 = cpu_to_le64(dma_addr);
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c.features.fid = cpu_to_le32(fid);
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c.features.fid = cpu_to_le32(fid);
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ret = nvme_submit_admin_cmd(dev, &c, result);
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/*
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/*
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* TODO: add cache invalidate operation when the size of
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* TODO: Add some cache invalidation when a DMA buffer is involved
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* the DMA buffer is known
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* in the request, here and before the command gets submitted. The
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* buffer size varies by feature, also some features use a different
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* field in the command packet to hold the buffer address.
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* Section 5.21.1 (Set Features command) in the NVMe specification
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* details the buffer requirements for each feature.
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*
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* At the moment there is no user of this function.
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*/
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*/
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return nvme_submit_admin_cmd(dev, &c, result);
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return ret;
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}
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}
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int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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@ -508,8 +525,14 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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c.features.dword11 = cpu_to_le32(dword11);
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c.features.dword11 = cpu_to_le32(dword11);
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/*
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/*
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* TODO: add cache flush operation when the size of
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* TODO: Add a cache clean (aka flush) operation when a DMA buffer is
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* the DMA buffer is known
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* involved in the request. The buffer size varies by feature, also
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* some features use a different field in the command packet to hold
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* the buffer address. Section 5.21.1 (Set Features command) in the
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* NVMe specification details the buffer requirements for each
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* feature.
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* At the moment the only user of this function is not using
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* any DMA buffer at all.
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*/
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*/
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return nvme_submit_admin_cmd(dev, &c, result);
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return nvme_submit_admin_cmd(dev, &c, result);
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@ -70,12 +70,25 @@ struct sys_info {
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int mr_no; /* number of memory regions */
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int mr_no; /* number of memory regions */
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};
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};
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#undef CONFIG_SYS_64BIT_LBA
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/*
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#ifdef CONFIG_SYS_64BIT_LBA
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* FIXME: Previously this code was:
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typedef u_int64_t lbasize_t;
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*
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#else
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* #undef CONFIG_SYS_64BIT_LBA
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* #ifdef CONFIG_SYS_64BIT_LBA
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* typedef u_int64_t lbasize_t;
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* #else
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* typedef unsigned long lbasize_t;
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* #endif
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*
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* But we cannot just undefine CONFIG_SYS_64BIT_LBA, because then in
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* api/api_storage.c the type signature of lbaint_t will be different if
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* CONFIG_SYS_64BIT_LBA is enabled for the board, which can result in various
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* bugs.
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* So simply define lbasize_t as an unsigned long, since this was what was done
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* anyway for at least 13 years, but don't undefine CONFIG_SYS_64BIT_LBA.
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*/
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typedef unsigned long lbasize_t;
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typedef unsigned long lbasize_t;
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#endif
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typedef unsigned long lbastart_t;
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typedef unsigned long lbastart_t;
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#define DEV_TYP_NONE 0x0000
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#define DEV_TYP_NONE 0x0000
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