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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
* Patch by Rune Torgersen, 17 Sep 2003:
- Fixes for MPC8266 default config - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
This commit is contained in:
wdenk
parent
206c60cbea
commit
65bd0e284b
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@ -4,6 +4,7 @@ Changes for U-Boot 1.0.0:
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* Patch by Rune Torgersen, 17 Sep 2003:
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- Fixes for MPC8266 default config
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- Allow eth_loopback_test() on 8260 to use a subset of the FCC's
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* Patches by Jon Diekema, 17 Sep 2003:
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- update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
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@ -427,7 +427,7 @@ long int initdram(int board_type)
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bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
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sda10 = sdam + 2;
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#else
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sdam = cols - 6;
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sdam = cols + banks - 8;
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bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
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sda10 = sdam;
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#endif
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@ -557,9 +557,18 @@ long int initdram(int board_type)
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printf("SDRAM configuration read from SPD\n");
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printf("\tSize per side = %dMB\n", sdram_size >> 20);
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printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
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printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);
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printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
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#if(CONFIG_PBI == 0) /* bank-based interleaving */
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printf(", Using Bank Based Interleave\n");
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#else
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printf(", Using Page Based Interleave\n");
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#endif
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printf("\tTotal size: ");
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/* this delay only needed for original 16MB DIMM...
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* Not needed for any other memory configuration */
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if ((sdram_size * chipselects) == (16 *1024 *1024))
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udelay (250000);
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return (sdram_size * chipselects);
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/*return (16 * 1024 * 1024);*/
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}
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@ -575,3 +584,4 @@ void pci_init_board(void)
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pci_mpc8250_init(&hose);
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}
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#endif
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@ -650,6 +650,15 @@ eth_loopback_test (void)
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/* 28.9 - (1-2): ioports have been set up already */
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#if defined(CONFIG_HYMOD)
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/*
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* Attention: this is board-specific
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* 0, FCC1
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* 1, FCC2
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* 2, FCC3
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*/
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# define FCC_START_LOOP 0
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# define FCC_END_LOOP 2
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/*
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* Attention: this is board-specific
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* - FCC1 Rx-CLK is CLK10
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@ -665,13 +674,30 @@ eth_loopback_test (void)
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immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
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CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
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CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
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#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng)
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/*
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* Attention: this is board-specific
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* 1, FCC2
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*/
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# define FCC_START_LOOP 1
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# define FCC_END_LOOP 1
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/*
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* Attention: this is board-specific
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* - FCC2 Rx-CLK is CLK13
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* - FCC2 Tx-CLK is CLK14
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*/
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/* 28.9 - (3): connect FCC's tx and rx clocks */
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immr->im_cpmux.cmx_uar = 0;
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immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
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#else
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#error "eth_loopback_test not supported on your board"
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#endif
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puts ("Initialise FCC channels:");
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for (c = 0; c < 3; c++) {
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for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
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elbt_chan *ecp = &elbt_chans[c];
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volatile fcc_t *fcp = &immr->im_fcc[c];
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volatile fcc_enet_t *fpp;
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@ -853,7 +879,7 @@ eth_loopback_test (void)
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do {
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nclosed = 0;
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for (c = 0; c < 3; c++) {
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for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
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volatile fcc_t *fcp = &immr->im_fcc[c];
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elbt_chan *ecp = &elbt_chans[c];
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int i;
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@ -1082,7 +1108,7 @@ eth_loopback_test (void)
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}
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}
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} while (nclosed < 3);
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} while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
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runtime = get_timer (runtime);
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if (runtime <= ELBT_CLSWAIT) {
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@ -1099,7 +1125,7 @@ eth_loopback_test (void)
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* now print stats
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*/
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for (c = 0; c < 3; c++) {
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for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
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elbt_chan *ecp = &elbt_chans[c];
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uint rxpps, txpps, nerr;
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@ -1131,17 +1157,17 @@ eth_loopback_test (void)
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}
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puts ("Receive Error Counts:\n");
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for (c = 0; c < 3; c++)
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for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
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bases[c] = (uchar *)&elbt_chans[c].rxeacc;
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print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
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puts ("\nTransmit Error Counts:\n");
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for (c = 0; c < 3; c++)
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for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
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bases[c] = (uchar *)&elbt_chans[c].txeacc;
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print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
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puts ("\nRMON(-like) Counters:\n");
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for (c = 0; c < 3; c++)
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for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
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bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
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print_desc (epram_descs, epram_ndesc, bases, 3);
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}
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@ -508,7 +508,8 @@
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#define CFG_MPTPR 0x00001900
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#define CFG_PSRT 0x00000021
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#define CFG_RESET_ADDRESS 0x04400000
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/* This address must not exist */
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#define CFG_RESET_ADDRESS 0xFCFFFF00
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/* PCI Memory map (if different from default map */
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#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
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@ -1,38 +1,38 @@
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/*----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| File Name: miiphy.h
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| File Name: miiphy.h
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| Function: Include file defining PHY registers.
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| Function: Include file defining PHY registers.
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| Author: Mark Wisner
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 04-May-99 Created MKW
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| 07-Jul-99 Added full duplex support MKW
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| 08-Sep-01 Tweaks gvb
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| Date Description of Change BY
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| --------- --------------------- ---
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| 04-May-99 Created MKW
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| 07-Jul-99 Added full duplex support MKW
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| 08-Sep-01 Tweaks gvb
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+----------------------------------------------------------------------------*/
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#ifndef _miiphy_h_
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@ -49,35 +49,35 @@ int miiphy_duplex(unsigned char addr);
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/* phy seed setup */
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#define AUTO 99
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#define _100BASET 100
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#define _10BASET 10
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#define HALF 22
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#define FULL 44
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#define AUTO 99
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#define _100BASET 100
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#define _10BASET 10
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#define HALF 22
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#define FULL 44
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/* phy register offsets */
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#define PHY_BMCR 0x00
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#define PHY_BMCR 0x00
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#define PHY_BMSR 0x01
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#define PHY_PHYIDR1 0x02
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#define PHY_PHYIDR2 0x03
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#define PHY_PHYIDR1 0x02
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#define PHY_PHYIDR2 0x03
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#define PHY_ANAR 0x04
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#define PHY_ANLPAR 0x05
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#define PHY_ANLPAR 0x05
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#define PHY_ANER 0x06
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#define PHY_ANNPTR 0x07
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#define PHY_PHYSTS 0x10
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#define PHY_MIPSCR 0x11
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#define PHY_MIPGSR 0x12
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#define PHY_DCR 0x13
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#define PHY_ANNPTR 0x07
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#define PHY_PHYSTS 0x10
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#define PHY_MIPSCR 0x11
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#define PHY_MIPGSR 0x12
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#define PHY_DCR 0x13
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#define PHY_FCSCR 0x14
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#define PHY_RECR 0x15
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#define PHY_PCSR 0x16
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#define PHY_LBR 0x17
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#define PHY_10BTSCR 0x18
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#define PHY_PHYCTRL 0x19
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#define PHY_LBR 0x17
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#define PHY_10BTSCR 0x18
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#define PHY_PHYCTRL 0x19
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/* PHY BMCR */
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOP 0x4000
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOP 0x4000
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#define PHY_BMCR_100MB 0x2000
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#define PHY_BMCR_AUTON 0x1000
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#define PHY_BMCR_POWD 0x0800
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@ -103,11 +103,11 @@ int miiphy_duplex(unsigned char addr);
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/*phy ANLPAR */
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#define PHY_ANLPAR_NP 0x8000
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#define PHY_ANLPAR_ACK 0x4000
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#define PHY_ANLPAR_RF 0x2000
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#define PHY_ANLPAR_T4 0x0200
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#define PHY_ANLPAR_TXFD 0x0100
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#define PHY_ANLPAR_TX 0x0080
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#define PHY_ANLPAR_RF 0x2000
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#define PHY_ANLPAR_T4 0x0200
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#define PHY_ANLPAR_TXFD 0x0100
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#define PHY_ANLPAR_TX 0x0080
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#define PHY_ANLPAR_10FD 0x0040
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#define PHY_ANLPAR_10 0x0020
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#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
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#define PHY_ANLPAR_10 0x0020
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#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
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#endif
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