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powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8641HPCN board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -53,12 +53,7 @@ struct law_entry law_table[] = {
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#if !defined(CONFIG_SPD_EEPROM)
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#if !defined(CONFIG_SPD_EEPROM)
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
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#endif
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#endif
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#ifdef CONFIG_PCI
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#if defined(CONFIG_RIO)
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
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#elif defined(CONFIG_RIO)
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SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
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SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
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#endif
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#endif
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SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
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SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
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@ -127,64 +127,18 @@ fixed_sdram(void)
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}
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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#if defined(CONFIG_PCI)
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif /* CONFIG_PCIE2 */
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int first_free_busno = 0;
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void pci_init_board(void)
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void pci_init_board(void)
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{
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{
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struct fsl_pci_info pci_info[2];
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fsl_pcie_init_board(0);
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int pcie_ep;
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int num = 0;
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#ifdef CONFIG_PCIE1
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#ifdef CONFIG_PCIE1
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint devdisr = in_be32(&gur->devdisr);
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int pcie_configured = is_serdes_configured(PCIE1);
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if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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/*
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/*
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* Activate ULI1575 legacy chip by performing a fake
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* Activate ULI1575 legacy chip by performing a fake
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* memory access. Needed to make ULI RTC work.
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* memory access. Needed to make ULI RTC work.
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*/
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*/
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in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
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in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
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+ CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
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+ CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
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} else {
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puts("PCIE1: disabled\n");
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}
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#else
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puts("PCIE1: disabled\n");
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#endif /* CONFIG_PCIE1 */
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf("PCIE2: connected as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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#else
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puts("PCIE2: disabled\n");
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#endif /* CONFIG_PCIE2 */
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}
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}
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@ -332,6 +332,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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* Addresses are mapped 1-1.
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* Addresses are mapped 1-1.
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*/
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*/
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#define CONFIG_SYS_PCIE1_NAME "ULI"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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