mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 23:50:26 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
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commit
64ace0d1e5
@ -304,9 +304,11 @@ void env_relocate_spec (void)
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crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
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crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
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if(!crc1_ok && !crc2_ok)
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if(!crc1_ok && !crc2_ok) {
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free(tmp_env1);
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free(tmp_env2);
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return use_default();
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else if(crc1_ok && !crc2_ok)
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} else if(crc1_ok && !crc2_ok)
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gd->env_valid = 1;
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else if(!crc1_ok && crc2_ok)
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gd->env_valid = 2;
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@ -28,6 +28,8 @@
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int nand_curr_device = -1;
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nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
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@ -46,6 +48,8 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
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if (nand_scan(mtd, 1) == 0) {
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if (!mtd->name)
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mtd->name = (char *)default_nand_name;
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else
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mtd->name += gd->reloc_off;
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} else
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mtd->name = NULL;
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} else {
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@ -75,6 +75,17 @@
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#include <jffs2/jffs2.h>
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#endif
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/*
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* CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
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* a flash. NAND flash is initialized prior to interrupts so standard timers
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* can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
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* which is greater than (max NAND reset time / NAND status read time).
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* A conservative default of 200000 (500 us / 25 ns) is used as a default.
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*/
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#ifndef CONFIG_SYS_NAND_RESET_CNT
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#define CONFIG_SYS_NAND_RESET_CNT 200000
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#endif
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/* Define default oob placement schemes for large and small page devices */
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static struct nand_ecclayout nand_oob_8 = {
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.eccbytes = 3,
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@ -524,6 +535,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
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{
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register struct nand_chip *chip = mtd->priv;
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int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
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uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
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/*
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* Write out the command to the device.
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@ -590,7 +602,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
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NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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chip->cmd_ctrl(mtd,
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NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
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while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
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(rst_sts_cnt--));
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return;
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/* This applies to read commands */
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@ -626,6 +639,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
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int column, int page_addr)
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{
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register struct nand_chip *chip = mtd->priv;
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uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
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/* Emulate NAND_CMD_READOOB */
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if (command == NAND_CMD_READOOB) {
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@ -696,7 +710,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
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NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
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chip->cmd_ctrl(mtd, NAND_CMD_NONE,
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NAND_NCE | NAND_CTRL_CHANGE);
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while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
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while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
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(rst_sts_cnt--));
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return;
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case NAND_CMD_RNDOUT:
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@ -2618,7 +2633,9 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips)
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type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
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if (IS_ERR(type)) {
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#ifndef CONFIG_SYS_NAND_QUIET_TEST
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printk(KERN_WARNING "No NAND device found!!!\n");
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#endif
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chip->select_chip(mtd, -1);
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return PTR_ERR(type);
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}
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