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powerpc/85xx:Fix IVORs addr after vector table relocation

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After relocation of vector table in SDRAM's lower address, IVORs value should
be updated with new handler addresses.

As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs
are updated with 0x100, 0x200,....f00  hard-coded values.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Prabhakar Kushwaha 2012-02-14 22:49:49 +00:00 committed by Andy Fleming
parent a4107f8617
commit 64829baf04
1 changed files with 33 additions and 0 deletions
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33
arch/powerpc/cpu/mpc85xx/start.S
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@ -1493,6 +1493,39 @@ trap_init:
cmplw 0,r7,r8
blt 2b
/* Update IVORs as per relocated vector table address */
li r7,0x0100
mtspr IVOR0,r7 /* 0: Critical input */
li r7,0x0200
mtspr IVOR1,r7 /* 1: Machine check */
li r7,0x0300
mtspr IVOR2,r7 /* 2: Data storage */
li r7,0x0400
mtspr IVOR3,r7 /* 3: Instruction storage */
li r7,0x0500
mtspr IVOR4,r7 /* 4: External interrupt */
li r7,0x0600
mtspr IVOR5,r7 /* 5: Alignment */
li r7,0x0700
mtspr IVOR6,r7 /* 6: Program check */
li r7,0x0800
mtspr IVOR7,r7 /* 7: floating point unavailable */
li r7,0x0900
mtspr IVOR8,r7 /* 8: System call */
/* 9: Auxiliary processor unavailable(unsupported) */
li r7,0x0a00
mtspr IVOR10,r7 /* 10: Decrementer */
li r7,0x0b00
mtspr IVOR11,r7 /* 11: Interval timer */
li r7,0x0c00
mtspr IVOR12,r7 /* 12: Watchdog timer */
li r7,0x0d00
mtspr IVOR13,r7 /* 13: Data TLB error */
li r7,0x0e00
mtspr IVOR14,r7 /* 14: Instruction TLB error */
li r7,0x0f00
mtspr IVOR15,r7 /* 15: Debug */
lis r7,0x0
mtspr IVPR,r7