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x86: timer: Reduce timer code size in TPL on Intel CPUs

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Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.

Note that version 1 of this commit caused bootstage to crash since the CPU
was not identified. This is corrected by changes previously applied to
make sure that the CPU is identified before spl_init() is called, such as

   39146a2e0b x86: Move CPU init to before spl_init()

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2019-12-06 21:41:50 -07:00 committed by Bin Meng
parent 77dd7c6854
commit 642e8487ec
2 changed files with 14 additions and 2 deletions
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9
drivers/timer/Kconfig
View File

@ -188,6 +188,15 @@ config X86_TSC_READ_BASE
The only exception is when U-Boot is used as a secondary bootloader,
where this option should be enabled.
config TPL_X86_TSC_TIMER_NATIVE
bool "x86 TSC timer uses native calibration"
depends on TPL && X86_TSC_TIMER
help
Selects native timer calibration for TPL and don't include the other
methods in the code. This helps to reduce code size in TPL and works
on fairly modern Intel chips. Code-size reductions is about 700
bytes.
config MTK_TIMER
bool "MediaTek timer support"
depends on TIMER

7
drivers/timer/tsc_timer.c
View File

@ -50,8 +50,7 @@ static unsigned long native_calibrate_tsc(void)
return 0;
crystal_freq = tsc_info.ecx / 1000;
if (!crystal_freq) {
if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
switch (gd->arch.x86_model) {
case INTEL_FAM6_SKYLAKE_MOBILE:
case INTEL_FAM6_SKYLAKE_DESKTOP:
@ -407,6 +406,10 @@ static void tsc_timer_ensure_setup(bool early)
if (fast_calibrate)
goto done;
/* Reduce code size by dropping other methods */
if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
panic("no timer");
fast_calibrate = cpu_mhz_from_cpuid();
if (fast_calibrate)
goto done;