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ram: rk3399: Fix code warnings
Fix checkpatch warninigs on sdram_rk3399.c like - Avoid CamelCase - Unnecessary parentheses - Alignment should match open parenthesis - multiple blank lines - misspelled - spaces preferred around that '>>' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki
Kever Yang
parent
f78b2ca453
commit
63f4d716b1
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@ -47,7 +47,7 @@ struct dram_info {
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#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
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#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
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#define PHY_DRV_ODT_Hi_Z 0x0
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#define PHY_DRV_ODT_HI_Z 0x0
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#define PHY_DRV_ODT_240 0x1
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#define PHY_DRV_ODT_120 0x8
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#define PHY_DRV_ODT_80 0x9
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@ -150,7 +150,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
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((16 - row) << 24));
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/* PI_41 PI_CS_MAP:RW:24:4 */
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clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
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if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3))
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if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)
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writel(0x2EC7FFFF, &denali_pi[34]);
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}
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@ -166,10 +166,10 @@ static void set_ds_odt(const struct chan_info *chan,
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u32 reg_value;
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if (sdram_params->base.dramtype == LPDDR4) {
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tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
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tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
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tsel_wr_select_p = PHY_DRV_ODT_40;
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ca_tsel_wr_select_p = PHY_DRV_ODT_40;
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tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
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tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
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tsel_rd_select_n = PHY_DRV_ODT_240;
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tsel_wr_select_n = PHY_DRV_ODT_40;
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@ -181,10 +181,10 @@ static void set_ds_odt(const struct chan_info *chan,
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ca_tsel_wr_select_p = PHY_DRV_ODT_48;
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tsel_idle_select_p = PHY_DRV_ODT_240;
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tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
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tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
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tsel_wr_select_n = PHY_DRV_ODT_34_3;
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ca_tsel_wr_select_n = PHY_DRV_ODT_48;
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tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
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tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
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} else {
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tsel_rd_select_p = PHY_DRV_ODT_240;
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tsel_wr_select_p = PHY_DRV_ODT_34_3;
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@ -294,7 +294,7 @@ static void set_ds_odt(const struct chan_info *chan,
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}
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static int phy_io_config(const struct chan_info *chan,
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const struct rk3399_sdram_params *sdram_params)
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const struct rk3399_sdram_params *sdram_params)
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{
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u32 *denali_phy = chan->publ->denali_phy;
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u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
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@ -423,7 +423,6 @@ static int phy_io_config(const struct chan_info *chan,
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/* PHY_939 PHY_PAD_CS_DRIVE */
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clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
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/* speed setting */
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if (sdram_params->base.ddr_freq < 400)
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speed = 0x0;
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@ -492,7 +491,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
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setbits_le32(&denali_pi[0], START);
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setbits_le32(&denali_ctl[0], START);
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/* Wating for phy DLL lock */
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/* Waiting for phy DLL lock */
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while (1) {
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tmp = readl(&denali_phy[920]);
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tmp1 = readl(&denali_phy[921]);
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@ -547,12 +546,12 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
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/* PHY_DLL_RST_EN */
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clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
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/* Wating for PHY and DRAM init complete */
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/* Waiting for PHY and DRAM init complete */
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tmp = get_timer(0);
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do {
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if (get_timer(tmp) > timeout_ms) {
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pr_err("DRAM (%s): phy failed to lock within %ld ms\n",
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__func__, timeout_ms);
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__func__, timeout_ms);
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return -ETIME;
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}
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} while (!(readl(&denali_ctl[203]) & (1 << 3)));
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@ -569,7 +568,7 @@ static void select_per_cs_training_index(const struct chan_info *chan,
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u32 *denali_phy = chan->publ->denali_phy;
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/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
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if ((readl(&denali_phy[84])>>16) & 1) {
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if ((readl(&denali_phy[84]) >> 16) & 1) {
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/*
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* PHY_8/136/264/392
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* phy_per_cs_training_index_X 1bit offset_24
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@ -646,7 +645,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
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if ((((tmp >> 11) & 0x1) == 0x1) &&
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(((tmp >> 13) & 0x1) == 0x1) &&
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(((tmp >> 5) & 0x1) == 0x0) &&
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(obs_err == 0))
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obs_err == 0)
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break;
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else if ((((tmp >> 5) & 0x1) == 0x1) ||
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(obs_err == 1))
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@ -700,7 +699,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
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if ((((tmp >> 10) & 0x1) == 0x1) &&
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(((tmp >> 13) & 0x1) == 0x1) &&
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(((tmp >> 4) & 0x1) == 0x0) &&
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(obs_err == 0))
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obs_err == 0)
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break;
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else if ((((tmp >> 4) & 0x1) == 0x1) ||
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(obs_err == 1))
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@ -759,7 +758,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
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if ((((tmp >> 9) & 0x1) == 0x1) &&
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(((tmp >> 13) & 0x1) == 0x1) &&
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(((tmp >> 3) & 0x1) == 0x0) &&
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(obs_err == 0))
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obs_err == 0)
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break;
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else if ((((tmp >> 3) & 0x1) == 0x1) ||
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(obs_err == 1))
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@ -955,8 +954,10 @@ static void dram_all_config(struct dram_info *dram,
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sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
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sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
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sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
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sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel);
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sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel);
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sys_reg |= (info->cs0_row - 13) <<
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SYS_REG_CS0_ROW_SHIFT(channel);
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sys_reg |= (info->cs1_row - 13) <<
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SYS_REG_CS1_ROW_SHIFT(channel);
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sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
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sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
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@ -991,7 +992,7 @@ static void dram_all_config(struct dram_info *dram,
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}
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static int switch_to_phy_index1(struct dram_info *dram,
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const struct rk3399_sdram_params *sdram_params)
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const struct rk3399_sdram_params *sdram_params)
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{
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u32 channel;
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u32 *denali_phy;
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@ -1026,7 +1027,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
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denali_phy = dram->chan[channel].publ->denali_phy;
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clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
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ret = data_training(&dram->chan[channel], channel,
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sdram_params, PI_FULL_TRAINING);
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sdram_params, PI_FULL_TRAINING);
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if (ret) {
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debug("index1 training failed\n");
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return ret;
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@ -1116,8 +1117,8 @@ static int conv_of_platdata(struct udevice *dev)
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int ret;
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ret = regmap_init_mem_platdata(dev, dtplat->reg,
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ARRAY_SIZE(dtplat->reg) / 2,
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&plat->map);
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ARRAY_SIZE(dtplat->reg) / 2,
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&plat->map);
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if (ret)
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return ret;
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@ -1199,8 +1200,8 @@ static int rk3399_dmc_probe(struct udevice *dev)
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priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
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debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
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priv->info.base = CONFIG_SYS_SDRAM_BASE;
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priv->info.size = rockchip_sdram_size(
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(phys_addr_t)&priv->pmugrf->os_reg2);
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priv->info.size =
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rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
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#endif
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return 0;
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}
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@ -1218,7 +1219,6 @@ static struct ram_ops rk3399_dmc_ops = {
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.get_info = rk3399_dmc_get_info,
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};
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static const struct udevice_id rk3399_dmc_ids[] = {
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{ .compatible = "rockchip,rk3399-dmc" },
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{ }
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