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mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output 

For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.

After commit b5874b552f ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON,
after CMD11, hardware will gate off the card clock automatically, so card do
not detect the clock off/on behavior, so will draw the data0 line low until
next command.

Fixes: b5874b552f ("mmc: fsl_esdhc_imx: add wait_dat0() support")
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
This commit is contained in:
Haibo Chen 2021-03-03 17:05:46 +08:00 committed by Stefano Babic
parent dec7755c44
commit 63756575b4
2 changed files with 23 additions and 8 deletions
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29
drivers/mmc/fsl_esdhc_imx.c
View File

@ -660,7 +660,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4);
#ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
if (ret)
pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
#else
esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
#endif
@ -672,7 +675,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
#ifdef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#else
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
@ -727,8 +730,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 val;
u32 tmp;
int ret;
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
if (ret)
pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
/*
@ -746,6 +755,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
pr_warn("HS400 strobe DLL status REF not lock!\n");
if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
pr_warn("HS400 strobe DLL status SLV not lock!\n");
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
}
}
@ -969,14 +979,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
#ifdef MMC_SUPPORTS_TUNING
if (mmc->clk_disable) {
#ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
u32 tmp;
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
if (ret)
pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
#else
esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
#endif
} else {
#ifdef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
VENDORSPEC_CKEN);
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#else
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
@ -1052,7 +1066,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
#else
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#endif
/* Set the initial clock speed */
@ -1190,8 +1204,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
esdhc_write32(&regs->autoc12err, 0);
esdhc_write32(&regs->clktunectrlstatus, 0);
#else
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#endif
if (priv->vs18_enable)

2
include/fsl_esdhc_imx.h
View File

@ -39,6 +39,7 @@
#define VENDORSPEC_HCKEN 0x00001000
#define VENDORSPEC_IPGEN 0x00000800
#define VENDORSPEC_INIT 0x20007809
#define VENDORSPEC_FRC_SDCLK_ON 0x00000100
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
@ -96,6 +97,7 @@
#define PRSSTAT_CINS (0x00010000)
#define PRSSTAT_BREN (0x00000800)
#define PRSSTAT_BWEN (0x00000400)
#define PRSSTAT_SDOFF (0x00000080)
#define PRSSTAT_SDSTB (0X00000008)
#define PRSSTAT_DLA (0x00000004)
#define PRSSTAT_CICHB (0x00000002)