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https://github.com/brain-hackers/u-boot-brain
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microblaze: start.S: Factor out exception setup code to __setup_exceptions
Currently, the exceptions setup code is duplicated in pre-relocation and post-relocation init. Factor out this code to __setup_exceptions asm routine to get rid of the duplication. __setup_exceptions is called with a relocation offset parameter (r5) which is set to zero for pre-reloc init and gd->reloc_off for post-reloc exception setup. Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ovidiu Panait
Michal Simek
parent
c99e87f828
commit
627085eacf
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@ -13,13 +13,6 @@
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.text
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.global _start
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_start:
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/*
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* reserve registers:
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* r10: Stores little/big endian offset for vectors
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* r2: Stores imm opcode
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* r3: Stores brai opcode
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*/
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mts rmsr, r0 /* disable cache */
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addi r8, r0, __end
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@ -38,102 +31,16 @@ _start:
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mts rshr, r1
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addi r1, r1, -4 /* Decrement SP to top of memory */
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/* Find-out if u-boot is running on BIG/LITTLE endian platform
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* There are some steps which is necessary to keep in mind:
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* 1. Setup offset value to r6
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* 2. Store word offset value to address 0x0
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* 3. Load just byte from address 0x0
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* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
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* value that's why is on address 0x0
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* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
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*/
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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lwi r7, r0, 0x28
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swi r6, r0, 0x28 /* used first unused MB vector */
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lbui r10, r0, 0x28 /* used first unused MB vector */
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swi r7, r0, 0x28
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/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
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addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
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addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
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#ifdef CONFIG_SYS_RESET_ADDRESS
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/* reset address */
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swi r2, r0, 0x0 /* reset address - imm opcode */
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swi r3, r0, 0x4 /* reset address - brai opcode */
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addik r6, r0, CONFIG_SYS_RESET_ADDRESS
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x2
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sh r7, r0, r8
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rsubi r8, r10, 0x6
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sh r6, r0, r8
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#endif
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#ifdef CONFIG_SYS_USR_EXCEP
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/* user_vector_exception */
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swi r2, r0, 0x8 /* user vector exception - imm opcode */
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swi r3, r0, 0xC /* user vector exception - brai opcode */
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addik r6, r0, _exception_handler
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sw r6, r1, r0
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/*
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* BIG ENDIAN memory map for user exception
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* 0x8: 0xB000XXXX
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* 0xC: 0xB808XXXX
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*
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* then it is necessary to count address for storing the most significant
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* 16bits from _exception_handler address and copy it to
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* 0xa address. Big endian use offset in r10=0 that's why is it just
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* 0xa address. The same is done for the least significant 16 bits
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* for 0xe address.
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*
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* LITTLE ENDIAN memory map for user exception
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* 0x8: 0xXXXX00B0
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* 0xC: 0xXXXX08B8
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*
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* Offset is for little endian setup to 0x2. rsubi instruction decrease
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* address value to ensure that points to proper place which is
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* 0x8 for the most significant 16 bits and
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* 0xC for the least significant 16 bits
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*/
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lhu r7, r1, r10
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rsubi r8, r10, 0xa
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sh r7, r0, r8
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rsubi r8, r10, 0xe
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sh r6, r0, r8
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#endif
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/* interrupt_handler */
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swi r2, r0, 0x10 /* interrupt - imm opcode */
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swi r3, r0, 0x14 /* interrupt - brai opcode */
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addik r6, r0, _interrupt_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x12
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sh r7, r0, r8
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rsubi r8, r10, 0x16
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sh r6, r0, r8
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/* hardware exception */
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swi r2, r0, 0x20 /* hardware exception - imm opcode */
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swi r3, r0, 0x24 /* hardware exception - brai opcode */
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addik r6, r0, _hw_exception_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x22
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sh r7, r0, r8
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rsubi r8, r10, 0x26
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sh r6, r0, r8
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/* Setup vectors with pre-relocation symbols */
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or r5, r0, r0
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bralid r15, __setup_exceptions
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nop
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#endif /* CONFIG_SPL_BUILD */
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/* Flush cache before enable cache */
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addik r5, r0, 0
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addik r6, r0, XILINX_DCACHE_BYTE_SIZE
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bralid r15, flush_cache
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bralid r15, flush_cache
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nop
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/* enable instruction and data cache */
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@ -182,6 +89,137 @@ _gd:
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.space GENERATED_GBL_DATA_SIZE
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#ifndef CONFIG_SPL_BUILD
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.text
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.ent __setup_exceptions
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.align 2
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/*
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* Set up reset, interrupt, user exception and hardware exception vectors.
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*
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* Parameters:
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* r5 - relocation offset (zero when setting up vectors before
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* relocation, and gd->reloc_off when setting up vectors after
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* relocation)
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* - the relocation offset is added to the _exception_handler,
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* _interrupt_handler and _hw_exception_handler symbols to reflect the
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* post-relocation memory addresses
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*
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* Reserve registers:
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* r10: Stores little/big endian offset for vectors
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* r2: Stores imm opcode
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* r3: Stores brai opcode
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*/
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__setup_exceptions:
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addik r1, r1, -28
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swi r2, r1, 4
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swi r3, r1, 8
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swi r6, r1, 12
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swi r7, r1, 16
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swi r8, r1, 20
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swi r10, r1, 24
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/* Find-out if u-boot is running on BIG/LITTLE endian platform
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* There are some steps which is necessary to keep in mind:
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* 1. Setup offset value to r6
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* 2. Store word offset value to address 0x0
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* 3. Load just byte from address 0x0
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* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
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* value that's why is on address 0x0
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* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
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*/
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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lwi r7, r0, 0x28
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swi r6, r0, 0x28 /* used first unused MB vector */
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lbui r10, r0, 0x28 /* used first unused MB vector */
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swi r7, r0, 0x28
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/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
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addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
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addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
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#ifdef CONFIG_SYS_RESET_ADDRESS
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/* reset address */
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swi r2, r0, 0x0 /* reset address - imm opcode */
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swi r3, r0, 0x4 /* reset address - brai opcode */
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addik r6, r0, CONFIG_SYS_RESET_ADDRESS
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x2
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sh r7, r0, r8
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rsubi r8, r10, 0x6
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sh r6, r0, r8
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#endif
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#ifdef CONFIG_SYS_USR_EXCEP
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/* user_vector_exception */
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swi r2, r0, 0x8 /* user vector exception - imm opcode */
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swi r3, r0, 0xC /* user vector exception - brai opcode */
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addik r6, r5, _exception_handler
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sw r6, r1, r0
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/*
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* BIG ENDIAN memory map for user exception
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* 0x8: 0xB000XXXX
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* 0xC: 0xB808XXXX
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*
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* then it is necessary to count address for storing the most significant
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* 16bits from _exception_handler address and copy it to
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* 0xa address. Big endian use offset in r10=0 that's why is it just
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* 0xa address. The same is done for the least significant 16 bits
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* for 0xe address.
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*
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* LITTLE ENDIAN memory map for user exception
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* 0x8: 0xXXXX00B0
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* 0xC: 0xXXXX08B8
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*
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* Offset is for little endian setup to 0x2. rsubi instruction decrease
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* address value to ensure that points to proper place which is
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* 0x8 for the most significant 16 bits and
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* 0xC for the least significant 16 bits
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*/
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lhu r7, r1, r10
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rsubi r8, r10, 0xa
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sh r7, r0, r8
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rsubi r8, r10, 0xe
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sh r6, r0, r8
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#endif
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/* interrupt_handler */
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swi r2, r0, 0x10 /* interrupt - imm opcode */
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swi r3, r0, 0x14 /* interrupt - brai opcode */
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addik r6, r5, _interrupt_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x12
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sh r7, r0, r8
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rsubi r8, r10, 0x16
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sh r6, r0, r8
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/* hardware exception */
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swi r2, r0, 0x20 /* hardware exception - imm opcode */
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swi r3, r0, 0x24 /* hardware exception - brai opcode */
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addik r6, r5, _hw_exception_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x22
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sh r7, r0, r8
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rsubi r8, r10, 0x26
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sh r6, r0, r8
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lwi r10, r1, 24
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lwi r8, r1, 20
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lwi r7, r1, 16
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lwi r6, r1, 12
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lwi r3, r1, 8
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lwi r2, r1, 4
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addik r1, r1, 28
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rtsd r15, 8
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or r0, r0, r0
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.end __setup_exceptions
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/*
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* Read 16bit little endian
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*/
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@ -249,39 +287,10 @@ relocate_code:
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addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
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rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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lwi r7, r0, 0x28
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swi r6, r0, 0x28 /* used first unused MB vector */
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lbui r10, r0, 0x28 /* used first unused MB vector */
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swi r7, r0, 0x28
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#ifdef CONFIG_SYS_USR_EXCEP
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addik r6, r0, _exception_handler
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addk r6, r6, r23 /* add offset */
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0xa
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sh r7, r0, r8
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rsubi r8, r10, 0xe
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sh r6, r0, r8
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#endif
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addik r6, r0, _hw_exception_handler
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addk r6, r6, r23 /* add offset */
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x22
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sh r7, r0, r8
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rsubi r8, r10, 0x26
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sh r6, r0, r8
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addik r6, r0, _interrupt_handler
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addk r6, r6, r23 /* add offset */
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x12
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sh r7, r0, r8
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rsubi r8, r10, 0x16
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sh r6, r0, r8
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/* Setup vectors with post-relocation symbols */
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add r5, r0, r23 /* load gd->reloc_off to r5 */
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bralid r15, __setup_exceptions
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nop
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/* Check if GOT exist */
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addik r21, r23, _got_start
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