From 9df4757718812b86f6ccb5d8331a08cdfd1527c4 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Thu, 23 Oct 2014 23:02:01 +0200 Subject: [PATCH 01/26] board: wandboard: add usb storage Cc: Fabio Estevam Signed-off-by: Jeroen Hofstee Acked-by: Fabio Estevam --- include/configs/wandboard.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 9fb501a341..809017c5fe 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -78,6 +78,15 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + /* Ethernet Configuration */ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP From f91c09acf5c58cde552e4036fe48b8e47e92d69c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 24 Oct 2014 23:39:07 +0200 Subject: [PATCH 02/26] ARM: mx6: Add support for Kosagi Novena Add support for the Kosagi Novena board. Currently supported are: - I2C busses - FEC Ethernet - MMC0, MMC1, Booting from MMC - SATA - USB ports - USB Ethernet Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Sean Cross Cc: Nikolay Dimitrov Reviewed-by: Nikolay Dimitrov --- arch/arm/Kconfig | 4 + board/kosagi/novena/Kconfig | 18 + board/kosagi/novena/Makefile | 11 + board/kosagi/novena/novena.c | 343 +++++++++++++++++++ board/kosagi/novena/novena_spl.c | 556 +++++++++++++++++++++++++++++++ board/kosagi/novena/setup.cfg | 47 +++ configs/novena_defconfig | 4 + include/configs/imx6_spl.h | 2 +- include/configs/novena.h | 298 +++++++++++++++++ 9 files changed, 1282 insertions(+), 1 deletion(-) create mode 100644 board/kosagi/novena/Kconfig create mode 100644 board/kosagi/novena/Makefile create mode 100644 board/kosagi/novena/novena.c create mode 100644 board/kosagi/novena/novena_spl.c create mode 100644 board/kosagi/novena/setup.cfg create mode 100644 configs/novena_defconfig create mode 100644 include/configs/novena.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 72558b8562..bef298f1bc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -414,6 +414,9 @@ config TARGET_GW_VENTANA config TARGET_HUMMINGBOARD bool "Support hummingboard" +config TARGET_KOSAGI_NOVENA + bool "Support Kosagi Novena" + config TARGET_TQMA6 bool "TQ Systems TQMa6 board" @@ -646,6 +649,7 @@ source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/jornada/Kconfig" source "board/karo/tx25/Kconfig" +source "board/kosagi/novena/Kconfig" source "board/logicpd/imx27lite/Kconfig" source "board/logicpd/imx31_litekit/Kconfig" source "board/mpl/vcma9/Kconfig" diff --git a/board/kosagi/novena/Kconfig b/board/kosagi/novena/Kconfig new file mode 100644 index 0000000000..4ba63999ae --- /dev/null +++ b/board/kosagi/novena/Kconfig @@ -0,0 +1,18 @@ +if TARGET_KOSAGI_NOVENA + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "novena" + +config SYS_VENDOR + default "kosagi" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "novena" + +endif diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile new file mode 100644 index 0000000000..6fba17718b --- /dev/null +++ b/board/kosagi/novena/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2014 Marek Vasut +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := novena_spl.o +else +obj-y := novena.o +endif diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c new file mode 100644 index 0000000000..2361a3c550 --- /dev/null +++ b/board/kosagi/novena/novena.c @@ -0,0 +1,343 @@ +/* + * Novena board support + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14) +#define NOVENA_SD_WP IMX_GPIO_NR(1, 2) +#define NOVENA_SD_CD IMX_GPIO_NR(1, 4) + +/* + * GPIO button + */ +#ifdef CONFIG_KEYBOARD +static struct input_config button_input; + +static int novena_gpio_button_read_keys(struct input_config *input) +{ + int key = KEY_ENTER; + if (gpio_get_value(NOVENA_BUTTON_GPIO)) + return 0; + input_send_keycodes(&button_input, &key, 1); + return 1; +} + +static int novena_gpio_button_getc(struct stdio_dev *dev) +{ + return input_getc(&button_input); +} + +static int novena_gpio_button_tstc(struct stdio_dev *dev) +{ + return input_tstc(&button_input); +} + +static int novena_gpio_button_init(struct stdio_dev *dev) +{ + gpio_direction_input(NOVENA_BUTTON_GPIO); + input_set_delays(&button_input, 250, 250); + return 0; +} + +int drv_keyboard_init(void) +{ + int error; + struct stdio_dev dev = { + .name = "button", + .flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM, + .start = novena_gpio_button_init, + .getc = novena_gpio_button_getc, + .tstc = novena_gpio_button_tstc, + }; + + error = input_init(&button_input, 0); + if (error) { + debug("%s: Cannot set up input\n", __func__); + return -1; + } + button_input.read_keys = novena_gpio_button_read_keys; + + error = input_stdio_register(&dev); + if (error) + return error; + + return 0; +} +#endif + +/* + * SDHC + */ +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC3_BASE_ADDR, 0, 4 }, /* Micro SD */ + { USDHC2_BASE_ADDR, 0, 4 }, /* Big SD */ +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + /* There is no CD for a microSD card, assume always present. */ + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + return 1; + else + return !gpio_get_value(NOVENA_SD_CD); +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + /* There is no WP for a microSD card, assume always read-write. */ + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + return 0; + else + return gpio_get_value(NOVENA_SD_WP); +} + + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + int index; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + /* Big SD write-protect and card-detect */ + gpio_direction_input(NOVENA_SD_WP); + gpio_direction_input(NOVENA_SD_CD); + + for (index = 0; index < ARRAY_SIZE(usdhc_cfg); index++) { + status = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (status) + return status; + } + + return status; +} +#endif + +/* + * Video over HDMI + */ +#if defined(CONFIG_VIDEO_IPUV3) +static void enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = { + { + /* HDMI Output */ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + } +}; + +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + /* set LDB0, LDB1 clk select to 011/011 */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK, + (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); + + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, + IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); +} +#endif + +int board_early_init_f(void) +{ +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + + /* Bring Ethernet PHY out of reset. */ + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: Novena 4x\n"); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + u32 reg; + int ret; + + power_pfuze100_init(1); + p = pmic_get("PFUZE100"); + if (!p) + return -EINVAL; + + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set SWBST to 5.0V and enable (for USB) */ + pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); + reg |= (SWBST_5_00V | SWBST_MODE_AUTO); + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); + + return 0; +} + +/* EEPROM configuration data */ +struct novena_eeprom_data { + uint8_t signature[6]; + uint8_t version; + uint8_t reserved; + uint32_t serial; + uint8_t mac[6]; + uint16_t features; +}; + +int misc_init_r(void) +{ + struct novena_eeprom_data data; + uchar *datap = (uchar *)&data; + const char *signature = "Novena"; + int ret; + + /* If 'ethaddr' is already set, do nothing. */ + if (getenv("ethaddr")) + return 0; + + /* EEPROM is at bus 2. */ + ret = i2c_set_bus_num(2); + if (ret) { + puts("Cannot select EEPROM I2C bus.\n"); + return 0; + } + + /* EEPROM is at address 0x56. */ + ret = eeprom_read(0x56, 0, datap, sizeof(data)); + if (ret) { + puts("Cannot read I2C EEPROM.\n"); + return 0; + } + + /* Check EEPROM signature. */ + if (memcmp(data.signature, signature, 6)) { + puts("Invalid I2C EEPROM signature.\n"); + return 0; + } + + /* Set ethernet address from EEPROM. */ + eth_setenv_enetaddr("ethaddr", data.mac); + + return ret; +} diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c new file mode 100644 index 0000000000..a8389d9c6b --- /dev/null +++ b/board/kosagi/novena/novena_spl.c @@ -0,0 +1,556 @@ +/* + * Novena SPL + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define RGMII_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL \ + (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define BUTTON_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) +#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) +#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) +#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) +#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) +#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22) +#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) + +/* + * Audio + */ +static iomux_v3_cfg_t audio_pads[] = { + /* AUD_PWRON */ + MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_audio(void) +{ + imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads)); + gpio_direction_output(NOVENA_AUDIO_PWRON, 1); +} + +/* + * ENET + */ +static iomux_v3_cfg_t enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t enet_pads2[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +/* + * FPGA + */ +static iomux_v3_cfg_t fpga_pads[] = { + /* FPGA_RESET_N */ + MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_fpga(void) +{ + imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads)); + gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0); +} + +/* + * GPIO Button + */ +static iomux_v3_cfg_t button_pads[] = { + /* Debug */ + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads)); +} + +/* + * I2C + */ +/* + * I2C1: + * 0x1d ... MMA7455L + * 0x30 ... SO-DIMM temp sensor + * 0x44 ... STMPE610 + * 0x50 ... SO-DIMM ID + */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* + * I2C2: + * 0x08 ... PMIC + * 0x3a ... HDMI DCC + * 0x50 ... HDMI DCC + */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + +/* + * I2C3: + * 0x11 ... ES8283 + * 0x50 ... LCD EDID + * 0x56 ... EEPROM + */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +static void novena_spl_setup_iomux_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +} + +/* + * PCI express + */ +#ifdef CONFIG_CMD_PCI +static iomux_v3_cfg_t pcie_pads[] = { + /* "Reset" pin */ + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* "Power on" pin */ + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* "Wake up" pin (input) */ + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* "Disable endpoint" (rfkill) pin */ + MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); + + /* Ensure PCIe is powered down */ + gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0); + + /* Put the card into reset */ + gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0); + + /* Input signal to wake system from mPCIe card */ + gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO); + + /* Drive RFKILL high, to ensure the radio is turned on */ + gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1); +} +#else +static inline void novena_spl_setup_iomux_pcie(void) {} +#endif + +/* + * SDHC + */ +static iomux_v3_cfg_t usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static iomux_v3_cfg_t usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_sdhc(void) +{ + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + + /* Big SD write-protect and card-detect */ + gpio_direction_input(IMX_GPIO_NR(1, 2)); + gpio_direction_input(IMX_GPIO_NR(1, 4)); +} + +/* + * SPI + */ +#ifdef CONFIG_MXC_SPI +static iomux_v3_cfg_t ecspi3_pads[] = { + /* SS1 */ + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); + /* De-assert the nCS */ + gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1); + gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1); + gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1); +} +#else +static void novena_spl_setup_iomux_spi(void) {} +#endif + +/* + * UART + */ +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + +}; + +static void novena_spl_setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +/* + * Video + */ +#ifdef CONFIG_VIDEO +static iomux_v3_cfg_t hdmi_pads[] = { + /* "Ghost HPD" pin */ + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_video(void) +{ + imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads)); + gpio_direction_input(NOVENA_HDMI_GHOST_HPD); +} +#else +static inline void novena_spl_setup_iomux_video(void) {} +#endif + +/* + * SPL boots from uSDHC card + */ +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg = { + USDHC3_BASE_ADDR, 0, 4 +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* There is no CD for a microSD card, assume always present. */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} +#endif + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020038, + .dram_sdclk_1 = 0x00020038, + .dram_cas = 0x00000038, + .dram_ras = 0x00000038, + .dram_reset = 0x00000038, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00000038, + .dram_sdodt1 = 0x00000038, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000038, + .dram_sdqs2 = 0x00000038, + .dram_sdqs3 = 0x00000038, + .dram_sdqs4 = 0x00000038, + .dram_sdqs5 = 0x00000038, + .dram_sdqs6 = 0x00000038, + .dram_sdqs7 = 0x00000038, + + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00000038, + .dram_dqm1 = 0x00000038, + .dram_dqm2 = 0x00000038, + .dram_dqm3 = 0x00000038, + .dram_dqm4 = 0x00000038, + .dram_dqm5 = 0x00000038, + .dram_dqm6 = 0x00000038, + .dram_dqm7 = 0x00000038, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs novena_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* Disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000038, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000038, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000038, + .grp_b1ds = 0x00000038, + .grp_b2ds = 0x00000038, + .grp_b3ds = 0x00000038, + .grp_b4ds = 0x00000038, + .grp_b5ds = 0x00000038, + .grp_b6ds = 0x00000038, + .grp_b7ds = 0x00000038, +}; + +static struct mx6_mmdc_calibration novena_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00420048, + .p0_mpwldectrl1 = 0x006f0059, + .p1_mpwldectrl0 = 0x005a0104, + .p1_mpwldectrl1 = 0x01070113, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x437c040b, + .p0_mpdgctrl1 = 0x0413040e, + .p1_mpdgctrl0 = 0x444f0446, + .p1_mpdgctrl1 = 0x044d0422, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4c424249, + .p1_mprddlctl = 0x4e48414f, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x42414641, + .p1_mpwrdlctl = 0x46374b43, +}; + +static struct mx6_ddr_sysinfo novena_ddr_info = { + /* Width of data bus: 0=16, 1=32, 2=64 */ + .dsize = 2, + /* Config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* Single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 3, /* Write additional latency */ + .ralat = 7, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +static struct mx6_ddr3_cfg elpida_4gib_1600 = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 16, + .coladdr = 10, + .pagesz = 2, + .trcd = 1300, + .trcmin = 4900, + .trasmin = 3590, +}; + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup GP timer */ + timer_init(); + +#ifdef CONFIG_BOARD_POSTCLK_INIT + board_postclk_init(); +#endif +#ifdef CONFIG_FSL_ESDHC + get_clocks(); +#endif + + /* Setup IOMUX and configure basics. */ + novena_spl_setup_iomux_audio(); + novena_spl_setup_iomux_buttons(); + novena_spl_setup_iomux_enet(); + novena_spl_setup_iomux_fpga(); + novena_spl_setup_iomux_i2c(); + novena_spl_setup_iomux_pcie(); + novena_spl_setup_iomux_sdhc(); + novena_spl_setup_iomux_spi(); + novena_spl_setup_iomux_uart(); + novena_spl_setup_iomux_video(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Start the DDR DRAM */ + mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs); + mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/kosagi/novena/setup.cfg b/board/kosagi/novena/setup.cfg new file mode 100644 index 0000000000..18d139c342 --- /dev/null +++ b/board/kosagi/novena/setup.cfg @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* Boot Device : sd */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/configs/novena_defconfig b/configs/novena_defconfig new file mode 100644 index 0000000000..a560afb730 --- /dev/null +++ b/configs/novena_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q,SPL" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_KOSAGI_NOVENA=y diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 970460d5f2..52fe9cf437 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -27,7 +27,7 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x00908000 -#define CONFIG_SPL_MAX_SIZE (64 * 1024) +#define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" #define CONFIG_SPL_STACK 0x0091FFB8 #define CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/include/configs/novena.h b/include/configs/novena.h new file mode 100644 index 0000000000..879141a7ca --- /dev/null +++ b/include/configs/novena.h @@ -0,0 +1,298 @@ +/* + * Configuration settings for the Novena U-boot. + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* System configurations */ +#define CONFIG_MX6 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_FIT +#define CONFIG_KEYBOARD +#define CONFIG_MXC_GPIO +#define CONFIG_OF_LIBFDT +#define CONFIG_REGEX +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_NO_FLASH + +#include "configs/mx6_common.h" +#include +#include +#include + +/* U-Boot Commands */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_I2C +#define CONFIG_CMD_FUSE +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SATA +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_TIME +#define CONFIG_CMD_USB +#define CONFIG_VIDEO + +/* U-Boot general configurations */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER + +/* U-Boot environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SIZE (16 * 1024) +/* + * Environment is on MMC, starting at offset 512KiB from start of the card. + * Please place first partition at offset 1MiB from the start of the card + * as recommended by GNU/fdisk. See below for details: + * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET (512 * 1024) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTARGS "console=ttymxc1,115200 " +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_LOADADDR 0x18000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_HOSTNAME novena + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE 0xF0000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) + +/* SPL */ +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" /* common IMX6 SPL configuration */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Ethernet Configuration */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0x7 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_ARP_TIMEOUT 200UL +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C EEPROM */ +#ifdef CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_SPD_BUS_NUM 2 +#endif + +/* MMC Configs */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* OCOTP Configs */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* PCI express */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) +#endif + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* SATA Configs */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_INDEX 1 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +/* Gadget part */ +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#endif + +/* Video output */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* Extra U-Boot environment. */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "consdev=ttymxc1\0" \ + "baudrate=115200\0" \ + "bootdev=/dev/mmcblk0p1\0" \ + "rootdev=/dev/mmcblk0p2\0" \ + "netdev=eth0\0" \ + "kernel_addr_r=0x18000000\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "update_sd_spl_filename=SPL\0" \ + "update_sd_uboot_filename=u-boot.img\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if dhcp ${update_sd_spl_filename} ; then " \ + "mmc write ${loadaddr} 2 0x200 ; " \ + "fi ; " \ + "if dhcp ${update_sd_uboot_filename} ; then " \ + "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\ + "fi ; " \ + "fi\0" \ + +#endif /* __CONFIG_H */ From ca9d817ab54077d5b8a814a7af9c8342a0641051 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 21 Oct 2014 21:14:53 -0200 Subject: [PATCH 03/26] mx6sabresd: Add Seiko WVGA panel support Add support for the 4.3'' Seiko WVGA parallel display. In order to direct the splash screen to the Seiko display: => setenv panel SEIKO-WVGA => save => reset Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- board/freescale/mx6sabresd/mx6sabresd.c | 61 +++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 81dcd6e5dd..3d81fffea5 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -51,6 +51,8 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) +#define DISP0_PWR_EN IMX_GPIO_NR(1, 21) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -141,6 +143,45 @@ iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t const rgb_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); + gpio_direction_output(DISP0_PWR_EN, 1); +} + static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, @@ -357,6 +398,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "SEIKO-WVGA", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED } } }; size_t display_count = ARRAY_SIZE(displays); From 1719d49c347f2faee387aacbf643d171461820a9 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Thu, 23 Oct 2014 15:47:05 +0200 Subject: [PATCH 04/26] tqma6: fix sf detection Commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 changed the way to define a GPIO line, which can be used to force CS high across multiple transactions. In order to fix sf detection change board code to make use of board_spi_cs_gpio(..). Signed-off-by: Markus Niebel --- board/tqc/tqma6/tqma6.c | 10 +++++++++- include/configs/tqma6.h | 19 ++++++++++++++++--- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index b552bb8d7e..fd1bd59c6c 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -138,8 +138,10 @@ static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = { NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), }; +#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19) + static unsigned const tqma6_ecspi1_cs[] = { - IMX_GPIO_NR(3, 19), + TQMA6_SF_CS_GPIO, }; static void tqma6_iomuxc_spi(void) @@ -152,6 +154,12 @@ static void tqma6_iomuxc_spi(void) ARRAY_SIZE(tqma6_ecspi1_pads)); } +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return ((bus == CONFIG_SF_DEFAULT_BUS) && + (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1; +} + static struct i2c_pads_info tqma6_i2c3_pads = { /* I2C3: on board LM75, M24C64, */ .scl = { diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2705d2c55f..9ba015560b 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -9,13 +9,26 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_MX6 + +/* SPL */ +/* #if defined(CONFIG_SPL_BUILD) */ + +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_EXT_SUPPORT + +/* common IMX6 SPL configuration */ +#include "imx6_spl.h" + +/* #endif */ + #include "mx6_common.h" #include #include #include -#define CONFIG_MX6 - #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #define PHYS_SDRAM_SIZE (512u * SZ_1M) #elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) @@ -57,7 +70,7 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(3, 19) << 8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 50000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) From 29fd5c289c6a95a37c26486ad1c02de9a8ec28da Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Thu, 23 Oct 2014 15:47:06 +0200 Subject: [PATCH 05/26] tqma6: fix typo in header guard define Signed-off-by: Markus Niebel --- board/tqc/tqma6/tqma6_bb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/tqc/tqma6/tqma6_bb.h b/board/tqc/tqma6/tqma6_bb.h index 9d072d28ad..fb7b4626a1 100644 --- a/board/tqc/tqma6/tqma6_bb.h +++ b/board/tqc/tqma6/tqma6_bb.h @@ -6,7 +6,7 @@ */ #ifndef __TQMA6_BB__ -#define __TQMA6_BB +#define __TQMA6_BB__ #include From 1199ddce9c3e5dd25acffe7d7e7999ff779ac832 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 23 Oct 2014 13:46:41 +0200 Subject: [PATCH 06/26] ot1200: add feature pads The older 'mr' variant and the generic variant of the OT1200 differ in some places. As the name suggests the generic variant supports more boot devices. In order to be compatible with the 'mr' variant we define some 'feature' GPIOs. On the 'mr' variant this pads are not connected so we define their state with the help of the internal pullups. On the generic variant this GPIOs are connected and represent the state of the hardware. Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/ot1200.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index acf95cb372..a2fb3cf63c 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -104,10 +104,25 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1; } +static iomux_v3_cfg_t const feature_pads[] = { + /* SD card detect */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN), + + /* eMMC soldered? */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP), +}; + +static void setup_iomux_features(void) +{ + imx_iomux_v3_setup_multiple_pads(feature_pads, + ARRAY_SIZE(feature_pads)); +} + int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_spi(); + setup_iomux_features(); return 0; } From 5a9ca420ce8d90e668c5e0660881f16328984fb0 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 23 Oct 2014 13:46:42 +0200 Subject: [PATCH 07/26] ot1200: add support for usdhc4 On the 'mr' variant switching to 'mmc dev 1' will result in "MMC: no card present". Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/ot1200.c | 52 +++++++++++++++++++++++++++++++--- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index a2fb3cf63c..45d761ff39 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -141,23 +141,67 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + int board_mmc_getcd(struct mmc *mmc) { - return 1; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + ret = 1; + else { + gpio_direction_input(IMX_GPIO_NR(1, 4)); + ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); + } + + return ret; } -struct fsl_esdhc_cfg usdhc_cfg[] = { +struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, }; int board_mmc_init(bd_t *bis) { + s32 status = 0; + u32 index = 0; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].max_bus_width = 4; - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; } #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) From 56740fa96f338025bf1c75e84a77120423f16680 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 23 Oct 2014 13:46:43 +0200 Subject: [PATCH 08/26] ot1200: rework card detect for eMMC Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/ot1200.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 45d761ff39..2ed8cf75d6 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -155,9 +155,10 @@ int board_mmc_getcd(struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret; - if (cfg->esdhc_base == USDHC3_BASE_ADDR) - ret = 1; - else { + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(4, 5)); + ret = gpio_get_value(IMX_GPIO_NR(4, 5)); + } else { gpio_direction_input(IMX_GPIO_NR(1, 4)); ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); } From b99ed2766ae7bfc28077b8e2ce90ce2402483195 Mon Sep 17 00:00:00 2001 From: Nikolay Dimitrov Date: Sun, 12 Oct 2014 13:47:51 +0300 Subject: [PATCH 09/26] novena: Fix ethernet PHY reset sequence This patch fixes conflict between PHY pins becoming outputs after reset and imx6 still driving the pins. It also fixes the reset timing as recommended by the PHY datasheet. Signed-off-by: Nikolay Dimitrov Cc: Stefano Babic Cc: Sean Cross Cc: Marek Vasut Reviewed-by: Fabio Estevam --- board/kosagi/novena/novena.c | 3 -- board/kosagi/novena/novena_spl.c | 64 +++++++++++++++++++++++--------- 2 files changed, 46 insertions(+), 21 deletions(-) diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index 2361a3c550..6add9e5265 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -237,9 +237,6 @@ int board_early_init_f(void) setup_display(); #endif - /* Bring Ethernet PHY out of reset. */ - gpio_set_value(IMX_GPIO_NR(3, 23), 1); - return 0; } diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index a8389d9c6b..c4155ddee2 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -41,6 +41,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PHY_CFG_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_HYS) + #define RGMII_PAD_CTRL \ (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -98,18 +102,20 @@ static iomux_v3_cfg_t enet_pads1[] = { MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* pin 35, PHY_AD2 */ + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 32, MODE0 */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 31, MODE1 */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 28, MODE2 */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 27, MODE3 */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 33, CLK125_EN */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 42 PHY nRST */ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -127,15 +133,37 @@ static void novena_spl_setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + /* Assert Ethernet PHY nRST */ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); - gpio_direction_output(IMX_GPIO_NR(6, 30), 1); - gpio_direction_output(IMX_GPIO_NR(6, 25), 1); - gpio_direction_output(IMX_GPIO_NR(6, 27), 1); - gpio_direction_output(IMX_GPIO_NR(6, 28), 1); - gpio_direction_output(IMX_GPIO_NR(6, 29), 1); - gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + /* + * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset + * de-assertion. The intention is to use weak signal drivers (pull-ups) + * to prevent the conflict between PHY pins becoming outputs after + * reset and imx6 still driving the pins. The issue is described in PHY + * datasheet, p.14 + */ + gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */ + + /* Following reset timing (p.53, fig.8 from the PHY datasheet) */ + mdelay(10); + + /* De-assert Ethernet PHY nRST */ + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + + /* PHY is now configured, connect FEC to the pads */ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + + /* + * PHY datasheet recommends on p.53 to wait at least 100us after reset + * before using MII, so we enforce the delay here + */ + udelay(100); } /* From 9c56936eb5fc8191df2e7f6016d579741d5f01e0 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 16 Oct 2014 20:37:25 +0200 Subject: [PATCH 10/26] arm: imx6: fix typos in CCM_ANALOG_PLL_VIDEO_DENOM register name Fix name for Video PLL denominator register. Signed-off-by: Anatolij Gustschin --- arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index e67b5b9e7d..85e301c6ea 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -89,7 +89,7 @@ struct mxc_ccm_reg { u32 analog_pll_video_tog; u32 analog_pll_video_num; /* 0x40b0 */ u32 analog_reserved6[3]; - u32 analog_pll_vedio_denon; /* 0x40c0 */ + u32 analog_pll_video_denom; /* 0x40c0 */ u32 analog_reserved7[7]; u32 analog_pll_enet; /* 0x40e0 */ u32 analog_pll_enet_set; From f9cfe17b3d145edd2a308a934594d659ffc69439 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 25 Sep 2014 21:13:36 +0200 Subject: [PATCH 11/26] mtd: nand: mxs: Add ECC geometry for 2048b/112b NAND Add ECC geometry for NAND which has 2048b pagesize and 112b OOB size. This is for example Macronix MX30LF2G28AB chip. Signed-off-by: Marek Vasut --- drivers/mtd/nand/mxs_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 036c113ad3..7a064ab1bf 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -146,8 +146,13 @@ static uint32_t mxs_nand_aux_status_offset(void) static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, uint32_t page_oob_size) { - if (page_data_size == 2048) - return 8; + if (page_data_size == 2048) { + if (page_oob_size == 64) + return 8; + + if (page_oob_size == 112) + return 14; + } if (page_data_size == 4096) { if (page_oob_size == 128) From 4bfa2db8e19d5e500d75ac71f3faacb7614df24b Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Fri, 24 Oct 2014 16:33:28 +0200 Subject: [PATCH 12/26] arm: arch-mx6: typo fixes in crm_regs.h fix typos in video pll related register names and bit defines Signed-off-by: Soeren Moch --- arch/arm/include/asm/arch-mx6/crm_regs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 85e301c6ea..92f9b21dd8 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -931,10 +931,10 @@ struct mxc_ccm_reg { #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ - (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) +#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 +#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 +#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ + (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 From d12159b63b0e0fe4842afedf84b4a497f2323b8b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Oct 2014 00:00:50 +0200 Subject: [PATCH 13/26] arm: mxs: Define bootscript env variable on m28evk The patch below failed to define the variable, so define it to make it consistent with M53EVK. commit a428ac914b2b6db851c1feac98622f2d9844db45 Author: Lothar Rubusch Date: Thu Jun 26 11:01:29 2014 +0200 ARM: m28evk: Update default environment Signed-off-by: Marek Vasut Cc: Tom Rini Cc: Wolfgang Denk Cc: Stefano Babic --- include/configs/m28evk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index efe770b81b..5c209913e5 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -171,6 +171,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "consdev=ttyAMA0\0" \ "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ "bootdev=/dev/mmcblk0p2\0" \ "rootdev=/dev/mmcblk0p3\0" \ "netdev=eth0\0" \ From de97980478db4378719a529deb8e203e33bf6f66 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 17:54:08 +0800 Subject: [PATCH 14/26] imximage: Fix the bootdata.size calculation In system boot chapter of i.MX6 reference manual, the "Image Vector Table" figure shows the bootdata.start points to the beginning of the destination memory. It means the bootdata.size should contain the IVT offset part, but the calculation in imximage tool does not have. We found this issue when booting from QuadSPI NOR on i.MX6SX. The u-boot runs into abnormal (crash or stop) after booting. After checked the destination memory where the image is loaded to, there are hundreds of bytes at the image end are not loaded into memory. Since there is a 4096 bytes round in the calculation, for the booting devices using smaller IVT offset, such as SD and SPI booting, they are not easy to reproduce. Signed-off-by: Ye.Li --- tools/imximage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imximage.c b/tools/imximage.c index faba23860f..526b7d490d 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -587,7 +587,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, * * The remaining fraction of a block bytes would not be loaded! */ - *header_size_ptr = ROUND(sbuf->st_size, 4096); + *header_size_ptr = ROUND((sbuf->st_size + imximage_ivt_offset), 4096); if (csf_ptr && imximage_csf_size) { *csf_ptr = params->ep - imximage_init_loadsize + From 1a1f7950781541f707a84111731634ee8b20ed61 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 18:20:55 +0800 Subject: [PATCH 15/26] imx: gpt: Add High frequency clock source support for GPT Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set, the GPT will select a high frequency clock as clock source. Otherwise, the GPT will stay to use 32Khz OSC as clock source. In the implementation, since only the GPT on i.MX6 series provide the clock source option for 24Mhz OSC. For others (only i.MX5 and i.MX6 compile the driver), if the configuration is set, the perclk will be selected as clock source. MX6Q/D Rev 1.0 and MX6SL are special in the implementation, because they don't have the 24Mhz OSC clock source option, so also select the perclk for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so eventually the clock comes from OSC 24Mhz. Signed-off-by: Ye.Li --- arch/arm/imx-common/timer.c | 75 ++++++++++++++++++++++++++++++++----- 1 file changed, 66 insertions(+), 9 deletions(-) diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index c63f78f682..65ef60bf2e 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -12,6 +12,7 @@ #include #include #include +#include /* General purpose timers registers */ struct mxc_gpt { @@ -26,23 +27,59 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; /* General purpose timers bitfields */ #define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */ #define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */ +#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */ +#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */ +#define GPTCR_CLKSOURCE_MASK (0x7 << 6) #define GPTCR_TEN 1 /* Timer enable */ +#define GPTPR_PRESCALER24M_SHIFT 12 +#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT) + DECLARE_GLOBAL_DATA_PTR; +static inline int gpt_has_clk_source_osc(void) +{ +#if defined(CONFIG_MX6) + if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && + (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) + return 1; + + return 0; +#else + return 0; +#endif +} + +static inline ulong gpt_get_clk(void) +{ +#ifdef CONFIG_MXC_GPT_HCLK + if (gpt_has_clk_source_osc()) + return MXC_HCLK >> 3; + else + return mxc_get_clock(MXC_IPG_PERCLK); +#else + return MXC_CLK32; +#endif +} static inline unsigned long long tick_to_time(unsigned long long tick) { + ulong gpt_clk = gpt_get_clk(); + tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); + do_div(tick, gpt_clk); return tick; } static inline unsigned long long us_to_tick(unsigned long long usec) { - usec = usec * MXC_CLK32 + 999999; + ulong gpt_clk = gpt_get_clk(); + + usec = usec * gpt_clk + 999999; do_div(usec, 1000000); return usec; @@ -59,11 +96,31 @@ int timer_init(void) for (i = 0; i < 100; i++) __raw_writel(0, &cur_gpt->control); - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ - - /* Freerun Mode, PERCLK1 input */ i = __raw_readl(&cur_gpt->control); - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); + i &= ~GPTCR_CLKSOURCE_MASK; + +#ifdef CONFIG_MXC_GPT_HCLK + if (gpt_has_clk_source_osc()) { + i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; + + /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */ + if (is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO) || + is_cpu_type(MXC_CPU_MX6SX)) { + i |= GPTCR_24MEN; + + /* Produce 3Mhz clock */ + __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT), + &cur_gpt->prescaler); + } + } else { + i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN; + } +#else + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ + i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; +#endif + __raw_writel(i, &cur_gpt->control); gd->arch.tbl = __raw_readl(&cur_gpt->counter); gd->arch.tbu = 0; @@ -86,7 +143,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -117,5 +174,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return MXC_CLK32; + return gpt_get_clk(); } From 0561b8edf0098e938f8e9fb55be41ddb455b52b2 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 18:20:56 +0800 Subject: [PATCH 16/26] imx: mx6sl: Add perclk_clk_sel bit define in CCM The MX6SL has the perclk_clk_sel to select the perclk source. Add its define in CCM Signed-off-by: Ye.Li --- arch/arm/include/asm/arch-mx6/crm_regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 92f9b21dd8..39f3c0707b 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -228,6 +228,8 @@ struct mxc_ccm_reg { #ifdef CONFIG_MX6SX #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 +#endif +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 #endif From e68661a32eb1304413ce45900446bcce9204537e Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 18:20:57 +0800 Subject: [PATCH 17/26] imx: mx6: Change the get_ipg_per_clk for OSC 24Mhz source For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix the get_ipg_per_clk function to support it. Signed-off-by: Ye.Li --- arch/arm/cpu/armv7/mx6/clock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index d200531030..6c9c78c11a 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -312,6 +312,10 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf; reg = __raw_readl(&imx_ccm->cscmr1); +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) + if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) + return MXC_HCLK; /* OSC 24Mhz */ +#endif perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; return get_ipg_clk() / (perclk_podf + 1); From 0f8ec145ba1354a479abecf7f83a86bb6db04ba2 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 18:20:58 +0800 Subject: [PATCH 18/26] imx: mx6sl: Set the preclk clock source to OSC 24Mhz For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li --- arch/arm/cpu/armv7/mx6/soc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 6dc26003b6..c0bb431412 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -239,6 +239,18 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); } +#ifdef CONFIG_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif + int arch_cpu_init(void) { init_aips(); @@ -254,6 +266,11 @@ int arch_cpu_init(void) if (mxc_get_clock(MXC_ARM_CLK) == 396000000) set_ahb_rate(132000000); + /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_MX6SL) + set_preclk_from_osc(); +#endif + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifdef CONFIG_APBH_DMA From f13ac7b2f0ab02d8536a5baf793a3227274388a2 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 18:20:59 +0800 Subject: [PATCH 19/26] imx: mx6: Enable high frequency clock source for GPT Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that 24Mhz OSC clock source will be selected for GPT on all MX6 platforms. Signed-off-by: Ye.Li --- include/configs/mx6_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 135a3f51f0..e0528ce4b9 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -29,5 +29,6 @@ #endif #define CONFIG_MP +#define CONFIG_MXC_GPT_HCLK #endif From 60b1e39586c038fd8b0d8301e73bdda5ecfdba89 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 18:30:53 +0800 Subject: [PATCH 20/26] imx: mx6sl: Add IOMUX setting for USDHC1-3 Set the USDHC1-3 IOMUX settings which are used for mx6slevk board. Signed-off-by: Ye.Li --- arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 045ccc4512..d9db58c9a3 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -14,12 +14,31 @@ enum { MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0), MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), From 36255d67790b5a4f086e2c157ecea2455df0b7ce Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 18:30:54 +0800 Subject: [PATCH 21/26] imx: mx6slevk: Add support for USDHC1 and USDHC3 slots There are three SD/MMC sockets on mx6slevk boards. Implements the full support for them. The default boot socket is USDHC2, so the MMC environment is set to that device. Signed-off-by: Ye.Li --- board/freescale/mx6slevk/mx6slevk.c | 105 ++++++++++++++++++++++++++-- include/configs/mx6slevk.h | 6 +- 2 files changed, 104 insertions(+), 7 deletions(-) diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index a500133efa..e76c343812 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -52,6 +52,23 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc1_pads[] = { + /* 8 bit SD */ + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -59,6 +76,21 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static iomux_v3_cfg_t const fec_pads[] = { @@ -109,21 +141,82 @@ static void setup_iomux_fec(void) gpio_set_value(ETH_PHY_RESET, 1); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR}, +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, }; int board_mmc_getcd(struct mmc *mmc) { - return 1; /* Assume boot SD always present */ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + int i, ret; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize " + "mmc dev %d\n", i); + return ret; + } + } + + return 0; } #ifdef CONFIG_FEC_MXC diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index fddedf1a8e..4fcaf515c7 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -190,7 +190,6 @@ #define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ @@ -210,4 +209,9 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ +#endif + #endif /* __CONFIG_H */ From 8fe280f330ddfd4a9e395ca15ab4019a1a32aa1f Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 30 Oct 2014 18:53:49 +0800 Subject: [PATCH 22/26] imx: mx6 sabreauto: Add board support for USB EHCI On mx6 sabreauto board, there are two USB ports: 0: OTG 1: HOST The EHCI driver is enabled for this board, but the IOMUX and VBUS power control is not implemented, which cause both USB port failed to work. This patch fix the problem by adding the board support codes. Since the power control uses the GPIO pin from port expander MAX7310, the PCA953X driver is enabled for accessing the MAX7310. The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting its daisy chain. Add a new function "imx_iomux_set_gpr_register" to handle GPR register setting. Signed-off-by: Ye.Li --- arch/arm/imx-common/iomux-v3.c | 15 +++ arch/arm/include/asm/imx-common/iomux-v3.h | 5 + board/freescale/mx6qsabreauto/mx6qsabreauto.c | 93 +++++++++++++++++++ include/configs/mx6qsabreauto.h | 3 + 4 files changed, 116 insertions(+) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 22cd11aa04..e88e6e2a98 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -77,3 +77,18 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, p += stride; } } + +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value) +{ + int i = 0; + u32 reg; + reg = readl(base + group * 4); + while (num_bits) { + reg &= ~(1<<(start_bit + i)); + i++; + num_bits--; + } + reg |= (value << start_bit); + writel(reg, base + group * 4); +} diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index a8ca49c343..e0a49be4ff 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -182,6 +182,11 @@ typedef u64 iomux_v3_cfg_t; void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count); +/* +* Set bits for general purpose registers +*/ +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value); /* macros for declaring and using pinmux array */ #if defined(CONFIG_MX6QDL) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 0dc0160e19..42ae6fac5e 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -27,6 +27,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -116,6 +117,44 @@ static iomux_v3_cfg_t const port_exp[] = { MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +/*Define for building port exp gpio, pin starts from 0*/ +#define PORTEXP_IO_NR(chip, pin) \ + ((chip << 5) + pin) + +/*Get the chip addr from a ioexp gpio*/ +#define PORTEXP_IO_TO_CHIP(gpio_nr) \ + (gpio_nr >> 5) + +/*Get the pin number from a ioexp gpio*/ +#define PORTEXP_IO_TO_PIN(gpio_nr) \ + (gpio_nr & 0x1f) + +static int port_exp_direction_output(unsigned gpio, int value) +{ + int ret; + + i2c_set_bus_num(2); + ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio)); + if (ret) + return ret; + + ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + return ret; + + ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (value << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + return ret; + + return 0; +} + static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); @@ -361,3 +400,57 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7) +#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1) + +iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + if (on) + port_exp_direction_output(USB_OTG_PWR, 1); + else + port_exp_direction_output(USB_OTG_PWR, 0); + break; + case 1: + if (on) + port_exp_direction_output(USB_HOST1_PWR, 1); + else + port_exp_direction_output(USB_HOST1_PWR, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 0ab31279cc..235dd6d33f 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -32,6 +32,9 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } + #include "mx6sabre_common.h" #define CONFIG_SYS_FSL_USDHC_NUM 2 From 2f6bb0a9419ec8016524142cb54fef81038b346e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 30 Oct 2014 13:14:03 +0100 Subject: [PATCH 23/26] arm, imx, spi: detect spi flash again on aristainetos board 155fa9af95a "spi: mxc: fix sf probe when using mxc_spi" break spi flash detection on the aristainetos board. Fix this. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 6 ++++++ include/configs/aristainetos.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 3bfcf5b0da..06922c0020 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -230,6 +230,12 @@ static iomux_v3_cfg_t const backlight_pads[] = { MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) + ? (IMX_GPIO_NR(3, 20)) : -1; +} + static void setup_spi(void) { int i; diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h index 20aea8572d..e6a08df4ba 100644 --- a/include/configs/aristainetos.h +++ b/include/configs/aristainetos.h @@ -77,7 +77,7 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 3 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)<<8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN From eb6b9f265c2902ae3864a891f51ed7ea6098097e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 30 Oct 2014 18:46:37 -0200 Subject: [PATCH 24/26] novena: Add MAINTAINERS file Commit f91c09acf5c58c ("ARM: mx6: Add support for Kosagi Novena") missed to add a MAINTAINERS file, so add Marek as the maintainer. Signed-off-by: Fabio Estevam --- board/kosagi/novena/MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 board/kosagi/novena/MAINTAINERS diff --git a/board/kosagi/novena/MAINTAINERS b/board/kosagi/novena/MAINTAINERS new file mode 100644 index 0000000000..d3471c2d65 --- /dev/null +++ b/board/kosagi/novena/MAINTAINERS @@ -0,0 +1,6 @@ +NOVENA BOARD +M: Marek Vasut +S: Maintained +F: board/kosagi/novena/ +F: include/configs/novena.h +F: configs/novena_defconfig From b65cbab194307d29cdff2e246e2f97738d9b6a15 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 29 Oct 2014 17:56:21 +0200 Subject: [PATCH 25/26] arm: mx6: cm_fx6: change issd gpio order Change the order in which GPIOs are toggled in SATA init sequence to accomodate both SanDisk and Phison SSDs. Signed-off-by: Nikita Kiryanov Cc: Igor Grinberg Cc: Stefano Babic Acked-by: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index fdb8ebf9e7..090f784cd9 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -29,12 +29,12 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_DWC_AHSATA static int cm_fx6_issd_gpios[] = { /* The order of the GPIOs in the array is important! */ + CM_FX6_SATA_LDO_EN, CM_FX6_SATA_PHY_SLP, CM_FX6_SATA_NRSTDLY, CM_FX6_SATA_PWREN, CM_FX6_SATA_NSTANDBY1, CM_FX6_SATA_NSTANDBY2, - CM_FX6_SATA_LDO_EN, }; static void cm_fx6_sata_power(int on) From 0b23780ff02bdbec46fac1fe4151e2ebf1eae881 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 29 Oct 2014 17:56:22 +0200 Subject: [PATCH 26/26] arm: mx6: cm_fx6: detect 1GB DRAM correctly on solo The 1GB DRAM configuration on mx6 solo uses 2 chip selects, but the code tests 1GB DRAM configuration as if it is all present on one chip select, and thus cannot see the full range of available memory. Refactor the check to detect 1GB DRAM correctly. Signed-off-by: Nikita Kiryanov Cc: Igor Grinberg Cc: Stefano Babic Acked-by: Igor Grinberg --- board/compulab/cm_fx6/spl.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c index 3948ba23ae..6fe937b418 100644 --- a/board/compulab/cm_fx6/spl.c +++ b/board/compulab/cm_fx6/spl.c @@ -235,10 +235,11 @@ static int cm_fx6_spl_dram_init(void) spl_mx6s_dram_init(DDR_32BIT_1GB, false); bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); - if (bank1_size == 0x40000000) - return 0; - + bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000); if (bank1_size == 0x20000000) { + if (bank2_size == 0x20000000) + return 0; + spl_mx6s_dram_init(DDR_32BIT_512MB, true); return 0; }