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mpc83xx: Introduce ARCH_MPC836* 

Replace CONFIG_MPC836* with proper CONFIG_ARCH_MPC836* Kconfig options.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six 2019-01-21 09:17:28 +01:00
parent d5cfa4aa5d
commit 61abced70f
12 changed files with 27 additions and 25 deletions
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4
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -80,6 +80,7 @@ config TARGET_IDS8313
config TARGET_KM8360
bool "Support km8360"
select ARCH_MPC8360
imply CMD_CRAMFS
imply CMD_DIAG
imply FS_CRAMFS
@ -147,6 +148,9 @@ config ARCH_MPC8349
bool
select ARCH_MPC834X
config ARCH_MPC8360
bool
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8308rdb/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"

10
arch/powerpc/cpu/mpc83xx/speed.c
View File

@ -113,7 +113,7 @@ int get_clocks(void)
u32 lbiu_clk;
u32 lclk_clk;
u32 mem_clk;
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
u32 mem_sec_clk;
#endif
#if defined(CONFIG_QE)
@ -313,7 +313,7 @@ int get_clocks(void)
#if defined(CONFIG_ARCH_MPC834X)
i2c1_clk = tsec2_clk;
#elif defined(CONFIG_MPC8360)
#elif defined(CONFIG_ARCH_MPC8360)
i2c1_clk = csb_clk;
#elif defined(CONFIG_ARCH_MPC832X)
i2c1_clk = enc_clk;
@ -407,7 +407,7 @@ int get_clocks(void)
(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
mem_sec_clk = csb_clk * (1 +
((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif
@ -476,7 +476,7 @@ int get_clocks(void)
gd->arch.lbiu_clk = lbiu_clk;
gd->arch.lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
gd->arch.mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_QE)
@ -536,7 +536,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf(" Local Bus: %-4s MHz\n",
strmhz(buf, gd->arch.lclk_clk));
printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
printf(" DDR Secondary: %-4s MHz\n",
strmhz(buf, gd->arch.mem_sec_clk));
#endif

4
arch/powerpc/include/asm/fsl_lbc.h
View File

@ -43,10 +43,10 @@ void lbc_sdram_init(void);
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_MPC8360)
#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
#define BR_MS_FCM 0x00000020 /* FCM */
#endif
#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */

4
arch/powerpc/include/asm/global_data.h
View File

@ -61,9 +61,9 @@ struct arch_global_data {
# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
# endif
# if defined(CONFIG_MPC8360)
# if defined(CONFIG_ARCH_MPC8360)
u32 mem_sec_clk;
# endif /* CONFIG_MPC8360 */
# endif /* CONFIG_ARCH_MPC8360 */
#endif
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)

2
arch/powerpc/include/asm/immap_83xx.h
View File

@ -803,7 +803,7 @@ typedef struct immap {
rom83xx_t rom; /* On Chip ROM */
} immap_t;
#elif defined(CONFIG_MPC8360)
#elif defined(CONFIG_ARCH_MPC8360)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */

4
board/keymile/km83xx/km83xx.c
View File

@ -33,7 +33,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
@ -148,7 +148,7 @@ int board_early_init_r(void)
u32 *mxmr = &lbc->mamr;
#endif
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
unsigned short svid;
/*
* Because of errata in the UCCs, we have to write to the reserved

8
drivers/ram/mpc83xx_sdram.c
View File

@ -169,7 +169,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
switch (odt_rd_cfg) {
case ODT_RD_ONLY_OTHER_DIMM:
if (!IS_ENABLED(CONFIG_MPC8360) &&
if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
@ -181,7 +181,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_RD_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
@ -200,7 +200,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
switch (odt_wr_cfg) {
case ODT_WR_ONLY_OTHER_DIMM:
if (!IS_ENABLED(CONFIG_MPC8360) &&
if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
@ -212,7 +212,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_WR_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);

1
include/configs/km8360.h
View File

@ -36,7 +36,6 @@
* High Level Configuration Options
*/
#define CONFIG_QE /* Has QE */
#define CONFIG_MPC8360 /* MPC8360 CPU specific */
/* include common defines/options for all 83xx Keymile boards */
#include "km/km83xx-common.h"

2
include/linux/immap_qe.h
View File

@ -12,7 +12,7 @@
#define __IMMAP_QE_H__
#ifdef CONFIG_MPC83xx
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28

10
include/mpc83xx.h
View File

@ -191,7 +191,7 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
#elif defined(CONFIG_MPC8360)
#elif defined(CONFIG_ARCH_MPC8360)
/* SICRL bits - MPC8360 specific */
#define SICRL_LDP_A 0xC0000000
#define SICRL_LCLK_1 0x10000000
@ -593,7 +593,7 @@
#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
#define HRCWL_CORE_TO_CSB_3X1 0x00060000
#if defined(CONFIG_MPC8360) || defined(CONFIG_ARCH_MPC832X)
#if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X)
#define HRCWL_CEVCOD 0x000000C0
#define HRCWL_CEVCOD_SHIFT 6
#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
@ -735,7 +735,7 @@
#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
#elif defined(CONFIG_MPC8360)
#elif defined(CONFIG_ARCH_MPC8360)
#define HRCWH_PCICKDRV_DISABLE 0x00000000
#define HRCWH_PCICKDRV_ENABLE 0x10000000
#endif
@ -801,7 +801,7 @@
#define HRCWH_TSEC2M_IN_TBI 0x00003000
#endif
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
#endif
@ -1129,7 +1129,7 @@
#elif defined(CONFIG_ARCH_MPC832X)
#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000

2
include/post.h
View File

@ -21,7 +21,7 @@
#define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR
#else
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
#include <linux/immap_qe.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)

1
scripts/config_whitelist.txt
View File

@ -1224,7 +1224,6 @@ CONFIG_MPC8313ERDB
CONFIG_MPC8315ERDB
CONFIG_MPC832XEMDS
CONFIG_MPC8349ITX
CONFIG_MPC8360
CONFIG_MPC837XEMDS
CONFIG_MPC837XERDB
CONFIG_MPC837x