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dts: powerpc: p2020rdb: Add eTSEC DT nodes

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P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII switch VSC7385
    eTSEC2: Connected to SGMII PHY VSC8221
    eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Hou Zhiqiang 2020-09-21 15:16:23 +05:30 committed by Tom Rini
parent 1e944259f5
commit 613e49bb91
8 changed files with 170 additions and 2 deletions
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8
arch/powerpc/dts/p2020-post.dtsi
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@ -47,8 +47,12 @@
status = "disabled";
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-etsec1-0.dtsi"
/include/ "pq3-etsec1-1.dtsi"
/include/ "pq3-etsec1-2.dtsi"
};
/* PCIe controller base address 0x8000 */

1
arch/powerpc/dts/p2020rdb-pc.dts
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@ -41,6 +41,7 @@
};
};
/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
&espi0 {

50
arch/powerpc/dts/p2020rdb-pc.dtsi Normal file
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@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&soc {
mdio@24520 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x1>;
};
};
mdio@25520 {
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26520 {
status = "disabled";
};
enet0: ethernet@24000 {
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
enet1: ethernet@25000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
};
enet2: ethernet@26000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};

1
arch/powerpc/dts/p2020rdb-pc_36b.dts
View File

@ -41,6 +41,7 @@
};
};
/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
&espi0 {

28
arch/powerpc/dts/pq3-etsec1-0.dtsi Normal file
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@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
};

28
arch/powerpc/dts/pq3-etsec1-1.dtsi Normal file
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@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
};
mdio@25520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
};

28
arch/powerpc/dts/pq3-etsec1-2.dtsi Normal file
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@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
};
mdio@26520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x26520 0x20>;
};

28
arch/powerpc/dts/pq3-etsec1-3.dtsi Normal file
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@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
};
mdio@27520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x27520 0x20>;
};