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powerpc/p4080: Add workaround for errata SERDES8
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
parent
34a8258fea
commit
61054ffa16
@ -41,6 +41,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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}
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}
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#endif
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
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puts("Work-around for Erratum SERDES8 enabled\n");
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#endif
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return 0;
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return 0;
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}
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}
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@ -21,10 +21,14 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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#include <hwconfig.h>
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#endif
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_serdes.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/fsl_law.h>
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#include "fsl_corenet_serdes.h"
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#include "fsl_corenet_serdes.h"
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static u32 serdes_prtcl_map;
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static u32 serdes_prtcl_map;
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@ -102,6 +106,13 @@ int serdes_lane_enabled(int lane)
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if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
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if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
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return 0;
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return 0;
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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if (!IS_SVR_REV(get_svr(), 1, 0))
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if (bank > 0)
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return !(srds_lpd_b[bank] &
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(8 >> (lane - (6 + 4 * bank))));
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#endif
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return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
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return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
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}
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}
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@ -116,6 +127,140 @@ int is_serdes_configured(enum srds_prtcl device)
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return (1 << device) & serdes_prtcl_map;
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return (1 << device) & serdes_prtcl_map;
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}
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}
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#ifndef CONFIG_SYS_DCSRBAR_PHYS
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#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
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#define CONFIG_SYS_DCSRBAR 0x80000000
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#define __DCSR_NOT_DEFINED_BY_CONFIG
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#endif
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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static void enable_bank(ccsr_gur_t *gur, int bank)
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{
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u32 rcw5;
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/*
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* Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
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* CCSR, and read/write in DSCR.
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*/
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rcw5 = in_be32(gur->rcwsr + 5);
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if (bank == FSL_SRDS_BANK_2) {
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rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
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rcw5 |= srds_lpd_b[bank] << 26;
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} else if (bank == FSL_SRDS_BANK_3) {
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rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
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rcw5 |= srds_lpd_b[bank] << 18;
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} else {
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printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
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return;
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}
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/* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
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* of the DCSR mapping.
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*/
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{
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#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
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struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
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int law_index;
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if (law.index == -1)
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law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
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LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
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else
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set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
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LAW_TRGT_IF_DCSR);
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#endif
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u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
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out_be32(p, rcw5);
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#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
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if (law.index == -1)
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disable_law(law_index);
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else
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set_law(law.index, law.addr, law.size, law.trgt_id);
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#endif
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}
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}
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/*
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* To avoid problems with clock jitter, rev 2 p4080 uses the pll from
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* bank 3 to clock banks 2 and 3, as well as a limited selection of
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* protocol configurations. This requires that banks 2 and 3's lanes be
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* disabled in the RCW, and enabled with some fixup here to re-enable
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* them, and to configure bank 2's clock parameters in bank 3's pll in
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* cases where they differ.
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*/
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static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
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u32 devdisr, u32 devdisr2, int cfg)
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{
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int srds_ratio_b2;
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int rfck_sel;
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/*
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* The disabled lanes of bank 2 will cause the associated
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* logic blocks to be disabled in DEVDISR. We reverse that here.
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*
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* Note that normally it is not permitted to clear DEVDISR bits
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* once the device has been disabled, but the hardware people
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* say that this special case is OK.
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*/
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clrbits_be32(&gur->devdisr, devdisr);
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clrbits_be32(&gur->devdisr2, devdisr2);
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/*
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* Some protocols require special handling. There are a few
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* additional protocol configurations that can be used, which are
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* not listed here. See app note 4065 for supported protocol
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* configurations.
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*/
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switch (cfg) {
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case 0x19:
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/*
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* Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
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* SGMII on bank 3 should still be usable.
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*/
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setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
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SRDS_PLLCR1_PLL_BWSEL);
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enable_bank(gur, FSL_SRDS_BANK_3);
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break;
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case 0x0f:
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case 0x10:
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/*
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* Banks 2 (XAUI) and 3 (SGMII) have different clocking
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* requirements in these configurations. Bank 3 cannot
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* be used and should have its lanes (but not the bank
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* itself) disabled in the RCW. We set up bank 3's pll
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* for bank 2's needs here.
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*/
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srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
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/* Determine refclock from XAUI ratio */
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switch (srds_ratio_b2) {
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case 1: /* 20:1 */
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rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
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break;
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case 2: /* 25:1 */
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rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
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break;
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default:
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printf("SERDES: bad SRDS_RATIO_B2 %d\n",
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srds_ratio_b2);
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return;
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}
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clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
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SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
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clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
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SRDS_PLLCR0_FRATE_SEL_MASK,
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SRDS_PLLCR0_FRATE_SEL_6_25);
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break;
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default:
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enable_bank(gur, FSL_SRDS_BANK_3);
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}
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}
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#endif
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void fsl_serdes_init(void)
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void fsl_serdes_init(void)
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{
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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@ -125,6 +270,13 @@ void fsl_serdes_init(void)
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enum srds_prtcl lane_prtcl;
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enum srds_prtcl lane_prtcl;
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long long end_tick;
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long long end_tick;
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int have_bank[SRDS_MAX_BANK] = {};
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int have_bank[SRDS_MAX_BANK] = {};
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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u32 serdes8_devdisr = 0;
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u32 serdes8_devdisr2 = 0;
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char srds_lpd_opt[16];
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const char *srds_lpd_arg;
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size_t arglen;
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#endif
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/* Is serdes enabled at all? */
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/* Is serdes enabled at all? */
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if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
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if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
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@ -139,6 +291,18 @@ void fsl_serdes_init(void)
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return;
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return;
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}
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}
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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if (!IS_SVR_REV(get_svr(), 1, 0))
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for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
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sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
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srds_lpd_arg = hwconfig_subarg("serdes", srds_lpd_opt,
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&arglen);
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if (srds_lpd_arg)
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srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg,
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NULL, 0);
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}
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#endif
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/* Look for banks with all lanes disabled, and power down the bank. */
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/* Look for banks with all lanes disabled, and power down the bank. */
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
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@ -148,6 +312,35 @@ void fsl_serdes_init(void)
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}
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}
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}
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}
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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if (IS_SVR_REV(get_svr(), 1, 0)) {
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/* At least one bank must be disabled due to SERDES8. If
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* no bank is found to be disabled based on lane
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* disables, disable bank 3 because we can't turn off its
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* lanes in the RCW without disabling MDIO due to erratum
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* GEN8.
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*
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* This means that if you are relying on bank 3 being
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* disabled to avoid SERDES8, in some cases you cannot
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* also disable all lanes of another bank, or else bank
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* 3 won't be disabled, leaving you with a configuration
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* that isn't valid according to SERDES8 (e.g. if banks
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* 2 and 3 have the same clock, and bank 1 is disabled
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* instead of 3).
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*/
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for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
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if (!have_bank[bank])
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break;
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}
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if (bank == SRDS_MAX_BANK)
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have_bank[FSL_SRDS_BANK_3] = 0;
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} else {
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if (have_bank[FSL_SRDS_BANK_2])
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have_bank[FSL_SRDS_BANK_3] = 1;
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}
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#endif
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for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
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for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
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if (!have_bank[bank]) {
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if (!have_bank[bank]) {
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printf("SERDES: bank %d disabled\n", bank + 1);
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printf("SERDES: bank %d disabled\n", bank + 1);
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@ -176,6 +369,68 @@ void fsl_serdes_init(void)
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}
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}
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printf("%s ", serdes_prtcl_str[lane_prtcl]);
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printf("%s ", serdes_prtcl_str[lane_prtcl]);
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#endif
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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switch (lane_prtcl) {
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case PCIE1:
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case PCIE2:
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case PCIE3:
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serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
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(lane_prtcl - PCIE1);
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break;
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case SRIO1:
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case SRIO2:
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serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
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(lane_prtcl - SRIO1);
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break;
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case SGMII_FM1_DTSEC1:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
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FSL_CORENET_DEVDISR2_DTSEC1_1;
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break;
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case SGMII_FM1_DTSEC2:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
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FSL_CORENET_DEVDISR2_DTSEC1_2;
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break;
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case SGMII_FM1_DTSEC3:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
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FSL_CORENET_DEVDISR2_DTSEC1_3;
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break;
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case SGMII_FM1_DTSEC4:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
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FSL_CORENET_DEVDISR2_DTSEC1_4;
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break;
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case SGMII_FM2_DTSEC1:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
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FSL_CORENET_DEVDISR2_DTSEC2_1;
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break;
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case SGMII_FM2_DTSEC2:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
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FSL_CORENET_DEVDISR2_DTSEC2_2;
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break;
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case SGMII_FM2_DTSEC3:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
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FSL_CORENET_DEVDISR2_DTSEC2_3;
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break;
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case SGMII_FM2_DTSEC4:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
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FSL_CORENET_DEVDISR2_DTSEC2_4;
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break;
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case XAUI_FM1:
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case XAUI_FM2:
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if (lane_prtcl == XAUI_FM1)
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
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FSL_CORENET_DEVDISR2_10GEC1;
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else
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
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FSL_CORENET_DEVDISR2_10GEC2;
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break;
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case AURORA:
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break;
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default:
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break;
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}
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#endif
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#endif
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}
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}
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@ -188,10 +443,38 @@ void fsl_serdes_init(void)
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bank = idx;
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bank = idx;
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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||||||
|
if (!IS_SVR_REV(get_svr(), 1, 0)) {
|
||||||
|
/*
|
||||||
|
* Change bank init order to 0, 2, 1, so that the
|
||||||
|
* third bank's PLL is established before we
|
||||||
|
* start the second bank which shares the third
|
||||||
|
* bank's PLL.
|
||||||
|
*/
|
||||||
|
|
||||||
|
if (idx == 1)
|
||||||
|
bank = FSL_SRDS_BANK_3;
|
||||||
|
else if (idx == 2)
|
||||||
|
bank = FSL_SRDS_BANK_2;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
/* Skip disabled banks */
|
/* Skip disabled banks */
|
||||||
if (!have_bank[bank])
|
if (!have_bank[bank])
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
|
||||||
|
if (!IS_SVR_REV(get_svr(), 1, 0)) {
|
||||||
|
if (idx == 1) {
|
||||||
|
p4080_erratum_serdes8(srds_regs, gur,
|
||||||
|
serdes8_devdisr,
|
||||||
|
serdes8_devdisr2, cfg);
|
||||||
|
} else if (idx == 2) {
|
||||||
|
enable_bank(gur, FSL_SRDS_BANK_2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
/* reset banks for errata */
|
/* reset banks for errata */
|
||||||
setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
|
setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
|
||||||
|
|
||||||
|
@ -37,4 +37,8 @@ int serdes_get_bank(int lane);
|
|||||||
int serdes_lane_enabled(int lane);
|
int serdes_lane_enabled(int lane);
|
||||||
enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
|
enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
|
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
|
||||||
|
extern uint16_t srds_lpd_b[SRDS_MAX_BANK];
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* __FSL_CORENET_SERDES_H */
|
#endif /* __FSL_CORENET_SERDES_H */
|
||||||
|
@ -71,6 +71,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
|
|||||||
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
|
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
|
||||||
|
uint16_t srds_lpd_b[SRDS_MAX_BANK];
|
||||||
|
#endif
|
||||||
|
|
||||||
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
|
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
|
||||||
{
|
{
|
||||||
if (!serdes_lane_enabled(lane))
|
if (!serdes_lane_enabled(lane))
|
||||||
|
Loading…
Reference in New Issue
Block a user