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mips: refactor disabling of caches
Logically this code belongs to cache_init.S. If a complex SoC needs to replace the generic cache init, mips_cache_disable() can now be called from custom start.S files. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
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@ -196,11 +196,10 @@ wr_done:
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mtc0 zero, CP0_COMPARE
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mtc0 zero, CP0_COMPARE
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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mfc0 t0, CP0_CONFIG
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/* Disable caches */
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and t0, t0, MIPS_CONF_IMPL
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PTR_LA t9, mips_cache_disable
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or t0, t0, CONF_CM_UNCACHED
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jalr t9
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mtc0 t0, CP0_CONFIG
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nop
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ehb
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#endif
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#endif
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#ifdef CONFIG_MIPS_CM
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#ifdef CONFIG_MIPS_CM
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@ -418,6 +418,12 @@ return:
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jr R_RETURN
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jr R_RETURN
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END(mips_cache_reset)
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END(mips_cache_reset)
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LEAF(mips_cache_disable)
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move R_RETURN, ra
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change_k0_cca_kseg1 CONF_CM_UNCACHED
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jr R_RETURN
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END(mips_cache_disable)
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LEAF(change_k0_cca)
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LEAF(change_k0_cca)
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mfc0 t0, CP0_CONFIG
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mfc0 t0, CP0_CONFIG
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#if __mips_isa_rev >= 2
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#if __mips_isa_rev >= 2
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