mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
arm: dts: arria10: Update dtsi/dts from Linux
Update these 3 files from Linux:. - socfpga_arria10.dtsi (Commit ID c1459a9d7e92) - socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b) - socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f) Change in socfpga_arria10.dtsi: - Add clkmgr label, so that can reference to it in u-boot.dtsi. Change in socfpga_arria10-u-boot.dtsi: - Add compatible and altr,sysmgr-syscon for uboot. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan
Marek Vasut
parent
f3fccb12c0
commit
5feb5e3215
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@ -38,6 +38,21 @@
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u-boot,dm-pre-reloc;
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};
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&gmac0 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x44 0>;
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};
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&gmac1 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x48 0>;
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};
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&gmac2 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
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};
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&i2c0 {
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reset-names = "i2c";
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};
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@ -1,17 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright Altera Corporation (C) 2014. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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@ -79,6 +68,8 @@
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#dma-requests = <32>;
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clocks = <&l4_main_clk>;
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clock-names = "apb_pclk";
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resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
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reset-names = "dma", "dma-ocp";
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};
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};
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@ -377,13 +368,28 @@
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clk-gate = <0xC8 11>;
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};
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nand_clk: nand_clk {
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nand_x_clk: nand_x_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_mp_clk>;
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clk-gate = <0xC8 10>;
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};
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nand_ecc_clk: nand_ecc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&nand_x_clk>;
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clk-gate = <0xC8 10>;
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};
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nand_clk: nand_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&nand_x_clk>;
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fixed-divider = <4>;
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clk-gate = <0xC8 10>;
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};
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spi_m_clk: spi_m_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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@ -414,7 +420,7 @@
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};
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gmac0: ethernet@ff800000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x44 0>;
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reg = <0xff800000 0x2000>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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@ -434,8 +440,8 @@
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};
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gmac1: ethernet@ff802000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x48 0>;
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compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x48 8>;
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reg = <0xff802000 0x2000>;
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interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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@ -454,8 +460,8 @@
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};
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gmac2: ethernet@ff804000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
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compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
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reg = <0xff804000 0x2000>;
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interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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@ -478,6 +484,7 @@
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02900 0x100>;
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resets = <&rst GPIO0_RESET>;
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status = "disabled";
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porta: gpio-controller@0 {
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@ -497,6 +504,7 @@
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02a00 0x100>;
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resets = <&rst GPIO1_RESET>;
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status = "disabled";
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portb: gpio-controller@0 {
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@ -516,6 +524,7 @@
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02b00 0x100>;
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resets = <&rst GPIO2_RESET>;
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status = "disabled";
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portc: gpio-controller@0 {
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@ -594,22 +603,35 @@
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status = "disabled";
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};
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spi0: spi@ffda4000 {
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compatible = "snps,dw-apb-ssi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xffda4000 0x100>;
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interrupts = <0 101 4>;
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num-cs = <4>;
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/*32bit_access;*/
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clocks = <&spi_m_clk>;
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resets = <&rst SPIM0_RESET>;
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status = "disabled";
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};
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spi1: spi@ffda5000 {
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compatible = "snps,dw-apb-ssi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xffda5000 0x100>;
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interrupts = <0 102 4>;
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num-chipselect = <4>;
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bus-num = <0>;
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num-cs = <4>;
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/*32bit_access;*/
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tx-dma-channel = <&pdma 16>;
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rx-dma-channel = <&pdma 17>;
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clocks = <&spi_m_clk>;
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resets = <&rst SPIM1_RESET>;
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status = "disabled";
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};
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sdr: sdr@ffc25000 {
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sdr: sdr@ffcfb100 {
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compatible = "altr,sdr-ctl", "syscon";
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reg = <0xffcfb100 0x80>;
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};
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@ -640,14 +662,14 @@
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nand: nand@ffb90000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
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reg = <0xffb90000 0x20>,
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<0xffb80000 0x1000>;
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#size-cells = <0>;
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compatible = "altr,socfpga-denali-nand";
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reg = <0xffb90000 0x72000>,
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<0xffb80000 0x10000>;
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reg-names = "nand_data", "denali_reg";
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interrupts = <0 99 4>;
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dma-mask = <0xffffffff>;
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clocks = <&nand_clk>;
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clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
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clock-names = "nand", "nand_x", "ecc";
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resets = <&rst NAND_RESET>;
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status = "disabled";
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};
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@ -733,6 +755,8 @@
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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clocks = <&qspi_clk>;
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resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
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reset-names = "qspi", "qspi-ocp";
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status = "disabled";
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};
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@ -758,7 +782,7 @@
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timer@ffffc600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xffffc600 0x100>;
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interrupts = <1 13 0xf04>;
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interrupts = <1 13 0xf01>;
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clocks = <&mpu_periph_clk>;
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};
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@ -768,6 +792,8 @@
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reg = <0xffc02700 0x100>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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resets = <&rst SPTIMER0_RESET>;
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reset-names = "timer";
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};
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timer1: timer1@ffc02800 {
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@ -776,6 +802,8 @@
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reg = <0xffc02800 0x100>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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resets = <&rst SPTIMER1_RESET>;
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reset-names = "timer";
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};
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timer2: timer2@ffd00000 {
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@ -784,6 +812,8 @@
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reg = <0xffd00000 0x100>;
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clocks = <&l4_sys_free_clk>;
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clock-names = "timer";
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resets = <&rst L4SYSTIMER0_RESET>;
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reset-names = "timer";
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};
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timer3: timer3@ffd00100 {
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@ -792,6 +822,8 @@
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reg = <0xffd01000 0x100>;
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clocks = <&l4_sys_free_clk>;
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clock-names = "timer";
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resets = <&rst L4SYSTIMER1_RESET>;
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reset-names = "timer";
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};
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uart0: serial0@ffc02000 {
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@ -853,6 +885,7 @@
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reg = <0xffd00200 0x100>;
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interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sys_free_clk>;
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resets = <&rst L4WD0_RESET>;
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status = "disabled";
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};
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@ -861,6 +894,7 @@
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reg = <0xffd00300 0x100>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sys_free_clk>;
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resets = <&rst L4WD1_RESET>;
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status = "disabled";
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};
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};
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@ -1,20 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "socfpga_arria10.dtsi"
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/ {
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@ -61,6 +48,22 @@
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};
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};
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ref_033v: 033-v-ref {
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compatible = "regulator-fixed";
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regulator-name = "0.33V";
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regulator-min-microvolt = <330000>;
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regulator-max-microvolt = <330000>;
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};
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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};
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};
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&gmac0 {
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@ -132,6 +135,18 @@
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i2c-sda-falling-time-ns = <6000>;
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i2c-scl-falling-time-ns = <6000>;
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adc@14 {
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compatible = "lltc,ltc2497";
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reg = <0x14>;
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vref-supply = <&ref_033v>;
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};
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adc@16 {
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compatible = "lltc,ltc2497";
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reg = <0x16>;
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vref-supply = <&ref_033v>;
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};
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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@ -1,18 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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@ -20,8 +8,8 @@
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&mmc {
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status = "okay";
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num-slots = <1>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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broken-cd;
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bus-width = <4>;
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};
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Reference in New Issue
Block a user