diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index df6e9aecbd..8640a5dc57 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -81,10 +81,14 @@ config TARGET_PWA7200 bool "Support PW-A7200 series" help Compatible with: - PW-G4200, PW-G5200, PW-G5300, PW-A7200, PW-A7300, PW-A7400, + PW-G4200, PW-G5200, PW-G5300, PW-A7200, PW-A7300, PW-A9100, PW-A9200, PW-A9300 select BOARD_EARLY_INIT_F +config TARGET_PWA7400 + bool "Support PW-A7400" + select BOARD_EARLY_INIT_F + endchoice config SYS_SOC @@ -101,5 +105,6 @@ source "board/sharp/pwsh5/Kconfig" source "board/sharp/pwsh6/Kconfig" source "board/sharp/pwsh7/Kconfig" source "board/sharp/pwa7200/Kconfig" +source "board/sharp/pwa7400/Kconfig" endif diff --git a/board/sharp/common/Kconfig b/board/sharp/common/Kconfig index a66066f0a1..60ba3a9b86 100644 --- a/board/sharp/common/Kconfig +++ b/board/sharp/common/Kconfig @@ -1,6 +1,6 @@ config BRAIN_2G bool - default y if TARGET_PWA7200 + default y if TARGET_PWA7200 || TARGET_PWA7400 config BRAIN_3G_4G bool @@ -9,13 +9,13 @@ config BRAIN_3G_4G config LCD_X string "LCD resolution X" - default 480 if TARGET_PWA7200 + default 480 if TARGET_PWA7200 || TARGET_PWA7400 default 800 if TARGET_PWSH1 || TARGET_PWSH2 default 854 if TARGET_PWSH3 || TARGET_PWSH4 || TARGET_PWSH5 || \ TARGET_PWSH6 || TARGET_PWSH7 config LCD_Y string "LCD resolution Y" - default 320 if TARGET_PWA7200 + default 320 if TARGET_PWA7200 || TARGET_PWA7400 default 480 if TARGET_PWSH1 || TARGET_PWSH2 || TARGET_PWSH3 || \ TARGET_PWSH4 || TARGET_PWSH5 || TARGET_PWSH6 || TARGET_PWSH7 diff --git a/board/sharp/pwa7400/Kconfig b/board/sharp/pwa7400/Kconfig new file mode 100644 index 0000000000..8f9b82b582 --- /dev/null +++ b/board/sharp/pwa7400/Kconfig @@ -0,0 +1,17 @@ +if TARGET_PWA7400 + +config SYS_BOARD + default "pwa7400" + +config SYS_VENDOR + default "sharp" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "pwa7400" + +endif + +source "board/sharp/common/Kconfig" diff --git a/board/sharp/pwa7400/MAINTAINERS b/board/sharp/pwa7400/MAINTAINERS new file mode 100644 index 0000000000..e9362c5a88 --- /dev/null +++ b/board/sharp/pwa7400/MAINTAINERS @@ -0,0 +1,6 @@ +PW-A7400 BOARD +M: Suguru Saito +S: Maintained +F: board/sharp/pwa7400/ +F: include/configs/pwa7400.h +F: configs/pwa7400_defconfig diff --git a/board/sharp/pwa7400/Makefile b/board/sharp/pwa7400/Makefile new file mode 100644 index 0000000000..8861c24060 --- /dev/null +++ b/board/sharp/pwa7400/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2024 Suguru Saito +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +ifndef CONFIG_SPL_BUILD +obj-y := pwa7400.o +else +obj-y := iomux.o +endif diff --git a/board/sharp/pwa7400/README b/board/sharp/pwa7400/README new file mode 100644 index 0000000000..7d9c56d26a --- /dev/null +++ b/board/sharp/pwa7400/README @@ -0,0 +1,12 @@ +SHARP Brain PW-A7400 +==================== + +Supports for PW-A7400. + +Files of the PW-A7400 port +-------------------------- + +arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 +arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 +board/sharp/pwa7400/ - PW-A7400 board specific files +include/configs/pwa7400.h - PW-A7400 configuration file diff --git a/board/sharp/pwa7400/iomux.c b/board/sharp/pwa7400/iomux.c new file mode 100644 index 0000000000..4bd49a442e --- /dev/null +++ b/board/sharp/pwa7400/iomux.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SHARP PW-A7400 IOMUX setup + * + * Copyright (C) 2024 Suguru Saito + * Copyright (C) 2020 Takumi Sueda + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#include +#include +#include +#include +#include +#include + +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP1 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_LCD (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SAIF (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) + +const iomux_cfg_t iomux_setup[] = { + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + //MX28_PAD_SSP1_SCK__GPIO_2_12, + /* eMMC power enable */ + MX28_PAD_PWM3__GPIO_3_28 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* MMC1 */ + MX28_PAD_GPMI_D00__SSP1_D0 | MUX_CONFIG_SSP1, + MX28_PAD_GPMI_D01__SSP1_D1 | MUX_CONFIG_SSP1, + MX28_PAD_GPMI_D02__SSP1_D2 | MUX_CONFIG_SSP1, + MX28_PAD_GPMI_D03__SSP1_D3 | MUX_CONFIG_SSP1, + MX28_PAD_GPMI_RDY1__SSP1_CMD | MUX_CONFIG_SSP1, + /*MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),*/ + MX28_PAD_GPMI_WRN__SSP1_SCK | MUX_CONFIG_SSP1, + /* SD slot power enable */ + MX28_PAD_SSP2_SS2__GPIO_2_21 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* USB */ + /*MX28_PAD_GPMI_RDY0__USB0_ID | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULLUP),*/ + + /* ENET0 */ + MX28_PAD_ENET0_COL__GPIO_4_14 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_TXD1__GPIO_4_8 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_TXD0__GPIO_4_7 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_TX_EN__GPIO_4_6 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_MDIO__GPIO_4_1 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_MDC__GPIO_4_0 | MUX_CONFIG_GPIO, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* SSP2 */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | MUX_CONFIG_SSP2, + /* SLCD reset? */ + MX28_PAD_SSP2_MISO__GPIO_2_18 | MUX_CONFIG_GPIO, + /* SLCD backlight control */ + MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_GPIO, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + MX28_PAD_PWM1__I2C1_SDA, + MX28_PAD_PWM0__I2C1_SCL, + + /* LCD */ + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_RD_E | MUX_CONFIG_LCD, + MX28_PAD_LCD_WR_RWN__LCD_WR_RWN | MUX_CONFIG_LCD, + MX28_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + /* LCD Regulator EN? */ + MX28_PAD_GPMI_ALE__GPIO_0_26 | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_CLE__GPIO_0_27 | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP), + /* LCD ? */ + MX28_PAD_ENET_CLK__GPIO_4_16 | MUX_CONFIG_LCD, + /* LCD backlight PWM */ + MX28_PAD_AUART1_RX__PWM_0 | MUX_CONFIG_GPIO, + MX28_PAD_AUART1_TX__PWM_1 | MUX_CONFIG_GPIO, + + /* GPIO */ + MX28_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_GPIO, + MX28_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_GPIO, + MX28_PAD_LCD_D18__GPIO_1_18 | MUX_CONFIG_GPIO, + MX28_PAD_LCD_D19__GPIO_1_19 | MUX_CONFIG_GPIO, + MX28_PAD_LCD_D20__GPIO_1_20 | MUX_CONFIG_GPIO, + MX28_PAD_LCD_D21__GPIO_1_21 | MUX_CONFIG_GPIO, + MX28_PAD_LCD_D22__GPIO_1_22 | MUX_CONFIG_GPIO, + MX28_PAD_LCD_D23__GPIO_1_23 | MUX_CONFIG_GPIO, + MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO, + MX28_PAD_SPDIF__GPIO_3_27 | MUX_CONFIG_GPIO, + MX28_PAD_SAIF1_SDATA0__GPIO_3_26 | MUX_CONFIG_GPIO, + MX28_PAD_PWM0__GPIO_3_16 | MUX_CONFIG_GPIO, + MX28_PAD_PWM1__GPIO_3_17 | MUX_CONFIG_GPIO, + MX28_PAD_AUART0_RTS__GPIO_3_3 | MUX_CONFIG_GPIO, + MX28_PAD_AUART0_CTS__GPIO_3_2 | MUX_CONFIG_GPIO, + MX28_PAD_AUART0_TX__GPIO_3_1 | MUX_CONFIG_GPIO, + MX28_PAD_AUART0_RX__GPIO_3_0 | MUX_CONFIG_GPIO, + + /* PWM */ + MX28_PAD_PWM4__PWM_4 | MUX_CONFIG_GPIO, + + /* SAIF0 */ + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | MUX_CONFIG_SAIF, + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | MUX_CONFIG_SAIF, + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | MUX_CONFIG_SAIF, + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | MUX_CONFIG_SAIF, +}; + +const static uint32_t lpddr_dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 000 - 003 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 004 - 007 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 008 - 011 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 012 - 015 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 016 - 019 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 020 - 023 + 0x00000000, 0x00000000, 0x00010101, 0x01010101, // 024 - 027 + 0x000f0f01, 0x0f02010a, 0x00000000, 0x00000101, // 028 - 031 + 0x00000100, 0x00000100, 0x01000000, 0x00000002, // 032 - 035 + 0x01010000, 0x08060301, 0x06000001, 0x0a000000, // 036 - 039 + 0x02009c40, 0x0002030b, 0x0036a608, 0x03160305, // 040 - 043 + 0x03030002, 0x001f001c, 0x00000000, 0x00000000, // 044 - 047 + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, // 048 - 051 + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, // 052 - 055 + 0x00000003, 0x00000000, 0x00000000, 0x00000000, // 056 - 059 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 060 - 063 + 0x00000000, 0x00000000, 0x00000305, 0x01000f02, // 064 - 067 + 0x00000000, 0x00000200, 0x00020007, 0xf3004a27, // 068 - 071 + 0xf3004a27, 0x00000000, 0x00000000, 0x07400310, // 072 - 075 + 0x07400310, 0x00000000, 0x00000000, 0x00800004, // 076 - 079 + 0x00000000, 0x00000000, 0x01000000, 0x01020408, // 080 - 083 + 0x08040201, 0x000f1133, 0x00000000, 0x00001f08, // 084 - 087 + 0x00001f08, 0x00000000, 0x00000000, 0x00001f01, // 088 - 091 + 0x00001f01, 0x00000000, 0x00000000, 0x00000000, // 092 - 095 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 096 - 099 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 100 - 103 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 104 - 107 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 108 - 111 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 112 - 115 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 116 - 119 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 120 - 123 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 124 - 127 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 128 - 131 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 132 - 135 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 136 - 139 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 140 - 143 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 144 - 147 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 148 - 151 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 152 - 155 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 156 - 159 + 0x00000000, 0x00000000, 0x00000000, 0x00010301, // 160 - 163 + 0x00000002, 0x00000000, 0x00000000, 0x00000000, // 164 - 167 + 0x00000000, 0x00000000, 0x00000000, 0x01010000, // 168 - 171 + 0x01000100, 0x03030000, 0x00020303, 0x01010202, // 172 - 175 + 0x00000000, 0x01030101, 0x21002101, 0x00030500, // 176 - 179 + 0x03050305, 0x00320032, 0x00320032, 0x00000000, // 180 - 183 + 0x00000000, 0x00000000, 0x00200020, 0x00200020, // 184 - 187 + 0x00000000, 0xffffffff // 188 - 189 +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + int i; + struct mxs_pinctrl_regs *pinctrl_regs = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; + + for (i = 0; i < ARRAY_SIZE(lpddr_dram_vals); i++) { + dram_vals[i] = lpddr_dram_vals[i]; + } + + /* Go into LPDDR mode */ + writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr); +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/sharp/pwa7400/pwa7400.c b/board/sharp/pwa7400/pwa7400.c new file mode 100644 index 0000000000..0b6e142313 --- /dev/null +++ b/board/sharp/pwa7400/pwa7400.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SHARP PW-A7400 + * + * (C) Copyright 2024 Suguru Saito. + * Author: Suguru Saito + * + * (C) Copyright 2020 Takumi Sueda. + * Author: Takumi Sueda + * + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * Author: Fabio Estevam + * + * Based on m28evk.c: + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/lcd.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP1 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK1, 96000, 0); + +#ifdef CONFIG_CMD_USB + mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); + mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | MXS_PAD_4MA | + MXS_PAD_3V3 | MXS_PAD_NOPULL); + gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_MMC +static int brain_mmc_wp(int id) +{ + return 0; +} + +static int brain_mmc_cd(int id) +{ + return 1; +} + +int board_mmc_init(struct bd_info *bis) +{ + mxsmmc_initialize(bis, 0, brain_mmc_wp, brain_mmc_cd); + mxsmmc_initialize(bis, 1, brain_mmc_wp, brain_mmc_cd); + + /* Turn on the SD */ + gpio_direction_output(MX28_PAD_SSP2_SS2__GPIO_2_21, 0); + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static const lcd_config_t lcd_config = { + .width = 480, + .height = 320, +}; + +lcd_config_t get_lcd_config() +{ + return lcd_config; +} +#endif diff --git a/configs/pwa7400_defconfig b/configs/pwa7400_defconfig new file mode 100644 index 0000000000..e35a1804f4 --- /dev/null +++ b/configs/pwa7400_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX28=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x4000 +CONFIG_SPL_TEXT_BASE=0x00001000 +CONFIG_TARGET_PWA7400=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="imx28-pwa7400.dtb" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_ARCH_MISC_INIT=y +# CONFIG_SPL_FRAMEWORK is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_MXS_GPIO=y +CONFIG_MMC_MXS=y +CONFIG_CONS_INDEX=0 +CONFIG_VIDEO=y +CONFIG_SPLASH_SCREEN=y +CONFIG_VIDEO_BMP_GZIP=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/pwa7400.h b/include/configs/pwa7400.h new file mode 100644 index 0000000000..e5e5ce5a14 --- /dev/null +++ b/include/configs/pwa7400.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2024 Suguru Saito. + * Author: Suguru Saito + * + * (C) Copyright 2011 Takumi Sueda. + * Author: Takumi Sueda + * + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * Author: Fabio Estevam + * + * Based on m28evk.h: + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ +#ifndef __CONFIGS_PWA7400_H__ +#define __CONFIGS_PWA7400_H__ + +/* Common configurations of Brain 2G, 3G, 4G */ +#include + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_PWA7400_H__ */ diff --git a/tools/logos/pwa7400.bmp b/tools/logos/pwa7400.bmp new file mode 120000 index 0000000000..e94b1676dd --- /dev/null +++ b/tools/logos/pwa7400.bmp @@ -0,0 +1 @@ +pwa7200.bmp \ No newline at end of file