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clk: clk_stm32f: Add set_rate for LTDC clock
Implement set_rate() for LTDC clock only, set_rate for other clocks will be added if needed. This is needed by future LTDC driver improvements. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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@ -136,6 +136,9 @@ struct stm32_clk {
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unsigned long hse_rate;
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unsigned long hse_rate;
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};
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};
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#ifdef CONFIG_VIDEO_STM32
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static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
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#endif
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static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
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static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
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static int configure_clocks(struct udevice *dev)
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static int configure_clocks(struct udevice *dev)
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@ -484,7 +487,104 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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static ulong stm32_set_rate(struct clk *clk, ulong rate)
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static ulong stm32_set_rate(struct clk *clk, ulong rate)
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{
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{
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#ifdef CONFIG_VIDEO_STM32
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struct stm32_clk *priv = dev_get_priv(clk->dev);
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struct stm32_rcc_regs *regs = priv->base;
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u32 pllsair_rate, pllsai_vco_rate, current_rate;
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u32 best_div, best_diff, diff;
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u16 div;
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u8 best_plldivr, best_pllsaidivr;
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u8 i, j;
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bool found = false;
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/* Only set_rate for LTDC clock is implemented */
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if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
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pr_err("set_rate not implemented for clock index %ld\n",
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clk->id);
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return 0;
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return 0;
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}
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if (rate == stm32_clk_get_rate(clk))
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/* already set to requested rate */
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return rate;
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/* get the current PLLSAIR output freq */
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pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
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best_div = pllsair_rate / rate;
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/* look into pllsaidivr_table if this divider is available*/
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for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
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if (best_div == pllsaidivr_table[i]) {
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/* set pll_saidivr with found value */
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clrsetbits_le32(®s->dckcfgr,
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RCC_DCKCFGR_PLLSAIDIVR_MASK,
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pllsaidivr_table[i]);
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return rate;
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}
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/*
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* As no pllsaidivr value is suitable to obtain requested freq,
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* test all combination of pllsaidivr * pllsair and find the one
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* which give freq closest to requested rate.
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*/
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pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
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best_diff = ULONG_MAX;
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best_pllsaidivr = 0;
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best_plldivr = 0;
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/*
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* start at index 2 of plldivr_table as divider value at index 0
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* and 1 are 0)
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*/
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for (i = 2; i < sizeof(plldivr_table); i++) {
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for (j = 0; j < sizeof(pllsaidivr_table); j++) {
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div = plldivr_table[i] * pllsaidivr_table[j];
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current_rate = pllsai_vco_rate / div;
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/* perfect combination is found ? */
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if (current_rate == rate) {
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best_pllsaidivr = j;
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best_plldivr = i;
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found = true;
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break;
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}
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diff = (current_rate > rate) ?
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current_rate - rate : rate - current_rate;
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/* found a better combination ? */
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if (diff < best_diff) {
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best_diff = diff;
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best_pllsaidivr = j;
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best_plldivr = i;
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}
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}
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if (found)
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break;
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}
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/* Disable the SAI PLL */
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clrbits_le32(®s->cr, RCC_CR_PLLSAION);
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/* set pll_saidivr with found value */
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clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
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best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
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/* set pllsair with found value */
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clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
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plldivr_table[best_plldivr]
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<< RCC_PLLSAICFGR_PLLSAIR_SHIFT);
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/* Enable the SAI PLL */
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setbits_le32(®s->cr, RCC_CR_PLLSAION);
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while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
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;
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div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
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return pllsai_vco_rate / div;
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#else
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return 0;
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#endif
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}
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}
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static int stm32_clk_enable(struct clk *clk)
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static int stm32_clk_enable(struct clk *clk)
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