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https://github.com/brain-hackers/u-boot-brain
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rockchip: rk3399: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
parent
474197812d
commit
5ce94c74a6
@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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@ -2,7 +2,6 @@ CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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