dma: ti: k3-udma: Update driver to use static endpoint Data
Update driver to use static PSIL endpoint Data instead of DT. This will allow DT bindings to be in sync with kernel's DT. Note that this patch breaks networking and OSPI boot as driver changes are not backward compatible with existing DT. Subsequent commit will update the DT to make it compatible with updated driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
This commit is contained in:
Vignesh Raghavendra
Lokesh Vutla
parent
53b04c6c09
commit
5c92fffab2
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@ -8,6 +8,7 @@ config TI_K3_NAVSS_UDMA
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select DMA
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select TI_K3_NAVSS_RINGACC
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select TI_K3_NAVSS_PSILCFG
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select TI_K3_PSIL
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default n
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help
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Support for UDMA used in K3 devices.
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@ -22,7 +22,6 @@
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#include <dma.h>
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#include <dma-uclass.h>
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#include <linux/delay.h>
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#include <dt-bindings/dma/k3-udma.h>
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#include <linux/bitmap.h>
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#include <linux/err.h>
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#include <linux/soc/ti/k3-navss-ringacc.h>
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@ -31,6 +30,7 @@
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#include <linux/soc/ti/ti_sci_protocol.h>
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#include "k3-udma-hwdef.h"
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#include "k3-psil-priv.h"
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#if BITS_PER_LONG == 64
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#define RINGACC_RING_USE_PROXY (0)
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@ -69,6 +69,21 @@ struct udma_rchan {
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struct k3_nav_ring *r_ring; /* Receive ring*/
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};
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#define UDMA_FLAG_PDMA_ACC32 BIT(0)
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#define UDMA_FLAG_PDMA_BURST BIT(1)
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#define UDMA_FLAG_TDTYPE BIT(2)
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struct udma_match_data {
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u32 psil_base;
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bool enable_memcpy_support;
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u32 flags;
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u32 statictr_z_mask;
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u32 rchan_oes_offset;
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u8 tpl_levels;
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u32 level_start_idx[];
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};
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struct udma_rflow {
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int id;
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};
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@ -114,6 +129,8 @@ struct udma_dev {
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struct udma_rchan *rchans;
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struct udma_rflow *rflows;
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struct udma_match_data *match_data;
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struct udma_chan *channels;
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u32 psil_base;
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@ -1293,12 +1310,8 @@ static int udma_probe(struct udevice *dev)
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if (IS_ERR(ud->ringacc))
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return PTR_ERR(ud->ringacc);
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ud->psil_base = dev_read_u32_default(dev, "ti,psil-base", 0);
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if (!ud->psil_base) {
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dev_info(dev,
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"Missing ti,psil-base property, using %d.\n", ret);
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return -EINVAL;
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}
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ud->match_data = (void *)dev_get_driver_data(dev);
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ud->psil_base = ud->match_data->psil_base;
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ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
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"ti,sci", &tisci_dev);
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@ -1723,8 +1736,7 @@ static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
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{
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struct udma_dev *ud = dev_get_priv(dma->dev);
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struct udma_chan *uc = &ud->channels[0];
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ofnode chconf_node, slave_node;
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char prop[50];
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struct psil_endpoint_config *ep_config;
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u32 val;
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for (val = 0; val < ud->ch_count; val++) {
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@ -1736,42 +1748,26 @@ static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
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if (val == ud->ch_count)
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return -EBUSY;
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uc->dir = DMA_DEV_TO_MEM;
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if (args->args[2] == UDMA_DIR_TX)
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uc->slave_thread_id = args->args[0];
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if (uc->slave_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)
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uc->dir = DMA_MEM_TO_DEV;
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else
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uc->dir = DMA_DEV_TO_MEM;
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slave_node = ofnode_get_by_phandle(args->args[0]);
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if (!ofnode_valid(slave_node)) {
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dev_err(ud->dev, "slave node is missing\n");
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return -EINVAL;
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ep_config = psil_get_ep_config(uc->slave_thread_id);
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if (IS_ERR(ep_config)) {
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dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
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uc->slave_thread_id);
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uc->dir = DMA_MEM_TO_MEM;
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uc->slave_thread_id = -1;
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return false;
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}
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snprintf(prop, sizeof(prop), "ti,psil-config%u", args->args[1]);
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chconf_node = ofnode_find_subnode(slave_node, prop);
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if (!ofnode_valid(chconf_node)) {
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dev_err(ud->dev, "Channel configuration node is missing\n");
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return -EINVAL;
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}
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uc->pkt_mode = ep_config->pkt_mode;
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if (!ofnode_read_u32(chconf_node, "linux,udma-mode", &val)) {
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if (val == UDMA_PKT_MODE)
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uc->pkt_mode = true;
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}
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if (!ofnode_read_u32(chconf_node, "statictr-type", &val))
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uc->static_tr_type = val;
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uc->needs_epib = ofnode_read_bool(chconf_node, "ti,needs-epib");
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if (!ofnode_read_u32(chconf_node, "ti,psd-size", &val))
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uc->psd_size = val;
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uc->metadata_size = (uc->needs_epib ? 16 : 0) + uc->psd_size;
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if (ofnode_read_u32(slave_node, "ti,psil-base", &val)) {
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dev_err(ud->dev, "ti,psil-base is missing\n");
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return -EINVAL;
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}
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uc->slave_thread_id = val + args->args[1];
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uc->needs_epib = ep_config->needs_epib;
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uc->psd_size = ep_config->psd_size;
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uc->metadata_size = (uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + uc->psd_size;
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dma->id = uc->id;
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pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
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@ -1859,10 +1855,73 @@ static const struct dma_ops udma_ops = {
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.get_cfg = udma_get_cfg,
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};
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static struct udma_match_data am654_main_data = {
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.psil_base = 0x1000,
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.enable_memcpy_support = true,
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.statictr_z_mask = GENMASK(11, 0),
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.rchan_oes_offset = 0x200,
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.tpl_levels = 2,
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.level_start_idx = {
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[0] = 8, /* Normal channels */
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[1] = 0, /* High Throughput channels */
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},
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};
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static struct udma_match_data am654_mcu_data = {
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.psil_base = 0x6000,
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.enable_memcpy_support = true,
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.statictr_z_mask = GENMASK(11, 0),
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.rchan_oes_offset = 0x200,
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.tpl_levels = 2,
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.level_start_idx = {
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[0] = 2, /* Normal channels */
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[1] = 0, /* High Throughput channels */
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},
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};
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static struct udma_match_data j721e_main_data = {
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.psil_base = 0x1000,
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.enable_memcpy_support = true,
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.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
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.statictr_z_mask = GENMASK(23, 0),
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.rchan_oes_offset = 0x400,
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.tpl_levels = 3,
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.level_start_idx = {
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[0] = 16, /* Normal channels */
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[1] = 4, /* High Throughput channels */
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[2] = 0, /* Ultra High Throughput channels */
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},
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};
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static struct udma_match_data j721e_mcu_data = {
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.psil_base = 0x6000,
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.enable_memcpy_support = true,
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.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
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.statictr_z_mask = GENMASK(23, 0),
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.rchan_oes_offset = 0x400,
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.tpl_levels = 2,
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.level_start_idx = {
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[0] = 2, /* Normal channels */
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[1] = 0, /* High Throughput channels */
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},
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};
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static const struct udevice_id udma_ids[] = {
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{ .compatible = "ti,k3-navss-udmap" },
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{ .compatible = "ti,j721e-navss-mcu-udmap" },
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{ }
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{
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.compatible = "ti,am654-navss-main-udmap",
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.data = (ulong)&am654_main_data,
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},
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{
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.compatible = "ti,am654-navss-mcu-udmap",
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.data = (ulong)&am654_mcu_data,
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}, {
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.compatible = "ti,j721e-navss-main-udmap",
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.data = (ulong)&j721e_main_data,
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}, {
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.compatible = "ti,j721e-navss-mcu-udmap",
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.data = (ulong)&j721e_mcu_data,
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},
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{ /* Sentinel */ },
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};
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U_BOOT_DRIVER(ti_edma3) = {
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