mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge git://git.denx.de/u-boot-marvell
This commit is contained in:
Tom Rini
commit
5c123f5fbf
6
Makefile
6
Makefile
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|
@ -856,12 +856,18 @@ MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
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|||
MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
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-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
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MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
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-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
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||||
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
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-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
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u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
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$(call if_changed,mkimage)
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u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
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$(call if_changed,mkimage)
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MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
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u-boot-dtb.img: u-boot-dtb.bin FORCE
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@ -236,10 +236,12 @@ config KIRKWOOD
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config TARGET_DB_MV784MP_GP
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bool "Support db-mv784mp-gp"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_MAXBCM
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bool "Support maxbcm"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_DEVKIT3250
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bool "Support devkit3250"
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|
|
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@ -5,3 +5,5 @@
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#
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obj-y = cpu.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
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|
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62
arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
Normal file
62
arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
Normal file
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@ -0,0 +1,62 @@
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/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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#include <linux/linkage.h>
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ENTRY(save_boot_params)
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bx lr
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ENDPROC(save_boot_params)
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/*
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* cache_inv - invalidate Cache line
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* r0 - dest
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*/
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.global cache_inv
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.type cache_inv, %function
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cache_inv:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c6, 1
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v6 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v6
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.type flush_l1_v6, %function
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flush_l1_v6:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v7 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v7
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.type flush_l1_v7, %function
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flush_l1_v7:
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stmfd sp!, {r1-r12}
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dmb /* @data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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dsb /* @data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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38
arch/arm/cpu/armv7/armada-xp/spl.c
Normal file
38
arch/arm/cpu/armv7/armada-xp/spl.c
Normal file
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@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 spl_boot_device(void)
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{
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/* Right now only booting via SPI NOR flash is supported */
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return BOOT_DEVICE_SPI;
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}
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void board_init_f(ulong dummy)
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{
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/* Set global data pointer */
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gd = &gdata;
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/* Linux expects the internal registers to be at 0xf1000000 */
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arch_cpu_init();
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preloader_console_init();
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/* First init the serdes PHY's */
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serdes_phy_config();
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/* Setup DDR */
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ddr3_init();
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board_init_r(NULL, 0);
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}
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@ -31,7 +31,11 @@
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#endif /* CONFIG_SYS_KWD_CONFIG */
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/* Add target to build it automatically upon "make" */
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#ifdef CONFIG_SPL
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#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
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#else
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#define CONFIG_BUILD_TARGET "u-boot.kwb"
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#endif
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/* end of 16M scrubbed by training in bootrom */
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#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
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@ -96,6 +96,9 @@ struct kwgpio_registers {
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u32 irq_level;
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};
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/* Needed for dynamic (board-specific) mbus configuration */
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extern struct mvebu_mbus_state mbus_state;
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/*
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* functions
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*/
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@ -103,5 +106,18 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
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unsigned int mvebu_sdram_bs(enum memory_bank bank);
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void mvebu_sdram_size_adjust(enum memory_bank bank);
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int mvebu_mbus_probe(struct mbus_win windows[], int count);
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/*
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* Highspeed SERDES PHY config init, ported from bin_hdr
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* to mainline U-Boot
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*/
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int serdes_phy_config(void);
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/*
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* DDR3 init / training code ported from Marvell bin_hdr. Now
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* available in mainline U-Boot in:
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* drivers/ddr/mvebu/
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*/
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int ddr3_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _ARMADA_XP_CPU_H */
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@ -10,3 +10,5 @@ obj-y = dram.o
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obj-y += gpio.o
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obj-$(CONFIG_ARMADA_XP) += mbus.o
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obj-y += timer.o
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obj-y += serdes/
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6
arch/arm/mvebu-common/serdes/Makefile
Normal file
6
arch/arm/mvebu-common/serdes/Makefile
Normal file
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@ -0,0 +1,6 @@
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|||
#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o
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obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
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262
arch/arm/mvebu-common/serdes/board_env_spec.h
Normal file
262
arch/arm/mvebu-common/serdes/board_env_spec.h
Normal file
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@ -0,0 +1,262 @@
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __BOARD_ENV_SPEC
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#define __BOARD_ENV_SPEC
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/* Board specific configuration */
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/* KW40 */
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#define MV_6710_DEV_ID 0x6710
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#define MV_6710_Z1_REV 0x0
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#define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV)
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#define MV_6710_Z1_NAME "MV6710 Z1"
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/* Armada XP Family */
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#define MV_78130_DEV_ID 0x7813
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#define MV_78160_DEV_ID 0x7816
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#define MV_78230_DEV_ID 0x7823
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#define MV_78260_DEV_ID 0x7826
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#define MV_78460_DEV_ID 0x7846
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#define MV_78000_DEV_ID 0x7888
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#define MV_FPGA_DEV_ID 0x2107
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#define MV_78XX0_Z1_REV 0x0
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/* boards ID numbers */
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#define BOARD_ID_BASE 0x0
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/* New board ID numbers */
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#define DB_88F78XX0_BP_ID (BOARD_ID_BASE)
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#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1)
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#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1)
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#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1)
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#define DB_88F78XX0_BP_REV2_ID (FPGA_88F78XX0_ID + 1)
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#define RD_78460_NAS_ID (DB_88F78XX0_BP_REV2_ID + 1)
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#define DB_78X60_AMC_ID (RD_78460_NAS_ID + 1)
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#define DB_78X60_PCAC_REV2_ID (DB_78X60_AMC_ID + 1)
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#define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1)
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#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
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#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
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#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
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#define INVALID_BAORD_ID 0xFFFFFFFF
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/* Sample at Reset */
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#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
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/* BIOS Modes related defines */
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#define SAR0_BOOTWIDTH_OFFSET 3
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#define SAR0_BOOTWIDTH_MASK (0x3 << SAR0_BOOTWIDTH_OFFSET)
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#define SAR0_BOOTSRC_OFFSET 5
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#define SAR0_BOOTSRC_MASK (0xF << SAR0_BOOTSRC_OFFSET)
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#define SAR0_L2_SIZE_OFFSET 19
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#define SAR0_L2_SIZE_MASK (0x3 << SAR0_L2_SIZE_OFFSET)
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#define SAR0_CPU_FREQ_OFFSET 21
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#define SAR0_CPU_FREQ_MASK (0x7 << SAR0_CPU_FREQ_OFFSET)
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#define SAR0_FABRIC_FREQ_OFFSET 24
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#define SAR0_FABRIC_FREQ_MASK (0xF << SAR0_FABRIC_FREQ_OFFSET)
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#define SAR0_CPU0CORE_OFFSET 31
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||||
#define SAR0_CPU0CORE_MASK (0x1 << SAR0_CPU0CORE_OFFSET)
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#define SAR1_CPU0CORE_OFFSET 0
|
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#define SAR1_CPU0CORE_MASK (0x1 << SAR1_CPU0CORE_OFFSET)
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||||
|
||||
#define PEX_CLK_100MHZ_OFFSET 2
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||||
#define PEX_CLK_100MHZ_MASK (0x1 << PEX_CLK_100MHZ_OFFSET)
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||||
|
||||
#define SAR1_FABRIC_MODE_OFFSET 19
|
||||
#define SAR1_FABRIC_MODE_MASK (0x1 << SAR1_FABRIC_MODE_OFFSET)
|
||||
#define SAR1_CPU_MODE_OFFSET 20
|
||||
#define SAR1_CPU_MODE_MASK (0x1 << SAR1_CPU_MODE_OFFSET)
|
||||
|
||||
#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
|
||||
|
||||
|
||||
#define CORE_AVS_CONTROL_0REG 0x18300
|
||||
#define CORE_AVS_CONTROL_2REG 0x18308
|
||||
#define CPU_AVS_CONTROL2_REG 0x20868
|
||||
#define CPU_AVS_CONTROL0_REG 0x20860
|
||||
#define GENERAL_PURPOSE_RESERVED0_REG 0x182E0
|
||||
|
||||
#define MSAR_TCLK_OFFS 28
|
||||
#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
|
||||
|
||||
|
||||
/* Controler environment registers offsets */
|
||||
#define GEN_PURP_RES_1_REG 0x182F4
|
||||
#define GEN_PURP_RES_2_REG 0x182F8
|
||||
|
||||
/* registers offsets */
|
||||
#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40))
|
||||
#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
|
||||
#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit))
|
||||
#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0)
|
||||
|
||||
#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
|
||||
#define GPP_DATA_OUT_REG_0 (MV_GPP_REGS_BASE_0 + 0x00) /* Used in .S files */
|
||||
#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
|
||||
#define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08)
|
||||
#define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C)
|
||||
#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
|
||||
#define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14)
|
||||
#define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18)
|
||||
#define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C)
|
||||
#define GPP_OUT_SET_REG(grp) (0x18130 + ((grp) * 0x40))
|
||||
#define GPP_64_66_DATA_OUT_SET_REG 0x181A4
|
||||
#define GPP_OUT_CLEAR_REG(grp) (0x18134 + ((grp) * 0x40))
|
||||
#define GPP_64_66_DATA_OUT_CLEAR_REG 0x181B0
|
||||
#define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40)
|
||||
|
||||
#define MV_GPP66 (1 << 2)
|
||||
|
||||
/* Relevant for MV78XX0 */
|
||||
#define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20)
|
||||
#define GPP_DATA_OUT_CLEAR_REG (MV_GPP_REGS_BASE(0) + 0x24)
|
||||
|
||||
/* This define describes the maximum number of supported PEX Interfaces */
|
||||
#define MV_PEX_MAX_IF 10
|
||||
#define MV_PEX_MAX_UNIT 4
|
||||
|
||||
#define MV_SERDES_NUM_TO_PEX_NUM(num) ((num < 8) ? (num) : (8 + (num / 12)))
|
||||
|
||||
#define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit) % 2 * 0x40000) + \
|
||||
((unit)/2 * 0x2000) + 0x1B00)
|
||||
|
||||
#define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000)
|
||||
|
||||
#define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804)
|
||||
#define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C)
|
||||
#define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918)
|
||||
#define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) + 0x920)
|
||||
#define SATA_LP_PHY_EXT_CTRL_REG(port) (SATA_BASE_REG(port) + 0x058)
|
||||
#define SATA_LP_PHY_EXT_STAT_REG(port) (SATA_BASE_REG(port) + 0x05C)
|
||||
#define SATA_IMP_TX_SSC_CTRL_REG(port) (SATA_BASE_REG(port) + 0x810)
|
||||
#define SATA_GEN_1_SET_0_REG(port) (SATA_BASE_REG(port) + 0x834)
|
||||
#define SATA_GEN_1_SET_1_REG(port) (SATA_BASE_REG(port) + 0x838)
|
||||
#define SATA_GEN_2_SET_0_REG(port) (SATA_BASE_REG(port) + 0x83C)
|
||||
#define SATA_GEN_2_SET_1_REG(port) (SATA_BASE_REG(port) + 0x840)
|
||||
|
||||
#define MV_ETH_BASE_ADDR (0x72000)
|
||||
#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * \
|
||||
0x40000 + ((port) % 2) * 0x4000)
|
||||
#define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port)
|
||||
|
||||
|
||||
#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04)
|
||||
#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C)
|
||||
#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18)
|
||||
#define SGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A0)
|
||||
#define SGMII_SERDES_STAT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A4)
|
||||
#define SGMII_COMPHY_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF20)
|
||||
#define QSGMII_GEN_1_SETTING_REG(port) (MV_ETH_REGS_BASE(port) + 0xE38)
|
||||
#define QSGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4a0)
|
||||
|
||||
#define SERDES_LINE_MUX_REG_0_7 0x18270
|
||||
#define SERDES_LINE_MUX_REG_8_15 0x18274
|
||||
#define QSGMII_CONTROL_1_REG 0x18404
|
||||
|
||||
/* SOC_CTRL_REG fields */
|
||||
#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3)
|
||||
#define SCR_PEX_ENA_MASK(pex) (1 << pex)
|
||||
|
||||
#define PCIE0_QUADX1_EN (1<<7)
|
||||
#define PCIE1_QUADX1_EN (1<<8)
|
||||
|
||||
#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7)
|
||||
#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex))
|
||||
|
||||
#define PCIE1_CLK_OUT_EN_OFF 5
|
||||
#define PCIE1_CLK_OUT_EN_MASK (1 << PCIE1_CLK_OUT_EN_OFF)
|
||||
|
||||
#define PCIE0_CLK_OUT_EN_OFF 4
|
||||
#define PCIE0_CLK_OUT_EN_MASK (1 << PCIE0_CLK_OUT_EN_OFF)
|
||||
|
||||
#define SCR_PEX0_4BY1_OFFS 7
|
||||
#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS)
|
||||
|
||||
#define SCR_PEX1_4BY1_OFFS 8
|
||||
#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS)
|
||||
|
||||
|
||||
#define MV_MISC_REGS_OFFSET (0x18200)
|
||||
#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET)
|
||||
#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
|
||||
|
||||
/*
|
||||
* PCI Express Control and Status Registers
|
||||
*/
|
||||
#define MAX_PEX_DEVICES 32
|
||||
#define MAX_PEX_FUNCS 8
|
||||
#define MAX_PEX_BUSSES 256
|
||||
|
||||
#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
|
||||
#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
|
||||
|
||||
#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
|
||||
#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
|
||||
|
||||
#define PXSR_DL_DOWN 0x1 /* DL_Down indication. */
|
||||
#define PXCAR_CONFIG_EN (1 << 31)
|
||||
#define PEX_STATUS_AND_COMMAND 0x004
|
||||
#define PXSAC_MABORT (1 << 29) /* Recieved Master Abort */
|
||||
|
||||
/* PCI Express Configuration Address Register */
|
||||
|
||||
/* PEX_CFG_ADDR_REG (PXCAR) */
|
||||
#define PXCAR_REG_NUM_OFFS 2
|
||||
#define PXCAR_REG_NUM_MAX 0x3F
|
||||
#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS)
|
||||
#define PXCAR_FUNC_NUM_OFFS 8
|
||||
#define PXCAR_FUNC_NUM_MAX 0x7
|
||||
#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS)
|
||||
#define PXCAR_DEVICE_NUM_OFFS 11
|
||||
#define PXCAR_DEVICE_NUM_MAX 0x1F
|
||||
#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS)
|
||||
#define PXCAR_BUS_NUM_OFFS 16
|
||||
#define PXCAR_BUS_NUM_MAX 0xFF
|
||||
#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS)
|
||||
#define PXCAR_EXT_REG_NUM_OFFS 24
|
||||
#define PXCAR_EXT_REG_NUM_MAX 0xF
|
||||
|
||||
#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
|
||||
#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
|
||||
|
||||
|
||||
#define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60)
|
||||
#define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C)
|
||||
#define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70)
|
||||
#define PEX_LINK_CTRL_STATUS2_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x90)
|
||||
#define PEX_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A00)
|
||||
#define PEX_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A04)
|
||||
#define PEX_COMPLT_TMEOUT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A10)
|
||||
#define PEX_PWR_MNG_EXT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A18)
|
||||
#define PEX_FLOW_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A20)
|
||||
#define PEX_DYNMC_WIDTH_MNG_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A30)
|
||||
#define PEX_ROOT_CMPLX_SSPL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A0C)
|
||||
#define PEX_RAM_PARITY_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A50)
|
||||
#define PEX_DBG_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A60)
|
||||
#define PEX_DBG_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A64)
|
||||
|
||||
#define PXLCSR_NEG_LNK_GEN_OFFS 16 /* Negotiated Link GEN */
|
||||
#define PXLCSR_NEG_LNK_GEN_MASK (0xf << PXLCSR_NEG_LNK_GEN_OFFS)
|
||||
#define PXLCSR_NEG_LNK_GEN_1_1 (0x1 << PXLCSR_NEG_LNK_GEN_OFFS)
|
||||
#define PXLCSR_NEG_LNK_GEN_2_0 (0x2 << PXLCSR_NEG_LNK_GEN_OFFS)
|
||||
|
||||
#define PEX_CFG_ADDR_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18F8)
|
||||
#define PEX_CFG_DATA_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18FC)
|
||||
#define PEX_CAUSE_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1900)
|
||||
|
||||
#define PEX_CAPABILITY_REG 0x60
|
||||
#define PEX_DEV_CAPABILITY_REG 0x64
|
||||
#define PEX_DEV_CTRL_STAT_REG 0x68
|
||||
#define PEX_LINK_CAPABILITY_REG 0x6C
|
||||
#define PEX_LINK_CTRL_STAT_REG 0x70
|
||||
#define PEX_LINK_CTRL_STAT_2_REG 0x90
|
||||
|
||||
#endif /* __BOARD_ENV_SPEC */
|
||||
1572
arch/arm/mvebu-common/serdes/high_speed_env_lib.c
Normal file
1572
arch/arm/mvebu-common/serdes/high_speed_env_lib.c
Normal file
File diff suppressed because it is too large
Load Diff
185
arch/arm/mvebu-common/serdes/high_speed_env_spec.c
Normal file
185
arch/arm/mvebu-common/serdes/high_speed_env_spec.c
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#include "high_speed_env_spec.h"
|
||||
|
||||
MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = {
|
||||
/* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */
|
||||
{
|
||||
/* PEX: Change of Slew Rate port0 */
|
||||
SERDES_UNIT_PEX, 0x0,
|
||||
(0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21
|
||||
}, {
|
||||
/* PEX: Change PLL BW port0 */
|
||||
SERDES_UNIT_PEX, 0x0,
|
||||
(0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219
|
||||
}, {
|
||||
/* SATA: Slew rate change port 0 */
|
||||
SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31
|
||||
}, {
|
||||
/* SATA: Slew rate change port 0 */
|
||||
SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928
|
||||
}, {
|
||||
/* SATA: Slew rate change port 0 */
|
||||
SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0
|
||||
}, {
|
||||
/* SATA: Slew rate change port 0 */
|
||||
SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5
|
||||
}, {
|
||||
/* SGMII: FFE setting Port0 */
|
||||
SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F
|
||||
}, {
|
||||
/* SGMII: SELMUP and SELMUF Port0 */
|
||||
SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA
|
||||
}, {
|
||||
/* SGMII: Amplitude new setting gen2 Port3 */
|
||||
SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C
|
||||
}, {
|
||||
/* QSGMII: Amplitude and slew rate change */
|
||||
SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58
|
||||
}, {
|
||||
/* QSGMII: SELMUP and SELMUF */
|
||||
SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF
|
||||
}, {
|
||||
/* QSGMII: 0x72e18 */
|
||||
SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC
|
||||
}, {
|
||||
/* Null terminated */
|
||||
SERDES_UNIT_UNCONNECTED, 0, 0
|
||||
}
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = {
|
||||
/* Z1B */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* Default */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* PEX module */
|
||||
/* Z1A */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000,
|
||||
{PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED,
|
||||
PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000,
|
||||
{PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
|
||||
0x0030, serdes_change_m_phy} /* PEX module - Z1A */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = {
|
||||
/* A0 */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = {
|
||||
{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy}, /* Default */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x00f4, serdes_change_m_phy}, /* Switch module */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = {
|
||||
{MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
|
||||
0x0010, serdes_change_m_phy}, /* CPU0 */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
|
||||
0x0010, serdes_change_m_phy} /* CPU1-3 */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = {
|
||||
{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
|
||||
0x0010, serdes_change_m_phy}, /* CPU0 */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
|
||||
0x0010, serdes_change_m_phy} /* CPU1-3 */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = {
|
||||
{MV_PEX_END_POINT, 0x22321111, 0x00000000,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
|
||||
0x0010, serdes_change_m_phy} /* Default */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = {
|
||||
{MV_PEX_END_POINT, 0x23321111, 0x00000000,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
|
||||
0x0010, serdes_change_m_phy} /* Default */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = {
|
||||
{MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000,
|
||||
{PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
|
||||
0x0000, serdes_change_m_phy} /* No PEX in FPGA */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = {
|
||||
{MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001,
|
||||
{PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1},
|
||||
0x0030, serdes_change_m_phy} /* Default */
|
||||
};
|
||||
|
||||
/*
|
||||
* ARMADA-XP CUSTOMER BOARD
|
||||
*/
|
||||
MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = {
|
||||
{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x00000030, serdes_change_m_phy}, /* Default */
|
||||
{MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x00000030, serdes_change_m_phy}, /* Switch module */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = {
|
||||
{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
|
||||
{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
|
||||
0x0030, serdes_change_m_phy} /* Default */
|
||||
};
|
||||
|
||||
MV_BIN_SERDES_CFG *serdes_info_tbl[] = {
|
||||
db88f78xx0_serdes_cfg,
|
||||
rd78460_serdes_cfg,
|
||||
db78X60pcac_serdes_cfg,
|
||||
fpga88f78xx0_serdes_cfg,
|
||||
db88f78xx0rev2_serdes_cfg,
|
||||
rd78460nas_serdes_cfg,
|
||||
db78X60amc_serdes_cfg,
|
||||
db78X60pcacrev2_serdes_cfg,
|
||||
rd78460server_rev2_serdes_cfg,
|
||||
rd78460AXP_GP_serdes_cfg,
|
||||
rd78460customer_serdes_cfg
|
||||
};
|
||||
|
||||
u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E };
|
||||
u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F };
|
||||
87
arch/arm/mvebu-common/serdes/high_speed_env_spec.h
Normal file
87
arch/arm/mvebu-common/serdes/high_speed_env_spec.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __HIGHSPEED_ENV_SPEC_H
|
||||
#define __HIGHSPEED_ENV_SPEC_H
|
||||
|
||||
#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
|
||||
|
||||
typedef enum {
|
||||
SERDES_UNIT_UNCONNECTED = 0x0,
|
||||
SERDES_UNIT_PEX = 0x1,
|
||||
SERDES_UNIT_SATA = 0x2,
|
||||
SERDES_UNIT_SGMII0 = 0x3,
|
||||
SERDES_UNIT_SGMII1 = 0x4,
|
||||
SERDES_UNIT_SGMII2 = 0x5,
|
||||
SERDES_UNIT_SGMII3 = 0x6,
|
||||
SERDES_UNIT_QSGMII = 0x7,
|
||||
SERDES_UNIT_SETM = 0x8,
|
||||
SERDES_LAST_UNIT
|
||||
} MV_BIN_SERDES_UNIT_INDX;
|
||||
|
||||
|
||||
typedef enum {
|
||||
PEX_BUS_DISABLED = 0,
|
||||
PEX_BUS_MODE_X1 = 1,
|
||||
PEX_BUS_MODE_X4 = 2,
|
||||
PEX_BUS_MODE_X8 = 3
|
||||
} MV_PEX_UNIT_CFG;
|
||||
|
||||
typedef enum pex_type {
|
||||
MV_PEX_ROOT_COMPLEX, /* root complex device */
|
||||
MV_PEX_END_POINT /* end point device */
|
||||
} MV_PEX_TYPE;
|
||||
|
||||
typedef struct serdes_change_m_phy {
|
||||
MV_BIN_SERDES_UNIT_INDX type;
|
||||
u32 reg_low_speed;
|
||||
u32 val_low_speed;
|
||||
u32 reg_hi_speed;
|
||||
u32 val_hi_speed;
|
||||
} MV_SERDES_CHANGE_M_PHY;
|
||||
|
||||
/*
|
||||
* Configuration per SERDES line. Each nibble is MV_SERDES_LINE_TYPE
|
||||
*/
|
||||
typedef struct board_serdes_conf {
|
||||
MV_PEX_TYPE pex_type; /* MV_PEX_ROOT_COMPLEX MV_PEX_END_POINT */
|
||||
u32 line0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */
|
||||
u32 line8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */
|
||||
MV_PEX_UNIT_CFG pex_mode[4];
|
||||
|
||||
/*
|
||||
* Bus speed - one bit per SERDES line:
|
||||
* Low speed (0) High speed (1)
|
||||
* PEX 2.5 G (10 bit) 5 G (20 bit)
|
||||
* SATA 1.5 G 3 G
|
||||
* SGMII 1.25 Gbps 3.125 Gbps
|
||||
*/
|
||||
u32 bus_speed;
|
||||
|
||||
MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
|
||||
} MV_BIN_SERDES_CFG;
|
||||
|
||||
|
||||
#define BIN_SERDES_CFG { \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
|
||||
{0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
|
||||
{0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
|
||||
{0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
|
||||
{0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
|
||||
{0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
|
||||
{0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 8 */ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 9 */ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 10 */ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 11 */ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 12 */ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 13 */ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 14 */ \
|
||||
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 15 */ \
|
||||
}
|
||||
|
||||
#endif /* __HIGHSPEED_ENV_SPEC_H */
|
||||
57
arch/arm/mvebu-common/u-boot-spl.lds
Normal file
57
arch/arm/mvebu-common/u-boot-spl.lds
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
|
||||
LENGTH = CONFIG_SPL_MAX_SIZE }
|
||||
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
|
||||
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__start = .;
|
||||
arch/arm/cpu/armv7/start.o (.text*)
|
||||
*(.text*)
|
||||
*(.vectors)
|
||||
} >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*_i2c_*)));
|
||||
} >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
|
||||
.end :
|
||||
{
|
||||
*(.__end)
|
||||
}
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} >.sdram
|
||||
}
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
--------
|
||||
WARNING:
|
||||
--------
|
||||
This file should contain the bin_hdr generated by the original Marvell
|
||||
U-Boot implementation. As this is currently not included in this
|
||||
U-Boot version, we have added this placeholder, so that the U-Boot
|
||||
image can be generated without errors.
|
||||
|
||||
If you have a known to be working bin_hdr for your board, then you
|
||||
just need to replace this text file here with the binary header
|
||||
and recompile U-Boot.
|
||||
|
||||
In a few weeks, mainline U-Boot will get support to generate the
|
||||
bin_hdr with the DDR training code itself. By implementing this code
|
||||
as SPL U-Boot. Then this file will not be needed any more and will
|
||||
get removed.
|
||||
|
||||
|
|
@ -9,4 +9,4 @@ VERSION 1
|
|||
BOOT_FROM spi
|
||||
|
||||
# Binary Header (bin_hdr) with DDR3 training code
|
||||
BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068
|
||||
BINARY spl/u-boot-spl.bin 0000005b 00000068
|
||||
|
|
|
|||
|
|
@ -1,17 +0,0 @@
|
|||
--------
|
||||
WARNING:
|
||||
--------
|
||||
This file should contain the bin_hdr generated by the original Marvell
|
||||
U-Boot implementation. As this is currently not included in this
|
||||
U-Boot version, we have added this placeholder, so that the U-Boot
|
||||
image can be generated without errors.
|
||||
|
||||
If you have a known to be working bin_hdr for your board, then you
|
||||
just need to replace this text file here with the binary header
|
||||
and recompile U-Boot.
|
||||
|
||||
In a few weeks, mainline U-Boot will get support to generate the
|
||||
bin_hdr with the DDR training code itself. By implementing this code
|
||||
as SPL U-Boot. Then this file will not be needed any more and will
|
||||
get removed.
|
||||
|
||||
|
|
@ -9,4 +9,4 @@ VERSION 1
|
|||
BOOT_FROM spi
|
||||
|
||||
# Binary Header (bin_hdr) with DDR3 training code
|
||||
BINARY board/maxbcm/binary.0 0000005b 00000068
|
||||
BINARY spl/u-boot-spl.bin 0000005b 00000068
|
||||
|
|
|
|||
|
|
@ -11,6 +11,9 @@
|
|||
#include <asm/arch/soc.h>
|
||||
#include <linux/mbus.h>
|
||||
|
||||
#include "../drivers/ddr/mvebu/ddr3_hw_training.h"
|
||||
#include "../arch/arm/mvebu-common/serdes/high_speed_env_spec.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Base addresses for the external device chip selects */
|
||||
|
|
@ -19,8 +22,84 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define DEV_CS2_BASE 0xe2000000
|
||||
#define DEV_CS3_BASE 0xe3000000
|
||||
|
||||
/* Needed for dynamic (board-specific) mbus configuration */
|
||||
extern struct mvebu_mbus_state mbus_state;
|
||||
/* DDR3 static configuration */
|
||||
MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
{0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
|
||||
{0x00001404, 0x30000820}, /* Dunit Control Low Register */
|
||||
{0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
|
||||
{0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
|
||||
{0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
|
||||
{0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
|
||||
{0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */
|
||||
{0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */
|
||||
{0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */
|
||||
{0x00001424, 0x0000F3FF}, /* Dunit Control High Register */
|
||||
{0x00001428, 0x0011A940}, /* Dunit Control High Register */
|
||||
{0x0000142C, 0x014C5134}, /* Dunit Control High Register */
|
||||
{0x0000147C, 0x0000D771},
|
||||
|
||||
{0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
|
||||
{0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
|
||||
{0x000014A0, 0x00000001},
|
||||
{0x000014A8, 0x00000101},
|
||||
|
||||
/* Recommended Settings from Marvell for 4 x 16 bit devices: */
|
||||
{0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/
|
||||
{0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */
|
||||
|
||||
/*
|
||||
* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
|
||||
* training sequence
|
||||
*/
|
||||
{0x000200e8, 0x3FFF0E01},
|
||||
{0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */
|
||||
|
||||
{0x0001504, 0x3FFFFFE1}, /* CS0 Size */
|
||||
{0x000150C, 0x00000000}, /* CS1 Size */
|
||||
{0x0001514, 0x00000000}, /* CS2 Size */
|
||||
{0x000151C, 0x00000000}, /* CS3 Size */
|
||||
|
||||
{0x0020220, 0x00000007}, /* Reserved */
|
||||
|
||||
{0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */
|
||||
|
||||
{0x000015D0, 0x00000670}, /* MR0 */
|
||||
{0x000015D4, 0x00000044}, /* MR1 */
|
||||
{0x000015D8, 0x00000018}, /* MR2 */
|
||||
{0x000015DC, 0x00000000}, /* MR3 */
|
||||
{0x000015E0, 0x00000001},
|
||||
{0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
|
||||
{0x000015EC, 0xF800A225}, /* DDR PHY */
|
||||
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = {
|
||||
{"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL},
|
||||
};
|
||||
|
||||
extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
|
||||
|
||||
/* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */
|
||||
MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = {
|
||||
{ MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000,
|
||||
{ PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
|
||||
PEX_BUS_DISABLED },
|
||||
0x1f, serdes_change_m_phy
|
||||
}
|
||||
};
|
||||
|
||||
MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
|
||||
{
|
||||
/* Only one mode supported for this board */
|
||||
return &maxbcm_ddr_modes[0];
|
||||
}
|
||||
|
||||
MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
|
||||
{
|
||||
return &maxbcm_serdes_cfg[0];
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
|
|
@ -63,9 +142,7 @@ int checkboard(void)
|
|||
/* Configure and enable MV88E6185 switch */
|
||||
void reset_phy(void)
|
||||
{
|
||||
u16 devadr = CONFIG_PHY_BASE_ADDR;
|
||||
char *name = "neta0";
|
||||
u16 reg;
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_DB_MV784MP_GP=y
|
||||
CONFIG_SPL=y
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_DB_MV784MP_GP=y
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_MAXBCM=y
|
||||
CONFIG_SPL=y
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_MAXBCM=y
|
||||
|
|
|
|||
14
drivers/ddr/mvebu/Makefile
Normal file
14
drivers/ddr/mvebu/Makefile
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_dfs.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_dqs.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_hw_training.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_pbs.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_read_leveling.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_sdram.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_spd.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr3_write_leveling.o
|
||||
obj-$(CONFIG_SPL_BUILD) += xor.o
|
||||
510
drivers/ddr/mvebu/ddr3_axp.h
Normal file
510
drivers/ddr/mvebu/ddr3_axp.h
Normal file
|
|
@ -0,0 +1,510 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __DDR3_AXP_H
|
||||
#define __DDR3_AXP_H
|
||||
|
||||
#define MV_78XX0_Z1_REV 0x0
|
||||
#define MV_78XX0_A0_REV 0x1
|
||||
#define MV_78XX0_B0_REV 0x2
|
||||
|
||||
#define SAR_DDR3_FREQ_MASK 0xFE00000
|
||||
#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
|
||||
|
||||
#define MAX_CS 4
|
||||
|
||||
#define MIN_DIMM_ADDR 0x50
|
||||
#define FAR_END_DIMM_ADDR 0x50
|
||||
#define MAX_DIMM_ADDR 0x60
|
||||
|
||||
#ifndef CONFIG_DDR_FIXED_SIZE
|
||||
#define SDRAM_CS_SIZE 0xFFFFFFF
|
||||
#else
|
||||
#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1)
|
||||
#endif
|
||||
#define SDRAM_CS_BASE 0x0
|
||||
#define SDRAM_DIMM_SIZE 0x80000000
|
||||
|
||||
#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
|
||||
#define CPU_MRVL_ID_OFFSET 0x10
|
||||
#define SAR1_CPU_CORE_MASK 0x00000018
|
||||
#define SAR1_CPU_CORE_OFFSET 3
|
||||
|
||||
#define ECC_SUPPORT
|
||||
#define NEW_FABRIC_TWSI_ADDR 0x4E
|
||||
#ifdef DB_784MP_GP
|
||||
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
|
||||
#else
|
||||
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4F
|
||||
#endif
|
||||
#define MV_MAX_DDR3_STATIC_SIZE 50
|
||||
#define MV_DDR3_MODES_NUMBER 30
|
||||
|
||||
#define RESUME_RL_PATTERNS_ADDR (0xFE0000)
|
||||
#define RESUME_RL_PATTERNS_SIZE (0x100)
|
||||
#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + RESUME_RL_PATTERNS_SIZE)
|
||||
#define RESUME_TRAINING_VALUES_MAX (0xCD0)
|
||||
#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000)
|
||||
#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000)
|
||||
#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4)
|
||||
#define SUSPEND_MAGIC_WORD (0xDEADB002)
|
||||
#define REGISTER_LIST_END (0xFFFFFFFF)
|
||||
|
||||
/*
|
||||
* Registers offset
|
||||
*/
|
||||
|
||||
#define REG_SAMPLE_RESET_LOW_ADDR 0x18230
|
||||
#define REG_SAMPLE_RESET_HIGH_ADDR 0x18234
|
||||
#define REG_SAMPLE_RESET_CPU_FREQ_OFFS 21
|
||||
#define REG_SAMPLE_RESET_CPU_FREQ_MASK 0x00E00000
|
||||
#define REG_SAMPLE_RESET_FAB_OFFS 24
|
||||
#define REG_SAMPLE_RESET_FAB_MASK 0xF000000
|
||||
#define REG_SAMPLE_RESET_TCLK_OFFS 28
|
||||
#define REG_SAMPLE_RESET_CPU_ARCH_OFFS 31
|
||||
#define REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS 20
|
||||
|
||||
/* MISC */
|
||||
/*
|
||||
* In mainline U-Boot we're re-configuring the mvebu base address
|
||||
* register to 0xf1000000. So need to use this value for the DDR
|
||||
* training code as well.
|
||||
*/
|
||||
#define INTER_REGS_BASE SOC_REGS_PHY_BASE
|
||||
|
||||
/* DDR */
|
||||
#define REG_SDRAM_CONFIG_ADDR 0x1400
|
||||
#define REG_SDRAM_CONFIG_MASK 0x9FFFFFFF
|
||||
#define REG_SDRAM_CONFIG_RFRS_MASK 0x3FFF
|
||||
#define REG_SDRAM_CONFIG_WIDTH_OFFS 15
|
||||
#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17
|
||||
#define REG_SDRAM_CONFIG_ECC_OFFS 18
|
||||
#define REG_SDRAM_CONFIG_IERR_OFFS 19
|
||||
#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28
|
||||
#define REG_SDRAM_CONFIG_RSTRD_OFFS 30
|
||||
|
||||
#define REG_DUNIT_CTRL_LOW_ADDR 0x1404
|
||||
#define REG_DUNIT_CTRL_LOW_2T_OFFS 3
|
||||
#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3
|
||||
#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14
|
||||
|
||||
#define REG_SDRAM_TIMING_LOW_ADDR 0x1408
|
||||
|
||||
#define REG_SDRAM_TIMING_HIGH_ADDR 0x140C
|
||||
#define REG_SDRAM_TIMING_H_R2R_OFFS 7
|
||||
#define REG_SDRAM_TIMING_H_R2R_MASK 0x3
|
||||
#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9
|
||||
#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3
|
||||
#define REG_SDRAM_TIMING_H_W2W_OFFS 11
|
||||
#define REG_SDRAM_TIMING_H_W2W_MASK 0x1F
|
||||
#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19
|
||||
#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7
|
||||
#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22
|
||||
#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7
|
||||
|
||||
#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410
|
||||
#define REG_SDRAM_ADDRESS_SIZE_OFFS 2
|
||||
#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18
|
||||
#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4
|
||||
|
||||
#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414
|
||||
#define REG_SDRAM_OPERATION_CS_OFFS 8
|
||||
|
||||
#define REG_SDRAM_OPERATION_ADDR 0x1418
|
||||
#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24
|
||||
#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20
|
||||
#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xF
|
||||
#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16
|
||||
#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xF
|
||||
#define REG_SDRAM_OPERATION_CMD_MR0 0xF03
|
||||
#define REG_SDRAM_OPERATION_CMD_MR1 0xF04
|
||||
#define REG_SDRAM_OPERATION_CMD_MR2 0xF08
|
||||
#define REG_SDRAM_OPERATION_CMD_MR3 0xF09
|
||||
#define REG_SDRAM_OPERATION_CMD_RFRS 0xF02
|
||||
#define REG_SDRAM_OPERATION_CMD_CWA 0xF0E
|
||||
#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xF
|
||||
#define REG_SDRAM_OPERATION_CMD_MASK 0xF
|
||||
#define REG_SDRAM_OPERATION_CS_OFFS 8
|
||||
|
||||
#define REG_OUDDR3_TIMING_ADDR 0x142C
|
||||
|
||||
#define REG_SDRAM_MODE_ADDR 0x141C
|
||||
|
||||
#define REG_SDRAM_EXT_MODE_ADDR 0x1420
|
||||
|
||||
#define REG_DDR_CONT_HIGH_ADDR 0x1424
|
||||
|
||||
#define REG_ODT_TIME_LOW_ADDR 0x1428
|
||||
#define REG_ODT_ON_CTL_RD_OFFS 12
|
||||
#define REG_ODT_OFF_CTL_RD_OFFS 16
|
||||
#define REG_SDRAM_ERROR_ADDR 0x1454
|
||||
#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474
|
||||
#define REG_ODT_TIME_HIGH_ADDR 0x147C
|
||||
|
||||
#define REG_SDRAM_INIT_CTRL_ADDR 0x1480
|
||||
#define REG_SDRAM_INIT_CTRL_OFFS 0
|
||||
#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2
|
||||
#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3
|
||||
|
||||
#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494
|
||||
|
||||
#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498
|
||||
/*#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0xFFFFFF55 */
|
||||
#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0
|
||||
#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3
|
||||
|
||||
#define REG_DUNIT_ODT_CTRL_ADDR 0x149C
|
||||
#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8
|
||||
#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9
|
||||
|
||||
#define REG_DRAM_FIFO_CTRL_ADDR 0x14A0
|
||||
|
||||
#define REG_DRAM_AXI_CTRL_ADDR 0x14A8
|
||||
#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0
|
||||
|
||||
#define REG_METAL_MASK_ADDR 0x14B0
|
||||
#define REG_METAL_MASK_MASK 0xDFFFFFFF
|
||||
#define REG_METAL_MASK_RETRY_OFFS 0
|
||||
|
||||
#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14C0
|
||||
|
||||
#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14C4
|
||||
#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8
|
||||
#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14CC
|
||||
|
||||
#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8
|
||||
|
||||
#define REG_CS_SIZE_SCRATCH_ADDR 0x1504
|
||||
#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520
|
||||
#define REG_DDR_IO_ADDR 0x1524
|
||||
#define REG_DDR_IO_CLK_RATIO_OFFS 15
|
||||
|
||||
#define REG_DFS_ADDR 0x1528
|
||||
#define REG_DFS_DLLNEXTSTATE_OFFS 0
|
||||
#define REG_DFS_BLOCK_OFFS 1
|
||||
#define REG_DFS_SR_OFFS 2
|
||||
#define REG_DFS_ATSR_OFFS 3
|
||||
#define REG_DFS_RECONF_OFFS 4
|
||||
#define REG_DFS_CL_NEXT_STATE_OFFS 8
|
||||
#define REG_DFS_CL_NEXT_STATE_MASK 0xF
|
||||
#define REG_DFS_CWL_NEXT_STATE_OFFS 12
|
||||
#define REG_DFS_CWL_NEXT_STATE_MASK 0x7
|
||||
|
||||
#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
|
||||
#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1F
|
||||
#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
|
||||
|
||||
#define REG_READ_DATA_READY_DELAYS_ADDR 0x153C
|
||||
#define REG_READ_DATA_READY_DELAYS_MASK 0x1F
|
||||
#define REG_READ_DATA_READY_DELAYS_OFFS 8
|
||||
|
||||
#define START_BURST_IN_ADDR 1
|
||||
|
||||
#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488
|
||||
#define REG_DRAM_TRAINING_ADDR 0x15B0
|
||||
#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0
|
||||
#define REG_DRAM_TRAINING_PATTERNS_OFFS 4
|
||||
#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2
|
||||
#define REG_DRAM_TRAINING_WL_OFFS 3
|
||||
#define REG_DRAM_TRAINING_RL_OFFS 6
|
||||
#define REG_DRAM_TRAINING_DQS_RX_OFFS 15
|
||||
#define REG_DRAM_TRAINING_DQS_TX_OFFS 16
|
||||
#define REG_DRAM_TRAINING_CS_OFFS 20
|
||||
#define REG_DRAM_TRAINING_RETEST_OFFS 24
|
||||
#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27
|
||||
#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29
|
||||
#define REG_DRAM_TRAINING_ERROR_OFFS 30
|
||||
#define REG_DRAM_TRAINING_AUTO_OFFS 31
|
||||
#define REG_DRAM_TRAINING_RETEST_PAR 0x3
|
||||
#define REG_DRAM_TRAINING_RETEST_MASK 0xF8FFFFFF
|
||||
#define REG_DRAM_TRAINING_CS_MASK 0xFF0FFFFF
|
||||
#define REG_DRAM_TRAINING_PATTERNS_MASK 0xFF0F0000
|
||||
|
||||
#define REG_DRAM_TRAINING_1_ADDR 0x15B4
|
||||
#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16
|
||||
|
||||
#define REG_DRAM_TRAINING_2_ADDR 0x15B8
|
||||
#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17
|
||||
#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4
|
||||
#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3
|
||||
#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2
|
||||
#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1
|
||||
#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0
|
||||
|
||||
#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15BC
|
||||
#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3
|
||||
|
||||
#define REG_TRAINING_DEBUG_2_ADDR 0x15C4
|
||||
#define REG_TRAINING_DEBUG_2_OFFS 16
|
||||
#define REG_TRAINING_DEBUG_2_MASK 0x3
|
||||
|
||||
#define REG_TRAINING_DEBUG_3_ADDR 0x15C8
|
||||
#define REG_TRAINING_DEBUG_3_OFFS 3
|
||||
#define REG_TRAINING_DEBUG_3_MASK 0x7
|
||||
|
||||
#define MR_CS_ADDR_OFFS 4
|
||||
|
||||
#define REG_DDR3_MR0_ADDR 0x15D0
|
||||
#define REG_DDR3_MR0_CS_ADDR 0x1870
|
||||
#define REG_DDR3_MR0_CL_MASK 0x74
|
||||
#define REG_DDR3_MR0_CL_OFFS 2
|
||||
#define REG_DDR3_MR0_CL_HIGH_OFFS 3
|
||||
#define CL_MASK 0xF
|
||||
|
||||
#define REG_DDR3_MR1_ADDR 0x15D4
|
||||
#define REG_DDR3_MR1_CS_ADDR 0x1874
|
||||
#define REG_DDR3_MR1_RTT_MASK 0xFFFFFDBB
|
||||
#define REG_DDR3_MR1_DLL_ENA_OFFS 0
|
||||
#define REG_DDR3_MR1_RTT_DISABLED 0x0
|
||||
#define REG_DDR3_MR1_RTT_RZQ2 0x40
|
||||
#define REG_DDR3_MR1_RTT_RZQ4 0x2
|
||||
#define REG_DDR3_MR1_RTT_RZQ6 0x42
|
||||
#define REG_DDR3_MR1_RTT_RZQ8 0x202
|
||||
#define REG_DDR3_MR1_RTT_RZQ12 0x4
|
||||
#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xFFFFEF7F /* WL-disabled,OB-enabled */
|
||||
#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12 /* Output Buffer Disabled */
|
||||
#define REG_DDR3_MR1_WL_ENA_OFFS 7
|
||||
#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */
|
||||
#define REG_DDR3_MR1_ODT_MASK 0xFFFFFDBB
|
||||
|
||||
#define REG_DDR3_MR2_ADDR 0x15D8
|
||||
#define REG_DDR3_MR2_CS_ADDR 0x1878
|
||||
#define REG_DDR3_MR2_CWL_OFFS 3
|
||||
#define REG_DDR3_MR2_CWL_MASK 0x7
|
||||
#define REG_DDR3_MR2_ODT_MASK 0xFFFFF9FF
|
||||
#define REG_DDR3_MR3_ADDR 0x15DC
|
||||
#define REG_DDR3_MR3_CS_ADDR 0x187C
|
||||
|
||||
#define REG_DDR3_RANK_CTRL_ADDR 0x15E0
|
||||
#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xF
|
||||
#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4
|
||||
|
||||
#define REG_ZQC_CONF_ADDR 0x15E4
|
||||
|
||||
#define REG_DRAM_PHY_CONFIG_ADDR 0x15EC
|
||||
#define REG_DRAM_PHY_CONFIG_MASK 0x3FFFFFFF
|
||||
|
||||
#define REG_ODPG_CNTRL_ADDR 0x1600
|
||||
#define REG_ODPG_CNTRL_OFFS 21
|
||||
|
||||
#define REG_PHY_LOCK_MASK_ADDR 0x1670
|
||||
#define REG_PHY_LOCK_MASK_MASK 0xFFFFF000
|
||||
|
||||
#define REG_PHY_LOCK_STATUS_ADDR 0x1674
|
||||
#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9
|
||||
#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xFFF
|
||||
#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7FF
|
||||
|
||||
#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0
|
||||
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xC0000000
|
||||
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000
|
||||
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000
|
||||
#define REG_PHY_BC_OFFS 27
|
||||
#define REG_PHY_CNTRL_OFFS 26
|
||||
#define REG_PHY_CS_OFFS 16
|
||||
#define REG_PHY_DQS_REF_DLY_OFFS 10
|
||||
#define REG_PHY_PHASE_OFFS 8
|
||||
#define REG_PHY_PUP_OFFS 22
|
||||
|
||||
#define REG_TRAINING_WL_ADDR 0x16AC
|
||||
#define REG_TRAINING_WL_CS_MASK 0xFFFFFFFC
|
||||
#define REG_TRAINING_WL_UPD_OFFS 2
|
||||
#define REG_TRAINING_WL_CS_DONE_OFFS 3
|
||||
#define REG_TRAINING_WL_RATIO_MASK 0xFFFFFF0F
|
||||
#define REG_TRAINING_WL_1TO1 0x50
|
||||
#define REG_TRAINING_WL_2TO1 0x10
|
||||
#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000
|
||||
#define REG_TRAINING_WL_RESULTS_MASK 0x000001FF
|
||||
#define REG_TRAINING_WL_RESULTS_OFFS 20
|
||||
|
||||
#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16D0
|
||||
#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15
|
||||
#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3F
|
||||
/* DLB*/
|
||||
#define REG_STATIC_DRAM_DLB_CONTROL 0x1700
|
||||
#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704
|
||||
#define DLB_AGING_REGISTER 0x1708
|
||||
#define DLB_EVICTION_CONTROL_REG 0x170c
|
||||
#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710
|
||||
|
||||
#define DLB_ENABLE 0x1
|
||||
#define DLB_WRITE_COALESING (0x1 << 2)
|
||||
#define DLB_AXI_PREFETCH_EN (0x1 << 3)
|
||||
#define DLB_MBUS_PREFETCH_EN (0x1 << 4)
|
||||
#define PREFETCH_NLNSZTR (0x1 << 6)
|
||||
|
||||
/* CPU */
|
||||
#define REG_BOOTROM_ROUTINE_ADDR 0x182D0
|
||||
#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
|
||||
|
||||
#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488
|
||||
#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16
|
||||
#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200FF
|
||||
#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488
|
||||
|
||||
#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700
|
||||
|
||||
#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704
|
||||
#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708
|
||||
|
||||
#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870C
|
||||
#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xFFFFC0FF
|
||||
#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8
|
||||
|
||||
#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710
|
||||
|
||||
#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718
|
||||
#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8
|
||||
|
||||
#define REG_CPU_PLL_CTRL_0_ADDR 0x1871C
|
||||
#define REG_CPU_PLL_STATUS_0_ADDR 0x18724
|
||||
#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740
|
||||
#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744
|
||||
#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780
|
||||
|
||||
#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784
|
||||
|
||||
#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858
|
||||
#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8
|
||||
|
||||
/* DRAM Windows */
|
||||
#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
|
||||
#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
|
||||
#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
|
||||
#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
|
||||
#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184
|
||||
#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
|
||||
|
||||
/* SRAM */
|
||||
#define REG_CDI_CONFIG_ADDR 0x20220
|
||||
#define REG_SRAM_WINDOW_0_ADDR 0x20240
|
||||
#define REG_SRAM_WINDOW_0_ENA_OFFS 0
|
||||
#define REG_SRAM_WINDOW_1_ADDR 0x20244
|
||||
#define REG_SRAM_L2_ENA_ADDR 0x8500
|
||||
#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87BC
|
||||
|
||||
/* PMU */
|
||||
#define REG_PMU_I_F_CTRL_ADDR 0x1C090
|
||||
#define REG_PMU_DUNIT_BLK_OFFS 16
|
||||
#define REG_PMU_DUNIT_RFRS_OFFS 20
|
||||
#define REG_PMU_DUNIT_ACK_OFFS 24
|
||||
|
||||
/* MBUS*/
|
||||
#define MBUS_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x420)
|
||||
#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x424)
|
||||
#define MBUS_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x428)
|
||||
#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x42c)
|
||||
|
||||
#define REG_PM_STAT_MASK_ADDR 0x2210C
|
||||
#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16
|
||||
|
||||
#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120
|
||||
#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17
|
||||
|
||||
#define REG_PM_CTRL_CONFIG_ADDR 0x22104
|
||||
#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18
|
||||
|
||||
#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218C4
|
||||
#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18
|
||||
|
||||
/* Controller revision info */
|
||||
#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
|
||||
#define PCCRIR_REVID_OFFS 0 /* Revision ID */
|
||||
#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
|
||||
|
||||
/* Power Management Clock Gating Control Register */
|
||||
#define MV_PEX_IF_REGS_OFFSET(if) \
|
||||
(if < 8 ? (0x40000 + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) \
|
||||
: (0x42000 + ((if) % 8) * 0x40000))
|
||||
#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit))
|
||||
#define POWER_MNG_CTRL_REG 0x18220
|
||||
#define PEX_DEVICE_AND_VENDOR_ID 0x000
|
||||
#define PEX_CFG_DIRECT_ACCESS(if, reg) (MV_PEX_IF_REGS_BASE(if) + (reg))
|
||||
#define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port)))
|
||||
#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port))
|
||||
#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port))
|
||||
#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port))
|
||||
|
||||
/* TWSI */
|
||||
#define TWSI_DATA_ADDR_MASK 0x7
|
||||
#define TWSI_DATA_ADDR_OFFS 1
|
||||
|
||||
/* General */
|
||||
#define MAX_CS 4
|
||||
|
||||
/* Frequencies */
|
||||
#define FAB_OPT 21
|
||||
#define CLK_CPU 12
|
||||
#define CLK_VCO (2 * CLK_CPU)
|
||||
#define CLK_DDR 12
|
||||
|
||||
/* Cpu Frequencies: */
|
||||
#define CLK_CPU_1000 0
|
||||
#define CLK_CPU_1066 1
|
||||
#define CLK_CPU_1200 2
|
||||
#define CLK_CPU_1333 3
|
||||
#define CLK_CPU_1500 4
|
||||
#define CLK_CPU_1666 5
|
||||
#define CLK_CPU_1800 6
|
||||
#define CLK_CPU_2000 7
|
||||
#define CLK_CPU_600 8
|
||||
#define CLK_CPU_667 9
|
||||
#define CLK_CPU_800 0xa
|
||||
|
||||
/* Extra Cpu Frequencies: */
|
||||
#define CLK_CPU_1600 11
|
||||
#define CLK_CPU_2133 12
|
||||
#define CLK_CPU_2200 13
|
||||
#define CLK_CPU_2400 14
|
||||
|
||||
/* DDR3 Frequencies: */
|
||||
#define DDR_100 0
|
||||
#define DDR_300 1
|
||||
#define DDR_333 1
|
||||
#define DDR_360 2
|
||||
#define DDR_400 3
|
||||
#define DDR_444 4
|
||||
#define DDR_500 5
|
||||
#define DDR_533 6
|
||||
#define DDR_600 7
|
||||
#define DDR_640 8
|
||||
#define DDR_666 8
|
||||
#define DDR_720 9
|
||||
#define DDR_750 9
|
||||
#define DDR_800 10
|
||||
#define DDR_833 11
|
||||
#define DDR_HCLK 20
|
||||
#define DDR_S 12
|
||||
#define DDR_S_1TO1 13
|
||||
#define MARGIN_FREQ DDR_400
|
||||
#define DFS_MARGIN DDR_100
|
||||
|
||||
#define ODT_OPT 16
|
||||
#define ODT20 0x200
|
||||
#define ODT30 0x204
|
||||
#define ODT40 0x44
|
||||
#define ODT120 0x40
|
||||
#define ODT120D 0x400
|
||||
|
||||
#define MRS_DELAY 100
|
||||
|
||||
#define SDRAM_WL_SW_OFFS 0x100
|
||||
#define SDRAM_RL_OFFS 0x0
|
||||
#define SDRAM_PBS_I_OFFS 0x140
|
||||
#define SDRAM_PBS_II_OFFS 0x180
|
||||
#define SDRAM_PBS_NEXT_OFFS (SDRAM_PBS_II_OFFS - SDRAM_PBS_I_OFFS)
|
||||
#define SDRAM_PBS_TX_OFFS 0x180
|
||||
#define SDRAM_PBS_TX_DM_OFFS 576
|
||||
#define SDRAM_DQS_RX_OFFS 1024
|
||||
#define SDRAM_DQS_TX_OFFS 2048
|
||||
#define SDRAM_DQS_RX_SPECIAL_OFFS 5120
|
||||
|
||||
#define LEN_STD_PATTERN 16
|
||||
#define LEN_KILLER_PATTERN 128
|
||||
#define LEN_SPECIAL_PATTERN 128
|
||||
#define LEN_PBS_PATTERN 16
|
||||
|
||||
#endif /* __DDR3_AXP_H */
|
||||
146
drivers/ddr/mvebu/ddr3_axp_config.h
Normal file
146
drivers/ddr/mvebu/ddr3_axp_config.h
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __DDR3_AXP_CONFIG_H
|
||||
#define __DDR3_AXP_CONFIG_H
|
||||
|
||||
/*
|
||||
* DDR3_LOG_LEVEL Information
|
||||
*
|
||||
* Level 0: Provides an error code in a case of failure, RL, WL errors
|
||||
* and other algorithm failure
|
||||
* Level 1: Provides the D-Unit setup (SPD/Static configuration)
|
||||
* Level 2: Provides the windows margin as a results of DQS centeralization
|
||||
* Level 3: Provides the windows margin of each DQ as a results of DQS
|
||||
* centeralization
|
||||
*/
|
||||
#ifdef CONFIG_DDR_LOG_LEVEL
|
||||
#define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL
|
||||
#else
|
||||
#define DDR3_LOG_LEVEL 0
|
||||
#endif
|
||||
|
||||
#define DDR3_PBS 1
|
||||
|
||||
/* This flag allows the execution of SW WL/RL upon HW failure */
|
||||
#define DDR3_RUN_SW_WHEN_HW_FAIL 1
|
||||
|
||||
/*
|
||||
* General Configurations
|
||||
*
|
||||
* The following parameters are required for proper setup:
|
||||
*
|
||||
* DDR_TARGET_FABRIC - Set desired fabric configuration
|
||||
* (for sample@Reset fabfreq parameter)
|
||||
* DRAM_ECC - Set ECC support 1/0
|
||||
* BUS_WIDTH - 64/32 bit
|
||||
* CONFIG_SPD_EEPROM - Enables auto detection of DIMMs and their timing values
|
||||
* DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board
|
||||
* MIXED_DIMM_STATIC - Mixed DIMM + On board devices support (ODT registers
|
||||
* values are taken statically)
|
||||
* DDR3_TRAINING_DEBUG - Debug prints of internal code
|
||||
*/
|
||||
#define DDR_TARGET_FABRIC 5
|
||||
#define DRAM_ECC 0
|
||||
|
||||
#ifdef MV_DDR_32BIT
|
||||
#define BUS_WIDTH 32
|
||||
#else
|
||||
#define BUS_WIDTH 64
|
||||
#endif
|
||||
|
||||
#undef DQS_CLK_ALIGNED
|
||||
#undef MIXED_DIMM_STATIC
|
||||
#define DDR3_TRAINING_DEBUG 0
|
||||
#define REG_DIMM_SKIP_WL 0
|
||||
|
||||
/* Marvell boards specific configurations */
|
||||
#if defined(DB_78X60_PCAC)
|
||||
#undef CONFIG_SPD_EEPROM
|
||||
#define STATIC_TRAINING
|
||||
#endif
|
||||
|
||||
#if defined(DB_78X60_AMC)
|
||||
#undef CONFIG_SPD_EEPROM
|
||||
#undef DRAM_ECC
|
||||
#define DRAM_ECC 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPD_EEPROM
|
||||
/*
|
||||
* DIMM support parameters:
|
||||
* DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
|
||||
* DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
|
||||
* (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
|
||||
*/
|
||||
#define DRAM_2T 0x0
|
||||
#define DIMM_CS_BITMAP 0xF
|
||||
#define DUNIT_SPD
|
||||
#endif
|
||||
|
||||
#ifdef DRAM_ECC
|
||||
/*
|
||||
* ECC support parameters:
|
||||
*
|
||||
* U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
|
||||
* to configure the scrubbing area
|
||||
*/
|
||||
#define TRAINING_SIZE 0x20000
|
||||
#define U_BOOT_START_ADDR 0
|
||||
#define U_BOOT_SCRUB_SIZE 0x1000000 /* TRAINING_SIZE */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Registered DIMM Support - In case registered DIMM is attached,
|
||||
* please supply the following values:
|
||||
* (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
|
||||
* Driver with Parity and Quad Chip
|
||||
* Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications")
|
||||
* RC0: Global Features Control Word
|
||||
* RC1: Clock Driver Enable Control Word
|
||||
* RC2: Timing Control Word
|
||||
* RC3-RC5 - taken from SPD
|
||||
* RC8: Additional IBT Setting Control Word
|
||||
* RC9: Power Saving Settings Control Word
|
||||
* RC10: Encoding for RDIMM Operating Speed
|
||||
* RC11: Operating Voltage VDD and VREFCA Control Word
|
||||
*/
|
||||
#define RDIMM_RC0 0
|
||||
#define RDIMM_RC1 0
|
||||
#define RDIMM_RC2 0
|
||||
#define RDIMM_RC8 0
|
||||
#define RDIMM_RC9 0
|
||||
#define RDIMM_RC10 0x2
|
||||
#define RDIMM_RC11 0x0
|
||||
|
||||
#if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM)
|
||||
#define DUNIT_STATIC
|
||||
#endif
|
||||
|
||||
#if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* This flag allows the user to change the dram refresh cycle in ps,
|
||||
* only in case of SPD or MIX DIMM topology
|
||||
*/
|
||||
#define TREFI_USER_EN
|
||||
|
||||
#ifdef TREFI_USER_EN
|
||||
#define TREFI_USER 3900000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPD_EEPROM
|
||||
/*
|
||||
* AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
|
||||
* Enables I2C auto detection different options
|
||||
*/
|
||||
#if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \
|
||||
defined(CONFIG_DB_784MP_GP)
|
||||
#define AUTO_DETECTION_SUPPORT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __DDR3_AXP_CONFIG_H */
|
||||
284
drivers/ddr/mvebu/ddr3_axp_mc_static.h
Normal file
284
drivers/ddr/mvebu/ddr3_axp_mc_static.h
Normal file
|
|
@ -0,0 +1,284 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __AXP_MC_STATIC_H
|
||||
#define __AXP_MC_STATIC_H
|
||||
|
||||
MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
#ifdef MV_DDR_32BIT
|
||||
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
|
||||
#else /*MV_DDR_64BIT */
|
||||
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
|
||||
#endif
|
||||
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
|
||||
{0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
|
||||
/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
|
||||
{0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
|
||||
|
||||
#ifdef DB_78X60_PCAC
|
||||
{0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
|
||||
#else
|
||||
{0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
|
||||
#endif
|
||||
|
||||
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
|
||||
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
|
||||
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
|
||||
{0x00001424, 0x0000D3FF}, /*Dunit Control High Register */
|
||||
{0x00001428, 0x000F8830}, /*Dunit Control High Register */
|
||||
{0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
|
||||
{0x0000147C, 0x0000c671},
|
||||
|
||||
{0x000014a0, 0x000002A9},
|
||||
{0x000014a8, 0x00000101}, /*2:1 */
|
||||
{0x00020220, 0x00000007},
|
||||
|
||||
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
|
||||
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
|
||||
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
|
||||
|
||||
{0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */
|
||||
{0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
|
||||
|
||||
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
|
||||
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
|
||||
|
||||
{0x0001504, 0x7FFFFFF1}, /* CS0 Size */
|
||||
{0x000150C, 0x00000000}, /* CS1 Size */
|
||||
{0x0001514, 0x00000000}, /* CS2 Size */
|
||||
{0x000151C, 0x00000000}, /* CS3 Size */
|
||||
|
||||
/* {0x00001524, 0x0000C800}, */
|
||||
{0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
|
||||
|
||||
{0x000015D0, 0x00000640}, /*MR0 */
|
||||
{0x000015D4, 0x00000046}, /*MR1 */
|
||||
{0x000015D8, 0x00000010}, /*MR2 */
|
||||
{0x000015DC, 0x00000000}, /*MR3 */
|
||||
|
||||
{0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
|
||||
{0x000015EC, 0xd800aa25}, /*DDR PHY */
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
#ifdef MV_DDR_32BIT
|
||||
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
|
||||
#else /*MV_DDR_64BIT */
|
||||
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
|
||||
#endif
|
||||
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
|
||||
{0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
|
||||
/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
|
||||
{0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
|
||||
|
||||
#ifdef DB_78X60_PCAC
|
||||
{0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
|
||||
#else
|
||||
{0x00001410, 0x040F000C}, /*DDR SDRAM Open Pages Control Register */
|
||||
#endif
|
||||
|
||||
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
|
||||
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
|
||||
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
|
||||
{0x00001424, 0x0000D3FF}, /*Dunit Control High Register */
|
||||
{0x00001428, 0x000F8830}, /*Dunit Control High Register */
|
||||
{0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
|
||||
{0x0000147C, 0x0000c671},
|
||||
|
||||
{0x000014a0, 0x000002A9},
|
||||
{0x000014a8, 0x00000101}, /*2:1 */
|
||||
{0x00020220, 0x00000007},
|
||||
|
||||
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
|
||||
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
|
||||
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
|
||||
|
||||
{0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */
|
||||
{0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
|
||||
|
||||
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
|
||||
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
|
||||
|
||||
{0x0001504, 0x3FFFFFF1}, /* CS0 Size */
|
||||
{0x000150C, 0x00000000}, /* CS1 Size */
|
||||
{0x0001514, 0x00000000}, /* CS2 Size */
|
||||
{0x000151C, 0x00000000}, /* CS3 Size */
|
||||
|
||||
/* {0x00001524, 0x0000C800}, */
|
||||
{0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
|
||||
|
||||
{0x000015D0, 0x00000640}, /*MR0 */
|
||||
{0x000015D4, 0x00000046}, /*MR1 */
|
||||
{0x000015D8, 0x00000010}, /*MR2 */
|
||||
{0x000015DC, 0x00000000}, /*MR3 */
|
||||
|
||||
{0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
|
||||
{0x000015EC, 0xd800aa25}, /*DDR PHY */
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
#ifdef MV_DDR_32BIT
|
||||
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
|
||||
#else /* MV_DDR_64BIT */
|
||||
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
|
||||
#endif
|
||||
{0x00001404, 0x3630B840}, /*Dunit Control Low Register */
|
||||
{0x00001408, 0x33137663}, /*DDR SDRAM Timing (Low) Register */
|
||||
{0x0000140C, 0x38000C55}, /*DDR SDRAM Timing (High) Register */
|
||||
{0x00001410, 0x040F0000}, /*DDR SDRAM Address Control Register */
|
||||
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
|
||||
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
|
||||
{0x0000141C, 0x00000672}, /*DDR SDRAM Mode Register */
|
||||
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
|
||||
{0x00001424, 0x0100D3FF}, /*Dunit Control High Register */
|
||||
{0x00001428, 0x000D6720}, /*Dunit Control High Register */
|
||||
{0x0000142C, 0x014C2F38}, /*Dunit Control High Register */
|
||||
{0x0000147C, 0x00006571},
|
||||
|
||||
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
|
||||
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
|
||||
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
|
||||
|
||||
{0x000014a0, 0x000002A9},
|
||||
{0x000014a8, 0x00000101}, /*2:1 */
|
||||
{0x00020220, 0x00000007},
|
||||
|
||||
{0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
|
||||
{0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
|
||||
|
||||
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
|
||||
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
|
||||
|
||||
{0x0001504, 0x7FFFFFF1}, /* CS0 Size */
|
||||
{0x000150C, 0x00000000}, /* CS1 Size */
|
||||
{0x0001514, 0x00000000}, /* CS2 Size */
|
||||
{0x000151C, 0x00000000}, /* CS3 Size */
|
||||
|
||||
{0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
|
||||
|
||||
{0x000015D0, 0x00000630}, /*MR0 */
|
||||
{0x000015D4, 0x00000046}, /*MR1 */
|
||||
{0x000015D8, 0x00000008}, /*MR2 */
|
||||
{0x000015DC, 0x00000000}, /*MR3 */
|
||||
|
||||
{0x000015E4, 0x00203c18}, /*ZQDS Configuration Register */
|
||||
/* {0x000015EC, 0xDE000025}, *//*DDR PHY */
|
||||
{0x000015EC, 0xF800AA25}, /*DDR PHY */
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
#ifdef MV_DDR_32BIT
|
||||
{0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
|
||||
#else /*MV_DDR_64BIT */
|
||||
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
|
||||
#endif
|
||||
{0x00001404, 0x3630B040}, /*Dunit Control Low Register */
|
||||
{0x00001408, 0x44149887}, /*DDR SDRAM Timing (Low) Register */
|
||||
/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
|
||||
{0x0000140C, 0x38D83FE0}, /*DDR SDRAM Timing (High) Register */
|
||||
|
||||
#ifdef DB_78X60_PCAC
|
||||
{0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
|
||||
#else
|
||||
{0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
|
||||
#endif
|
||||
|
||||
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
|
||||
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
|
||||
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
|
||||
{0x00001424, 0x0100D1FF}, /*Dunit Control High Register */
|
||||
{0x00001428, 0x000F8830}, /*Dunit Control High Register */
|
||||
{0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
|
||||
{0x0000147C, 0x0000c671},
|
||||
|
||||
{0x000014a8, 0x00000101}, /*2:1 */
|
||||
{0x00020220, 0x00000007},
|
||||
|
||||
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
|
||||
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
|
||||
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
|
||||
|
||||
{0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
|
||||
{0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
|
||||
|
||||
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
|
||||
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
|
||||
|
||||
{0x0001504, 0x7FFFFFF1}, /* CS0 Size */
|
||||
{0x000150C, 0x00000000}, /* CS1 Size */
|
||||
{0x0001514, 0x00000000}, /* CS2 Size */
|
||||
{0x000151C, 0x00000000}, /* CS3 Size */
|
||||
|
||||
/* {0x00001524, 0x0000C800}, */
|
||||
{0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
|
||||
|
||||
{0x000015D0, 0x00000650}, /*MR0 */
|
||||
{0x000015D4, 0x00000046}, /*MR1 */
|
||||
{0x000015D8, 0x00000010}, /*MR2 */
|
||||
{0x000015DC, 0x00000000}, /*MR3 */
|
||||
|
||||
{0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
|
||||
{0x000015EC, 0xDE000025}, /*DDR PHY */
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
#ifdef MV_DDR_32BIT
|
||||
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
|
||||
#else /*MV_DDR_64BIT */
|
||||
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
|
||||
/*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */
|
||||
#endif
|
||||
{0x00001404, 0x3630B840}, /*Dunit Control Low Register */
|
||||
{0x00001408, 0x33137663}, /*DDR SDRAM Timing (Low) Register */
|
||||
{0x0000140C, 0x38000C55}, /*DDR SDRAM Timing (High) Register */
|
||||
{0x00001410, 0x040F0000}, /*DDR SDRAM Address Control Register */
|
||||
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
|
||||
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
|
||||
{0x0000141C, 0x00000672}, /*DDR SDRAM Mode Register */
|
||||
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
|
||||
{0x00001424, 0x0100F1FF}, /*Dunit Control High Register */
|
||||
{0x00001428, 0x000D6720}, /*Dunit Control High Register */
|
||||
{0x0000142C, 0x014C2F38}, /*Dunit Control High Register */
|
||||
{0x0000147C, 0x00006571},
|
||||
|
||||
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
|
||||
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
|
||||
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
|
||||
|
||||
{0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
|
||||
{0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
|
||||
|
||||
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
|
||||
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
|
||||
|
||||
{0x0001504, 0x7FFFFFF1}, /* CS0 Size */
|
||||
{0x000150C, 0x00000000}, /* CS1 Size */
|
||||
{0x0001514, 0x00000000}, /* CS2 Size */
|
||||
{0x000151C, 0x00000000}, /* CS3 Size */
|
||||
|
||||
{0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
|
||||
|
||||
{0x000015D0, 0x00000630}, /*MR0 */
|
||||
{0x000015D4, 0x00000046}, /*MR1 */
|
||||
{0x000015D8, 0x00000008}, /*MR2 */
|
||||
{0x000015DC, 0x00000000}, /*MR3 */
|
||||
|
||||
{0x000015E4, 0x00203c18}, /*ZQDS Configuration Register */
|
||||
{0x000015EC, 0xDE000025}, /*DDR PHY */
|
||||
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
#endif /* __AXP_MC_STATIC_H */
|
||||
770
drivers/ddr/mvebu/ddr3_axp_training_static.h
Normal file
770
drivers/ddr/mvebu/ddr3_axp_training_static.h
Normal file
|
|
@ -0,0 +1,770 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __AXP_TRAINING_STATIC_H
|
||||
#define __AXP_TRAINING_STATIC_H
|
||||
|
||||
/*
|
||||
* STATIC_TRAINING - Set only if static parameters for training are set and
|
||||
* required
|
||||
*/
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_db_rev2_667[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC002011A},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0420100},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC082020A},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C20017},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1020113},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1420107},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC182011F},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C2001C},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC202010D},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0004A06},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC040690D},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0806A0D},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C0A01B},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1003A01},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1408113},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1805609},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C04504},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2009518},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_db_rev2_800[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0020301},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0420202},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0820314},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C20117},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1020219},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC142020B},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC182030A},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C2011D},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2020212},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0007A12},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0408D16},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0809E1B},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C0AC1F},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1005E0A},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC140A91D},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1808E17},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C05509},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2003A01},
|
||||
|
||||
/* PBS Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0007A12},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0408D16},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0809E1B},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C0AC1F},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1005E0A},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC140A91D},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1808E17},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C05509},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2003A01},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000B},
|
||||
|
||||
{0x00001538, 0x0000000D}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 2 4 15 */
|
||||
{0x000016A0, 0xC002010C},
|
||||
/*1 2 4 2 */
|
||||
{0x000016A0, 0xC042001C},
|
||||
/*2 2 4 27 */
|
||||
{0x000016A0, 0xC0820115},
|
||||
/*3 2 4 0 */
|
||||
{0x000016A0, 0xC0C20019},
|
||||
/*4 2 4 13 */
|
||||
{0x000016A0, 0xC1020108},
|
||||
/*5 2 4 5 */
|
||||
{0x000016A0, 0xC1420100},
|
||||
/*6 2 4 19 */
|
||||
{0x000016A0, 0xC1820111},
|
||||
/*7 2 4 0 */
|
||||
{0x000016A0, 0xC1C2001B},
|
||||
/*8 2 4 10 */
|
||||
/*{0x000016A0, 0xC2020117}, */
|
||||
{0x000016A0, 0xC202010C},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0005508},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0409819},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC080650C},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C0700F},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1004103},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC140A81D},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC180650C},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C08013},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2005508},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_db_533[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 2 4 15 */
|
||||
{0x000016A0, 0xC002040C},
|
||||
/*1 2 4 2 */
|
||||
{0x000016A0, 0xC0420117},
|
||||
/*2 2 4 27 */
|
||||
{0x000016A0, 0xC082041B},
|
||||
/*3 2 4 0 */
|
||||
{0x000016A0, 0xC0C20117},
|
||||
/*4 2 4 13 */
|
||||
{0x000016A0, 0xC102040A},
|
||||
/*5 2 4 5 */
|
||||
{0x000016A0, 0xC1420117},
|
||||
/*6 2 4 19 */
|
||||
{0x000016A0, 0xC1820419},
|
||||
/*7 2 4 0 */
|
||||
{0x000016A0, 0xC1C20117},
|
||||
/*8 2 4 10 */
|
||||
{0x000016A0, 0xC2020117},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0008113},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0404504},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0808514},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C09418},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1006D0E},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1405508},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1807D12},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C0b01F},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2005D0A},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 2 3 1 */
|
||||
{0x000016A0, 0xC0020104},
|
||||
/*1 2 2 6 */
|
||||
{0x000016A0, 0xC0420010},
|
||||
/*2 2 3 16 */
|
||||
{0x000016A0, 0xC0820112},
|
||||
/*3 2 1 26 */
|
||||
{0x000016A0, 0xC0C20009},
|
||||
/*4 2 2 29 */
|
||||
{0x000016A0, 0xC102001F},
|
||||
/*5 2 2 13 */
|
||||
{0x000016A0, 0xC1420014},
|
||||
/*6 2 3 6 */
|
||||
{0x000016A0, 0xC1820109},
|
||||
/*7 2 1 31 */
|
||||
{0x000016A0, 0xC1C2000C},
|
||||
/*8 2 2 22 */
|
||||
{0x000016A0, 0xC2020112},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0009919},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0405508},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0809919},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C09C1A},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1008113},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC140650C},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1809518},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C04103},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2006D0E},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 2 3 1 */
|
||||
{0x000016A0, 0xC0020103},
|
||||
/*1 2 2 6 */
|
||||
{0x000016A0, 0xC0420012},
|
||||
/*2 2 3 16 */
|
||||
{0x000016A0, 0xC0820113},
|
||||
/*3 2 1 26 */
|
||||
{0x000016A0, 0xC0C20012},
|
||||
/*4 2 2 29 */
|
||||
{0x000016A0, 0xC1020100},
|
||||
/*5 2 2 13 */
|
||||
{0x000016A0, 0xC1420016},
|
||||
/*6 2 3 6 */
|
||||
{0x000016A0, 0xC1820109},
|
||||
/*7 2 1 31 */
|
||||
{0x000016A0, 0xC1C20010},
|
||||
/*8 2 2 22 */
|
||||
{0x000016A0, 0xC2020112},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC000b11F},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC040690D},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0803600},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C0a81D},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1009919},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1407911},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC180ad1e},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C04d06},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2008514},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_db_800[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 2 3 1 */
|
||||
{0x000016A0, 0xC0020213},
|
||||
/*1 2 2 6 */
|
||||
{0x000016A0, 0xC0420108},
|
||||
/*2 2 3 16 */
|
||||
{0x000016A0, 0xC0820210},
|
||||
/*3 2 1 26 */
|
||||
{0x000016A0, 0xC0C20108},
|
||||
/*4 2 2 29 */
|
||||
{0x000016A0, 0xC102011A},
|
||||
/*5 2 2 13 */
|
||||
{0x000016A0, 0xC1420300},
|
||||
/*6 2 3 6 */
|
||||
{0x000016A0, 0xC1820204},
|
||||
/*7 2 1 31 */
|
||||
{0x000016A0, 0xC1C20106},
|
||||
/*8 2 2 22 */
|
||||
{0x000016A0, 0xC2020112},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC000620B},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0408D16},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0806A0D},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C03D02},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1004a05},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC140A11B},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1805E0A},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C06D0E},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC200AD1E},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x0000000C}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000E}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_rd_667_0[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC002010E},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC042001E},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0820118},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C2001E},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC102010C},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1420102},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1820111},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C2001C},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2020109},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0003600},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC040690D},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0805207},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C0A81D},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1009919},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1407911},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1803E02},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C05107},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2008113},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_rd_667_1[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0020106},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0420016},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0820117},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C2000F},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1020105},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC142001B},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC182010C},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C20011},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2020101},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0003600},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0406D0E},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0803600},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C04504},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1009919},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1407911},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1803600},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C0610B},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2008113},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_rd_667_2[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC002010C},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC042001B},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC082011D},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C20015},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC102010B},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1420101},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1820113},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C20017},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2020107},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0003600},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0406D0E},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0803600},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C04504},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1009919},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1407911},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC180B11F},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C0610B},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2008113},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_db_667_M[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/* CS 0 */
|
||||
/*0 2 3 1 */
|
||||
{0x000016A0, 0xC0020103},
|
||||
/*1 2 2 6 */
|
||||
{0x000016A0, 0xC0420012},
|
||||
/*2 2 3 16 */
|
||||
{0x000016A0, 0xC0820113},
|
||||
/*3 2 1 26 */
|
||||
{0x000016A0, 0xC0C20012},
|
||||
/*4 2 2 29 */
|
||||
{0x000016A0, 0xC1020100},
|
||||
/*5 2 2 13 */
|
||||
{0x000016A0, 0xC1420016},
|
||||
/*6 2 3 6 */
|
||||
{0x000016A0, 0xC1820109},
|
||||
/*7 2 1 31 */
|
||||
{0x000016A0, 0xC1C20010},
|
||||
/*8 2 2 22 */
|
||||
{0x000016A0, 0xC2020112},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC000b11F},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC040690D},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0803600},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C0a81D},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1009919},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1407911},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC180ad1e},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C04d06},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2008514},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
/* CS 1 */
|
||||
|
||||
{0x000016A0, 0xC0060103},
|
||||
/*1 2 2 6 */
|
||||
{0x000016A0, 0xC0460012},
|
||||
/*2 2 3 16 */
|
||||
{0x000016A0, 0xC0860113},
|
||||
/*3 2 1 26 */
|
||||
{0x000016A0, 0xC0C60012},
|
||||
/*4 2 2 29 */
|
||||
{0x000016A0, 0xC1060100},
|
||||
/*5 2 2 13 */
|
||||
{0x000016A0, 0xC1460016},
|
||||
/*6 2 3 6 */
|
||||
{0x000016A0, 0xC1860109},
|
||||
/*7 2 1 31 */
|
||||
{0x000016A0, 0xC1C60010},
|
||||
/*8 2 2 22 */
|
||||
{0x000016A0, 0xC2060112},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC004b11F},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC044690D},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0843600},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C4a81D},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1049919},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1447911},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC184ad1e},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C44d06},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2048514},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC807000F},
|
||||
|
||||
/* Both CS */
|
||||
|
||||
{0x00001538, 0x00000B0B}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x00000F0F}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_rd_667_3[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0020118},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0420108},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0820202},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C20108},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1020117},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC142010C},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC182011B},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C20107},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2020113},
|
||||
|
||||
/* Write Leveling */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0003600},
|
||||
/*1 */
|
||||
{0x000016A0, 0xC0406D0E},
|
||||
/*2 */
|
||||
{0x000016A0, 0xC0805207},
|
||||
/*3 */
|
||||
{0x000016A0, 0xC0C0A81D},
|
||||
/*4 */
|
||||
{0x000016A0, 0xC1009919},
|
||||
/*5 */
|
||||
{0x000016A0, 0xC1407911},
|
||||
/*6 */
|
||||
{0x000016A0, 0xC1803E02},
|
||||
/*7 */
|
||||
{0x000016A0, 0xC1C04D06},
|
||||
/*8 */
|
||||
{0x000016A0, 0xC2008113},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
|
||||
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
|
||||
|
||||
/*init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
MV_DRAM_TRAINING_INIT ddr3_pcac_600[MV_MAX_DDR3_STATIC_SIZE] = {
|
||||
/* Read Leveling */
|
||||
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
|
||||
/*0 */
|
||||
{0x000016A0, 0xC0020404},
|
||||
/* 1 2 2 6 */
|
||||
{0x000016A0, 0xC042031E},
|
||||
/* 2 2 3 16 */
|
||||
{0x000016A0, 0xC0820411},
|
||||
/* 3 2 1 26 */
|
||||
{0x000016A0, 0xC0C20400},
|
||||
/* 4 2 2 29 */
|
||||
{0x000016A0, 0xC1020404},
|
||||
/* 5 2 2 13 */
|
||||
{0x000016A0, 0xC142031D},
|
||||
/* 6 2 3 6 */
|
||||
{0x000016A0, 0xC182040C},
|
||||
/* 7 2 1 31 */
|
||||
{0x000016A0, 0xC1C2031B},
|
||||
/* 8 2 2 22 */
|
||||
{0x000016A0, 0xC2020112},
|
||||
|
||||
/* Write Leveling */
|
||||
/* 0 */
|
||||
{0x000016A0, 0xC0004905},
|
||||
/* 1 */
|
||||
{0x000016A0, 0xC040A81D},
|
||||
/* 2 */
|
||||
{0x000016A0, 0xC0804504},
|
||||
/* 3 */
|
||||
{0x000016A0, 0xC0C08013},
|
||||
/* 4 */
|
||||
{0x000016A0, 0xC1004504},
|
||||
/* 5 */
|
||||
{0x000016A0, 0xC140A81D},
|
||||
/* 6 */
|
||||
{0x000016A0, 0xC1805909},
|
||||
/* 7 */
|
||||
{0x000016A0, 0xC1C09418},
|
||||
/* 8 */
|
||||
{0x000016A0, 0xC2006D0E},
|
||||
|
||||
/*center DQS on read cycle */
|
||||
{0x000016A0, 0xC803000F},
|
||||
{0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
|
||||
{0x0000153C, 0x0000000D}, /*Read Data Ready Delay Register */
|
||||
/* init DRAM */
|
||||
{0x00001480, 0x00000001},
|
||||
{0x0, 0x0}
|
||||
};
|
||||
|
||||
#endif /* __AXP_TRAINING_STATIC_H */
|
||||
226
drivers/ddr/mvebu/ddr3_axp_vars.h
Normal file
226
drivers/ddr/mvebu/ddr3_axp_vars.h
Normal file
|
|
@ -0,0 +1,226 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __AXP_VARS_H
|
||||
#define __AXP_VARS_H
|
||||
|
||||
#include "ddr3_axp_config.h"
|
||||
#include "ddr3_axp_mc_static.h"
|
||||
#include "ddr3_axp_training_static.h"
|
||||
|
||||
MV_DRAM_MODES ddr_modes[MV_DDR3_MODES_NUMBER] = {
|
||||
/* Conf name CPUFreq FabFreq Chip ID Chip/Board MC regs Training Values */
|
||||
/* db board values: */
|
||||
{"db_800-400", 0xA, 0x5, 0x0, A0, ddr3_A0_db_400, NULL},
|
||||
{"db_1200-300", 0x2, 0xC, 0x0, A0, ddr3_A0_db_400, NULL},
|
||||
{"db_1200-600", 0x2, 0x5, 0x0, A0, NULL, NULL},
|
||||
{"db_1333-667", 0x3, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_667},
|
||||
{"db_1600-800", 0xB, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_800},
|
||||
{"amc_1333-667", 0x3, 0x5, 0x0, A0_AMC, ddr3_A0_AMC_667, NULL},
|
||||
{"db_667-667", 0x9, 0x13, 0x0, Z1, ddr3_Z1_db_600, ddr3_db_667},
|
||||
{"db_800-400", 0xA, 0x1, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_400},
|
||||
{"db_1066-533", 0x1, 0x1, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_533},
|
||||
{"db_1200-300", 0x2, 0xC, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_667},
|
||||
{"db_1200-600", 0x2, 0x5, 0x0, Z1, ddr3_Z1_db_600, NULL},
|
||||
{"db_1333-333", 0x3, 0xC, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_400},
|
||||
{"db_1333-667", 0x3, 0x5, 0x0, Z1, ddr3_Z1_db_600, ddr3_db_667},
|
||||
/* pcac board values (Z1 device): */
|
||||
{"pcac_1200-600", 0x2, 0x5, 0x0, Z1_PCAC, ddr3_Z1_db_600,
|
||||
ddr3_pcac_600},
|
||||
/* rd board values (Z1 device): */
|
||||
{"rd_667_0", 0x3, 0x5, 0x0, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_0},
|
||||
{"rd_667_1", 0x3, 0x5, 0x1, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_1},
|
||||
{"rd_667_2", 0x3, 0x5, 0x2, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_2},
|
||||
{"rd_667_3", 0x3, 0x5, 0x3, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_3}
|
||||
};
|
||||
|
||||
/* ODT settings - if needed update the following tables: (ODT_OPT - represents the CS configuration bitmap) */
|
||||
|
||||
u16 odt_static[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
|
||||
{0, 0, 0, 0}, /* 0000 0/0 - Not supported */
|
||||
{ODT40, 0, 0, 0}, /* 0001 0/1 */
|
||||
{0, 0, 0, 0}, /* 0010 0/0 - Not supported */
|
||||
{ODT40, ODT40, 0, 0}, /* 0011 0/2 */
|
||||
{0, 0, ODT40, 0}, /* 0100 1/0 */
|
||||
{ODT30, 0, ODT30, 0}, /* 0101 1/1 */
|
||||
{0, 0, 0, 0}, /* 0110 0/0 - Not supported */
|
||||
{ODT120, ODT20, ODT20, 0}, /* 0111 1/2 */
|
||||
{0, 0, 0, 0}, /* 1000 0/0 - Not supported */
|
||||
{0, 0, 0, 0}, /* 1001 0/0 - Not supported */
|
||||
{0, 0, 0, 0}, /* 1010 0/0 - Not supported */
|
||||
{0, 0, 0, 0}, /* 1011 0/0 - Not supported */
|
||||
{0, 0, ODT40, 0}, /* 1100 2/0 */
|
||||
{ODT20, 0, ODT120, ODT20}, /* 1101 2/1 */
|
||||
{0, 0, 0, 0}, /* 1110 0/0 - Not supported */
|
||||
{ODT120, ODT30, ODT120, ODT30} /* 1111 2/2 */
|
||||
};
|
||||
|
||||
u16 odt_dynamic[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
|
||||
{0, 0, 0, 0}, /* 0000 0/0 */
|
||||
{0, 0, 0, 0}, /* 0001 0/1 */
|
||||
{0, 0, 0, 0}, /* 0010 0/0 - Not supported */
|
||||
{0, 0, 0, 0}, /* 0011 0/2 */
|
||||
{0, 0, 0, 0}, /* 0100 1/0 */
|
||||
{ODT120D, 0, ODT120D, 0}, /* 0101 1/1 */
|
||||
{0, 0, 0, 0}, /* 0110 0/0 - Not supported */
|
||||
{0, 0, ODT120D, 0}, /* 0111 1/2 */
|
||||
{0, 0, 0, 0}, /* 1000 0/0 - Not supported */
|
||||
{0, 0, 0, 0}, /* 1001 0/0 - Not supported */
|
||||
{0, 0, 0, 0}, /* 1010 0/0 - Not supported */
|
||||
{0, 0, 0, 0}, /* 1011 0/0 - Not supported */
|
||||
{0, 0, 0, 0}, /* 1100 2/0 */
|
||||
{ODT120D, 0, 0, 0}, /* 1101 2/1 */
|
||||
{0, 0, 0, 0}, /* 1110 0/0 - Not supported */
|
||||
{0, 0, 0, 0} /* 1111 2/2 */
|
||||
};
|
||||
|
||||
u32 odt_config[ODT_OPT] = {
|
||||
0, 0x00010000, 0, 0x00030000, 0x04000000, 0x05050104, 0, 0x07430340, 0,
|
||||
0, 0, 0,
|
||||
0x30000, 0x1C0D100C, 0, 0x3CC330C0
|
||||
};
|
||||
|
||||
/*
|
||||
* User can manually set SPD values (in case SPD is not available on
|
||||
* DIMM/System).
|
||||
* SPD Values can simplify calculating the DUNIT registers values
|
||||
*/
|
||||
u8 spd_data[SPD_SIZE] = {
|
||||
/* AXP DB Board DIMM SPD Values - manually set */
|
||||
0x92, 0x10, 0x0B, 0x2, 0x3, 0x19, 0x0, 0x9, 0x09, 0x52, 0x1, 0x8, 0x0C,
|
||||
0x0, 0x7E, 0x0, 0x69, 0x78,
|
||||
0x69, 0x30, 0x69, 0x11, 0x20, 0x89, 0x0, 0x5, 0x3C, 0x3C, 0x0, 0xF0,
|
||||
0x82, 0x5, 0x80, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0F, 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x80, 0x2C, 0x1, 0x10, 0x23, 0x35, 0x28, 0xEB, 0xCA, 0x19, 0x8F
|
||||
};
|
||||
|
||||
/*
|
||||
* Controller Specific configurations Starts Here - DO NOT MODIFY
|
||||
*/
|
||||
|
||||
/* Frequency - values are 1/HCLK in ps */
|
||||
u32 cpu_fab_clk_to_hclk[FAB_OPT][CLK_CPU] =
|
||||
/* CPU Frequency:
|
||||
1000 1066 1200 1333 1500 1666 1800 2000 600 667 800 1600 Fabric */
|
||||
{
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 2500, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 4500, 3750, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 2500, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{4000, 3750, 3333, 3000, 2666, 2400, 0, 0, 0, 0, 5000, 2500},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{2500, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 5000, 0, 4000, 0, 0, 0, 0, 0, 0, 3750},
|
||||
{5000, 0, 0, 3750, 3333, 0, 0, 0, 0, 0, 0, 3125},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 3330, 3000, 0, 0, 0, 0, 0, 0, 0, 2500},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3750},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 2500, 0},
|
||||
{3000, 0, 2500, 0, 0, 0, 0, 0, 0, 0, 3750, 0}
|
||||
};
|
||||
|
||||
u32 cpu_ddr_ratios[FAB_OPT][CLK_CPU] =
|
||||
/* CPU Frequency:
|
||||
1000 1066 1200 1333 1500 1666 1800 2000 600 667 800 1600 Fabric */
|
||||
{
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_333, DDR_400, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_444, DDR_533, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, DDR_400, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{DDR_500, DDR_533, DDR_600, DDR_666, DDR_750, DDR_833, 0, 0, 0, 0,
|
||||
DDR_400, DDR_800},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_333, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{DDR_400, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, DDR_400, 0, DDR_500, 0, 0, 0, 0, 0, 0, DDR_533},
|
||||
{DDR_400, 0, 0, DDR_533, DDR_600, 0, 0, 0, 0, 0, 0, DDR_640},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, DDR_300, DDR_333, 0, 0, 0, 0, 0, 0, 0, DDR_400},
|
||||
{0, 0, 0, 0, 0, 0, DDR_600, DDR_666, 0, 0, 0, DDR_533},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_666, DDR_800, 0},
|
||||
{DDR_666, 0, DDR_800, 0, 0, 0, 0, 0, 0, 0, DDR_533, 0}
|
||||
};
|
||||
|
||||
u8 div_ratio1to1[CLK_VCO][CLK_DDR] =
|
||||
/* DDR Frequency:
|
||||
100 300 360 400 444 500 533 600 666 750 800 833 */
|
||||
{ {0xA, 3, 0, 3, 0, 2, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1000 */
|
||||
{0xB, 3, 0, 3, 0, 0, 2, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1066 */
|
||||
{0xC, 4, 0, 3, 0, 0, 0, 2, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1200 */
|
||||
{0xD, 4, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0}, /* 1:1 CLK_CPU_1333 */
|
||||
{0xF, 5, 0, 4, 0, 3, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1500 */
|
||||
{0x11, 5, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1666 */
|
||||
{0x12, 6, 5, 4, 0, 0, 0, 3, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1800 */
|
||||
{0x14, 7, 0, 5, 0, 4, 0, 0, 3, 0, 0, 0}, /* 1:1 CLK_CPU_2000 */
|
||||
{0x6, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_600 */
|
||||
{0x6, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_667 */
|
||||
{0x8, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_800 */
|
||||
{0x10, 5, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1600 */
|
||||
{0x14, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1000 VCO_2000 */
|
||||
{0x15, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1066 VCO_2133 */
|
||||
{0x18, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1200 VCO_2400 */
|
||||
{0x1A, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1333 VCO_2666 */
|
||||
{0x1E, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1500 VCO_3000 */
|
||||
{0x21, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1666 VCO_3333 */
|
||||
{0x24, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1800 VCO_3600 */
|
||||
{0x28, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_2000 VCO_4000 */
|
||||
{0xC, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_600 VCO_1200 */
|
||||
{0xD, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_667 VCO_1333 */
|
||||
{0x10, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_800 VCO_1600 */
|
||||
{0x20, 10, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0} /* 1:1 CLK_CPU_1600 VCO_3200 */
|
||||
};
|
||||
|
||||
u8 div_ratio2to1[CLK_VCO][CLK_DDR] =
|
||||
/* DDR Frequency:
|
||||
100 300 360 400 444 500 533 600 666 750 800 833 */
|
||||
{ {0, 0, 0, 0, 0, 2, 0, 0, 3, 0, 0, 0}, /* 2:1 CLK_CPU_1000 */
|
||||
{0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1066 */
|
||||
{0, 0, 0, 3, 5, 0, 0, 2, 0, 0, 3, 3}, /* 2:1 CLK_CPU_1200 */
|
||||
{0, 0, 0, 0, 0, 0, 5, 0, 2, 0, 3, 0}, /* 2:1 CLK_CPU_1333 */
|
||||
{0, 0, 0, 0, 0, 3, 0, 5, 0, 2, 0, 0}, /* 2:1 CLK_CPU_1500 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 2}, /* 2:1 CLK_CPU_1666 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 3, 0, 5, 0, 0}, /* 2:1 CLK_CPU_1800 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 5}, /* 2:1 CLK_CPU_2000 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_600 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, /* 2:1 CLK_CPU_667 */
|
||||
{0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 1, 0}, /* 2:1 CLK_CPU_800 */
|
||||
{0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 2, 0}, /* 2:1 CLK_CPU_1600 */
|
||||
{0, 0, 0, 5, 0, 0, 0, 0, 3, 0, 0, 0}, /* 2:1 CLK_CPU_1000 VCO_2000 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1066 VCO_2133 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0}, /* 2:1 CLK_CPU_1200 VCO_2400 */
|
||||
{0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1333 VCO_2666 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1500 VCO_3000 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1666 VCO_3333 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1800 VCO_3600 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_2000 VCO_4000 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_600 VCO_1200 */
|
||||
{0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_667 VCO_1333 */
|
||||
{0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_800 VCO_1600 */
|
||||
{0, 0, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0} /* 2:1 CLK_CPU_1600 VCO_3200 */
|
||||
};
|
||||
|
||||
#endif /* __AXP_VARS_H */
|
||||
1552
drivers/ddr/mvebu/ddr3_dfs.c
Normal file
1552
drivers/ddr/mvebu/ddr3_dfs.c
Normal file
File diff suppressed because it is too large
Load Diff
1374
drivers/ddr/mvebu/ddr3_dqs.c
Normal file
1374
drivers/ddr/mvebu/ddr3_dqs.c
Normal file
File diff suppressed because it is too large
Load Diff
1115
drivers/ddr/mvebu/ddr3_hw_training.c
Normal file
1115
drivers/ddr/mvebu/ddr3_hw_training.c
Normal file
File diff suppressed because it is too large
Load Diff
392
drivers/ddr/mvebu/ddr3_hw_training.h
Normal file
392
drivers/ddr/mvebu/ddr3_hw_training.h
Normal file
|
|
@ -0,0 +1,392 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __DDR3_TRAINING_H
|
||||
#define __DDR3_TRAINING_H
|
||||
|
||||
#include "ddr3_init.h"
|
||||
|
||||
#ifdef MV88F78X60
|
||||
#include "ddr3_axp.h"
|
||||
#elif defined(MV88F67XX)
|
||||
#include "ddr3_a370.h"
|
||||
#elif defined(MV88F672X)
|
||||
#include "ddr3_a375.h"
|
||||
#endif
|
||||
|
||||
/* The following is a list of Marvell status */
|
||||
#define MV_ERROR (-1)
|
||||
#define MV_OK (0x00) /* Operation succeeded */
|
||||
#define MV_FAIL (0x01) /* Operation failed */
|
||||
#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
|
||||
#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
|
||||
#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
|
||||
#define MV_BAD_PTR (0x05) /* Illegal pointer value */
|
||||
#define MV_BAD_SIZE (0x06) /* Illegal size */
|
||||
#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
|
||||
#define MV_SET_ERROR (0x08) /* Set operation failed */
|
||||
#define MV_GET_ERROR (0x09) /* Get operation failed */
|
||||
#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */
|
||||
#define MV_NOT_FOUND (0x0B) /* Item not found */
|
||||
#define MV_NO_MORE (0x0C) /* No more items found */
|
||||
#define MV_NO_SUCH (0x0D) /* No such item */
|
||||
#define MV_TIMEOUT (0x0E) /* Time Out */
|
||||
#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */
|
||||
#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
|
||||
#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
|
||||
#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
|
||||
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
|
||||
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
|
||||
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
|
||||
#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
|
||||
#define MV_HW_ERROR (0x17) /* Hardware error */
|
||||
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
|
||||
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
|
||||
#define MV_NOT_READY (0x1A) /* The other side is not ready yet */
|
||||
#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */
|
||||
#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */
|
||||
#define MV_NOT_STARTED (0x1D) /* Not started yet */
|
||||
#define MV_BUSY (0x1E) /* Item is busy. */
|
||||
#define MV_TERMINATE (0x1F) /* Item terminates it's work. */
|
||||
#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
|
||||
#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
|
||||
#define MV_WRITE_PROTECT (0x22) /* Write protected */
|
||||
|
||||
#define MV_INVALID (int)(-1)
|
||||
|
||||
/*
|
||||
* Debug (Enable/Disable modules) and Error report
|
||||
*/
|
||||
|
||||
#ifdef BASIC_DEBUG
|
||||
#define MV_DEBUG_WL
|
||||
#define MV_DEBUG_RL
|
||||
#define MV_DEBUG_DQS_RESULTS
|
||||
#endif
|
||||
|
||||
#ifdef FULL_DEBUG
|
||||
#define MV_DEBUG_WL
|
||||
#define MV_DEBUG_RL
|
||||
#define MV_DEBUG_DQS
|
||||
|
||||
#define MV_DEBUG_PBS
|
||||
#define MV_DEBUG_DFS
|
||||
#define MV_DEBUG_MAIN_FULL
|
||||
#define MV_DEBUG_DFS_FULL
|
||||
#define MV_DEBUG_DQS_FULL
|
||||
#define MV_DEBUG_RL_FULL
|
||||
#define MV_DEBUG_WL_FULL
|
||||
#endif
|
||||
|
||||
/*
|
||||
* General Consts
|
||||
*/
|
||||
|
||||
#define SDRAM_READ_WRITE_LEN_IN_WORDS 16
|
||||
#define SDRAM_READ_WRITE_LEN_IN_DOUBLE_WORDS 8
|
||||
#define CACHE_LINE_SIZE 0x20
|
||||
|
||||
#define SDRAM_CS_BASE 0x0
|
||||
|
||||
#define SRAM_BASE 0x40000000
|
||||
#define SRAM_SIZE 0xFFF
|
||||
|
||||
#define LEN_64BIT_STD_PATTERN 16
|
||||
#define LEN_64BIT_KILLER_PATTERN 128
|
||||
#define LEN_64BIT_SPECIAL_PATTERN 128
|
||||
#define LEN_64BIT_PBS_PATTERN 16
|
||||
#define LEN_WL_SUP_PATTERN 32
|
||||
|
||||
#define LEN_16BIT_STD_PATTERN 4
|
||||
#define LEN_16BIT_KILLER_PATTERN 128
|
||||
#define LEN_16BIT_SPECIAL_PATTERN 128
|
||||
#define LEN_16BIT_PBS_PATTERN 4
|
||||
|
||||
#define CMP_BYTE_SHIFT 8
|
||||
#define CMP_BYTE_MASK 0xFF
|
||||
#define PUP_SIZE 8
|
||||
|
||||
#define S 0
|
||||
#define C 1
|
||||
#define P 2
|
||||
#define D 3
|
||||
#define DQS 6
|
||||
#define PS 2
|
||||
#define DS 3
|
||||
#define PE 4
|
||||
#define DE 5
|
||||
|
||||
#define CS0 0
|
||||
#define MAX_DIMM_NUM 2
|
||||
#define MAX_DELAY 0x1F
|
||||
|
||||
/*
|
||||
* Invertion limit and phase1 limit are WA for the RL @ 1:1 design bug -
|
||||
* Armada 370 & AXP Z1
|
||||
*/
|
||||
#define MAX_DELAY_INV_LIMIT 0x5
|
||||
#define MIN_DELAY_PHASE_1_LIMIT 0x10
|
||||
|
||||
#define MAX_DELAY_INV (0x3F - MAX_DELAY_INV_LIMIT)
|
||||
#define MIN_DELAY 0
|
||||
#define MAX_PUP_NUM 9
|
||||
#define ECC_PUP 8
|
||||
#define DQ_NUM 8
|
||||
#define DQS_DQ_NUM 8
|
||||
#define INIT_WL_DELAY 13
|
||||
#define INIT_RL_DELAY 15
|
||||
#define TWLMRD_DELAY 20
|
||||
#define TCLK_3_DELAY 3
|
||||
#define ECC_BIT 8
|
||||
#define DMA_SIZE 64
|
||||
#define MV_DMA_0 0
|
||||
#define MAX_TRAINING_RETRY 10
|
||||
|
||||
#define PUP_RL_MODE 0x2
|
||||
#define PUP_WL_MODE 0
|
||||
#define PUP_PBS_TX 0x10
|
||||
#define PUP_PBS_TX_DM 0x1A
|
||||
#define PUP_PBS_RX 0x30
|
||||
#define PUP_DQS_WR 0x1
|
||||
#define PUP_DQS_RD 0x3
|
||||
#define PUP_BC 10
|
||||
#define PUP_DELAY_MASK 0x1F
|
||||
#define PUP_PHASE_MASK 0x7
|
||||
#define PUP_NUM_64BIT 8
|
||||
#define PUP_NUM_32BIT 4
|
||||
#define PUP_NUM_16BIT 2
|
||||
|
||||
/* control PHY registers */
|
||||
#define CNTRL_PUP_DESKEW 0x10
|
||||
|
||||
/* WL */
|
||||
#define COUNT_WL_HI_FREQ 2
|
||||
#define COUNT_WL 2
|
||||
#define COUNT_WL_RFRS 9
|
||||
#define WL_HI_FREQ_SHIFT 2
|
||||
#define WL_HI_FREQ_STATE 1
|
||||
#define COUNT_HW_WL 2
|
||||
|
||||
/* RL */
|
||||
/*
|
||||
* RL_MODE - this define uses the RL mode SW RL instead of the functional
|
||||
* window SW RL
|
||||
*/
|
||||
#define RL_MODE
|
||||
#define RL_WINDOW_WA
|
||||
#define MAX_PHASE_1TO1 2
|
||||
#define MAX_PHASE_2TO1 4
|
||||
|
||||
#define MAX_PHASE_RL_UL_1TO1 0
|
||||
#define MAX_PHASE_RL_L_1TO1 4
|
||||
#define MAX_PHASE_RL_UL_2TO1 3
|
||||
#define MAX_PHASE_RL_L_2TO1 7
|
||||
|
||||
#define RL_UNLOCK_STATE 0
|
||||
#define RL_WINDOW_STATE 1
|
||||
#define RL_FINAL_STATE 2
|
||||
#define RL_RETRY_COUNT 2
|
||||
#define COUNT_HW_RL 2
|
||||
|
||||
/* PBS */
|
||||
#define MAX_PBS 31
|
||||
#define MIN_PBS 0
|
||||
#define COUNT_PBS_PATTERN 2
|
||||
#define COUNT_PBS_STARTOVER 2
|
||||
#define COUNT_PBS_REPEAT 3
|
||||
#define COUNT_PBS_COMP_RETRY_NUM 2
|
||||
#define PBS_DIFF_LIMIT 31
|
||||
#define PATTERN_PBS_TX_A 0x55555555
|
||||
#define PATTERN_PBS_TX_B 0xAAAAAAAA
|
||||
|
||||
/* DQS */
|
||||
#define ADLL_ERROR 0x55
|
||||
#define ADLL_MAX 31
|
||||
#define ADLL_MIN 0
|
||||
#define MIN_WIN_SIZE 4
|
||||
#define VALID_WIN_THRS MIN_WIN_SIZE
|
||||
|
||||
#define MODE_2TO1 1
|
||||
#define MODE_1TO1 0
|
||||
|
||||
/*
|
||||
* Macros
|
||||
*/
|
||||
#define IS_PUP_ACTIVE(_data_, _pup_) (((_data_) >> (_pup_)) & 0x1)
|
||||
|
||||
/*
|
||||
* Internal ERROR codes
|
||||
*/
|
||||
#define MV_DDR3_TRAINING_ERR_WR_LVL_HW 0xDD302001
|
||||
#define MV_DDR3_TRAINING_ERR_LOAD_PATTERNS 0xDD302002
|
||||
#define MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ 0xDD302003
|
||||
#define MV_DDR3_TRAINING_ERR_DFS_H2L 0xDD302004
|
||||
#define MV_DDR3_TRAINING_ERR_DRAM_COMPARE 0xDD302005
|
||||
#define MV_DDR3_TRAINING_ERR_WIN_LIMITS 0xDD302006
|
||||
#define MV_DDR3_TRAINING_ERR_PUP_RANGE 0xDD302025
|
||||
#define MV_DDR3_TRAINING_ERR_DQS_LOW_LIMIT_SEARCH 0xDD302007
|
||||
#define MV_DDR3_TRAINING_ERR_DQS_HIGH_LIMIT_SEARCH 0xDD302008
|
||||
#define MV_DDR3_TRAINING_ERR_DQS_PATTERN 0xDD302009
|
||||
#define MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE 0xDD302010
|
||||
#define MV_DDR3_TRAINING_ERR_PBS_TX_MAX_VAL 0xDD302011
|
||||
#define MV_DDR3_TRAINING_ERR_PBS_RX_PER_BIT 0xDD302012
|
||||
#define MV_DDR3_TRAINING_ERR_PBS_TX_PER_BIT 0xDD302013
|
||||
#define MV_DDR3_TRAINING_ERR_PBS_RX_MAX_VAL 0xDD302014
|
||||
#define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP 0xDD302015
|
||||
#define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_MAX_VAL 0xDD302016
|
||||
#define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PATTERN 0xDD302017
|
||||
#define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PUP_UNLOCK 0xDD302018
|
||||
#define MV_DDR3_TRAINING_ERR_RD_LVL_PUP_UNLOCK 0xDD302019
|
||||
#define MV_DDR3_TRAINING_ERR_WR_LVL_SW 0xDD302020
|
||||
#define MV_DDR3_TRAINING_ERR_PRBS_RX 0xDD302021
|
||||
#define MV_DDR3_TRAINING_ERR_DQS_RX 0xDD302022
|
||||
#define MV_DDR3_TRAINING_ERR_PRBS_TX 0xDD302023
|
||||
#define MV_DDR3_TRAINING_ERR_DQS_TX 0xDD302024
|
||||
|
||||
/*
|
||||
* DRAM information structure
|
||||
*/
|
||||
typedef struct dram_info {
|
||||
u32 num_cs;
|
||||
u32 cs_ena;
|
||||
u32 num_of_std_pups; /* Q value = ddrWidth/8 - Without ECC!! */
|
||||
u32 num_of_total_pups; /* numOfStdPups + eccEna */
|
||||
u32 target_frequency; /* DDR Frequency */
|
||||
u32 ddr_width; /* 32/64 Bit or 16/32 Bit */
|
||||
u32 ecc_ena; /* 0/1 */
|
||||
u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
|
||||
u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
|
||||
u32 rl_max_phase;
|
||||
u32 rl_min_phase;
|
||||
u32 wl_max_phase;
|
||||
u32 wl_min_phase;
|
||||
u32 rd_smpl_dly;
|
||||
u32 rd_rdy_dly;
|
||||
u32 cl;
|
||||
u32 cwl;
|
||||
u32 mode_2t;
|
||||
int rl400_bug;
|
||||
int multi_cs_mr_support;
|
||||
int reg_dimm;
|
||||
} MV_DRAM_INFO;
|
||||
|
||||
enum training_modes {
|
||||
DQS_WR_MODE,
|
||||
WL_MODE_,
|
||||
RL_MODE_,
|
||||
DQS_RD_MODE,
|
||||
PBS_TX_DM_MODE,
|
||||
PBS_TX_MODE,
|
||||
PBS_RX_MODE,
|
||||
MAX_TRAINING_MODE,
|
||||
};
|
||||
|
||||
typedef struct dram_training_init {
|
||||
u32 reg_addr;
|
||||
u32 reg_value;
|
||||
} MV_DRAM_TRAINING_INIT;
|
||||
|
||||
typedef struct dram_mv_init {
|
||||
u32 reg_addr;
|
||||
u32 reg_value;
|
||||
} MV_DRAM_MC_INIT;
|
||||
|
||||
/* Board/Soc revisions define */
|
||||
enum board_rev {
|
||||
Z1,
|
||||
Z1_PCAC,
|
||||
Z1_RD_SLED,
|
||||
A0,
|
||||
A0_AMC
|
||||
};
|
||||
|
||||
typedef struct dram_modes {
|
||||
char *mode_name;
|
||||
u8 cpu_freq;
|
||||
u8 fab_freq;
|
||||
u8 chip_id;
|
||||
int chip_board_rev;
|
||||
MV_DRAM_MC_INIT *regs;
|
||||
MV_DRAM_TRAINING_INIT *vals;
|
||||
} MV_DRAM_MODES;
|
||||
|
||||
/*
|
||||
* Function Declarations
|
||||
*/
|
||||
|
||||
u32 cache_inv(u32 addr);
|
||||
void flush_l1_v7(u32 line);
|
||||
void flush_l1_v6(u32 line);
|
||||
|
||||
u32 ddr3_cl_to_valid_cl(u32 cl);
|
||||
u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
|
||||
|
||||
void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
|
||||
u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
|
||||
|
||||
int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx,
|
||||
u32 pbs_pattern_idx, u32 pbs_curr_val,
|
||||
u32 pbs_lock_val, u32 *skew_array,
|
||||
u8 *unlock_pup_dq_array, u32 ecc);
|
||||
|
||||
int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
||||
u32 *new_locked_pup, u32 *pattern,
|
||||
u32 pattern_len, u32 sdram_offset, int write,
|
||||
int mask, u32 *mask_pattern, int b_special_compare);
|
||||
|
||||
int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
||||
u32 *new_locked_pup, u32 *pattern, u32 pattern_len,
|
||||
u32 sdram_offset, int write, int mask,
|
||||
u32 *mask_pattern, int b_special_compare);
|
||||
|
||||
int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
||||
u32 *new_locked_pup, u32 *pattern,
|
||||
u32 pattern_len, u32 sdram_offset, int write,
|
||||
int mask, u32 *mask_pattern);
|
||||
|
||||
int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
||||
u32 *new_locked_pup, u32 *pattern,
|
||||
u32 sdram_offset);
|
||||
int ddr3_dram_sram_read(u32 src, u32 dst, u32 len);
|
||||
int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume);
|
||||
|
||||
int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
|
||||
int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
|
||||
|
||||
int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
|
||||
int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
|
||||
int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info);
|
||||
int ddr3_wl_supplement(MV_DRAM_INFO *dram_info);
|
||||
|
||||
int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info);
|
||||
int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
|
||||
|
||||
int ddr3_pbs_tx(MV_DRAM_INFO *dram_info);
|
||||
int ddr3_pbs_rx(MV_DRAM_INFO *dram_info);
|
||||
int ddr3_load_pbs_patterns(MV_DRAM_INFO *dram_info);
|
||||
|
||||
int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info);
|
||||
int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info);
|
||||
int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info);
|
||||
|
||||
void ddr3_static_training_init(void);
|
||||
|
||||
u8 ddr3_get_eprom_fabric(void);
|
||||
void ddr3_set_performance_params(MV_DRAM_INFO *dram_info);
|
||||
int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len);
|
||||
void ddr3_save_training(MV_DRAM_INFO *dram_info);
|
||||
int ddr3_read_training_results(void);
|
||||
int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info);
|
||||
int ddr3_get_min_max_read_sample_delay(u32 cs_enable, u32 reg, u32 *min,
|
||||
u32 *max, u32 *cs_max);
|
||||
int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max,
|
||||
u32 cs);
|
||||
int ddr3_odt_activate(int activate);
|
||||
int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info);
|
||||
void ddr3_print_freq(u32 freq);
|
||||
void ddr3_reset_phy_read_fifo(void);
|
||||
|
||||
#endif /* __DDR3_TRAINING_H */
|
||||
1219
drivers/ddr/mvebu/ddr3_init.c
Normal file
1219
drivers/ddr/mvebu/ddr3_init.c
Normal file
File diff suppressed because it is too large
Load Diff
143
drivers/ddr/mvebu/ddr3_init.h
Normal file
143
drivers/ddr/mvebu/ddr3_init.h
Normal file
|
|
@ -0,0 +1,143 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __DDR3_INIT_H
|
||||
#define __DDR3_INIT_H
|
||||
|
||||
/*
|
||||
* Debug
|
||||
*/
|
||||
|
||||
/*
|
||||
* MV_DEBUG_INIT need to be defines, otherwise the output of the
|
||||
* DDR2 training code is not complete and misleading
|
||||
*/
|
||||
#define MV_DEBUG_INIT
|
||||
|
||||
#ifdef MV_DEBUG_INIT
|
||||
#define DEBUG_INIT_S(s) puts(s)
|
||||
#define DEBUG_INIT_D(d, l) printf("%x", d)
|
||||
#define DEBUG_INIT_D_10(d, l) printf("%d", d)
|
||||
#else
|
||||
#define DEBUG_INIT_S(s)
|
||||
#define DEBUG_INIT_D(d, l)
|
||||
#define DEBUG_INIT_D_10(d, l)
|
||||
#endif
|
||||
|
||||
#ifdef MV_DEBUG_INIT_FULL
|
||||
#define DEBUG_INIT_FULL_S(s) puts(s)
|
||||
#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
|
||||
#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
|
||||
#define DEBUG_WR_REG(reg, val) \
|
||||
{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
|
||||
DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
|
||||
#define DEBUG_RD_REG(reg, val) \
|
||||
{ DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
|
||||
DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
|
||||
#else
|
||||
#define DEBUG_INIT_FULL_S(s)
|
||||
#define DEBUG_INIT_FULL_D(d, l)
|
||||
#define DEBUG_INIT_FULL_D_10(d, l)
|
||||
#define DEBUG_WR_REG(reg, val)
|
||||
#define DEBUG_RD_REG(reg, val)
|
||||
#endif
|
||||
|
||||
#define DEBUG_INIT_FULL_C(s, d, l) \
|
||||
{ DEBUG_INIT_FULL_S(s); DEBUG_INIT_FULL_D(d, l); DEBUG_INIT_FULL_S("\n"); }
|
||||
#define DEBUG_INIT_C(s, d, l) \
|
||||
{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
|
||||
|
||||
#define MV_MBUS_REGS_OFFSET (0x20000)
|
||||
|
||||
#include "ddr3_hw_training.h"
|
||||
|
||||
#define MAX_DIMM_NUM 2
|
||||
#define SPD_SIZE 128
|
||||
|
||||
#ifdef MV88F78X60
|
||||
#include "ddr3_axp.h"
|
||||
#elif defined(MV88F67XX)
|
||||
#include "ddr3_a370.h"
|
||||
#elif defined(MV88F672X)
|
||||
#include "ddr3_a375.h"
|
||||
#endif
|
||||
|
||||
/* DRR training Error codes */
|
||||
/* Stage 0 errors */
|
||||
#define MV_DDR3_TRAINING_ERR_BAD_SAR 0xDD300001
|
||||
/* Stage 1 errors */
|
||||
#define MV_DDR3_TRAINING_ERR_TWSI_FAIL 0xDD301001
|
||||
#define MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH 0xDD301001
|
||||
#define MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE 0xDD301003
|
||||
#define MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH 0xDD301004
|
||||
#define MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP 0xDD301005
|
||||
#define MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT 0xDD301006
|
||||
#define MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT 0xDD301007
|
||||
#define MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP 0xDD301008
|
||||
/* Stage 2 errors */
|
||||
#define MV_DDR3_TRAINING_ERR_HW_FAIL_BASE 0xDD302000
|
||||
|
||||
typedef enum config_type {
|
||||
CONFIG_ECC,
|
||||
CONFIG_MULTI_CS,
|
||||
CONFIG_BUS_WIDTH
|
||||
} MV_CONFIG_TYPE;
|
||||
|
||||
enum log_level {
|
||||
MV_LOG_LEVEL_0,
|
||||
MV_LOG_LEVEL_1,
|
||||
MV_LOG_LEVEL_2,
|
||||
MV_LOG_LEVEL_3
|
||||
};
|
||||
|
||||
int ddr3_hw_training(u32 target_freq, u32 ddr_width,
|
||||
int xor_bypass, u32 scrub_offs, u32 scrub_size,
|
||||
int dqs_clk_aligned, int debug_mode, int reg_dimm_skip_wl);
|
||||
|
||||
void ddr3_print_version(void);
|
||||
void fix_pll_val(u8 target_fab);
|
||||
u8 ddr3_get_eprom_fabric(void);
|
||||
u32 ddr3_get_fab_opt(void);
|
||||
u32 ddr3_get_cpu_freq(void);
|
||||
u32 ddr3_get_vco_freq(void);
|
||||
int ddr3_check_config(u32 addr, MV_CONFIG_TYPE config_type);
|
||||
u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
|
||||
u32 mask2);
|
||||
u32 ddr3_cl_to_valid_cl(u32 cl);
|
||||
u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
|
||||
u32 ddr3_get_cs_num_from_reg(void);
|
||||
u32 ddr3_get_cs_ena_from_reg(void);
|
||||
u8 mv_ctrl_rev_get(void);
|
||||
|
||||
u32 ddr3_get_log_level(void);
|
||||
|
||||
/* SPD */
|
||||
int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width);
|
||||
|
||||
/*
|
||||
* Accessor functions for the registers
|
||||
*/
|
||||
static inline void reg_write(u32 addr, u32 val)
|
||||
{
|
||||
writel(val, INTER_REGS_BASE + addr);
|
||||
}
|
||||
|
||||
static inline u32 reg_read(u32 addr)
|
||||
{
|
||||
return readl(INTER_REGS_BASE + addr);
|
||||
}
|
||||
|
||||
static inline void reg_bit_set(u32 addr, u32 mask)
|
||||
{
|
||||
setbits_le32(INTER_REGS_BASE + addr, mask);
|
||||
}
|
||||
|
||||
static inline void reg_bit_clr(u32 addr, u32 mask)
|
||||
{
|
||||
clrbits_le32(INTER_REGS_BASE + addr, mask);
|
||||
}
|
||||
|
||||
#endif /* __DDR3_INIT_H */
|
||||
924
drivers/ddr/mvebu/ddr3_patterns_64bit.h
Normal file
924
drivers/ddr/mvebu/ddr3_patterns_64bit.h
Normal file
|
|
@ -0,0 +1,924 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __DDR3_PATTERNS_64_H
|
||||
#define __DDR3_PATTERNS_64_H
|
||||
|
||||
/*
|
||||
* Patterns Declerations
|
||||
*/
|
||||
|
||||
u32 wl_sup_pattern[LEN_WL_SUP_PATTERN] __aligned(32) = {
|
||||
0x04030201, 0x08070605, 0x0c0b0a09, 0x100f0e0d,
|
||||
0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d,
|
||||
0x24232221, 0x28272625, 0x2c2b2a29, 0x302f2e2d,
|
||||
0x34333231, 0x38373635, 0x3c3b3a39, 0x403f3e3d,
|
||||
0x44434241, 0x48474645, 0x4c4b4a49, 0x504f4e4d,
|
||||
0x54535251, 0x58575655, 0x5c5b5a59, 0x605f5e5d,
|
||||
0x64636261, 0x68676665, 0x6c6b6a69, 0x706f6e6d,
|
||||
0x74737271, 0x78777675, 0x7c7b7a79, 0x807f7e7d
|
||||
};
|
||||
|
||||
u32 pbs_pattern_32b[2][LEN_PBS_PATTERN] __aligned(32) = {
|
||||
{
|
||||
0xAAAAAAAA, 0x55555555, 0xAAAAAAAA, 0x55555555,
|
||||
0xAAAAAAAA, 0x55555555, 0xAAAAAAAA, 0x55555555,
|
||||
0xAAAAAAAA, 0x55555555, 0xAAAAAAAA, 0x55555555,
|
||||
0xAAAAAAAA, 0x55555555, 0xAAAAAAAA, 0x55555555
|
||||
},
|
||||
{
|
||||
0x55555555, 0xAAAAAAAA, 0x55555555, 0xAAAAAAAA,
|
||||
0x55555555, 0xAAAAAAAA, 0x55555555, 0xAAAAAAAA,
|
||||
0x55555555, 0xAAAAAAAA, 0x55555555, 0xAAAAAAAA,
|
||||
0x55555555, 0xAAAAAAAA, 0x55555555, 0xAAAAAAAA
|
||||
}
|
||||
};
|
||||
|
||||
u32 pbs_pattern_64b[2][LEN_PBS_PATTERN] __aligned(32) = {
|
||||
{
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555
|
||||
},
|
||||
{
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA
|
||||
}
|
||||
};
|
||||
|
||||
u32 rl_pattern[LEN_STD_PATTERN] __aligned(32) = {
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x01010101, 0x01010101, 0x01010101, 0x01010101
|
||||
};
|
||||
|
||||
u32 killer_pattern_32b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
|
||||
{
|
||||
0x01010101, 0x00000000, 0x01010101, 0xFFFFFFFF,
|
||||
0x01010101, 0x00000000, 0x01010101, 0xFFFFFFFF,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0xFEFEFEFE,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0xFEFEFEFE,
|
||||
0x01010101, 0xFEFEFEFE, 0x01010101, 0x01010101,
|
||||
0x01010101, 0xFEFEFEFE, 0x01010101, 0x01010101,
|
||||
0xFEFEFEFE, 0x01010101, 0xFEFEFEFE, 0x00000000,
|
||||
0xFEFEFEFE, 0x01010101, 0xFEFEFEFE, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x01010101,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x01010101,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xFEFEFEFE,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xFEFEFEFE,
|
||||
0xFEFEFEFE, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFEFEFEFE, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFEFEFEFE, 0x00000000, 0xFEFEFEFE, 0x00000000,
|
||||
0xFEFEFEFE, 0x00000000, 0xFEFEFEFE, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x01010101,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x01010101,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x00000000,
|
||||
0x01010101, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0x01010101, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE
|
||||
},
|
||||
{
|
||||
0x02020202, 0x00000000, 0x02020202, 0xFFFFFFFF,
|
||||
0x02020202, 0x00000000, 0x02020202, 0xFFFFFFFF,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0xFDFDFDFD,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0xFDFDFDFD,
|
||||
0x02020202, 0xFDFDFDFD, 0x02020202, 0x02020202,
|
||||
0x02020202, 0xFDFDFDFD, 0x02020202, 0x02020202,
|
||||
0xFDFDFDFD, 0x02020202, 0xFDFDFDFD, 0x00000000,
|
||||
0xFDFDFDFD, 0x02020202, 0xFDFDFDFD, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x02020202,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x02020202,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xFDFDFDFD,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xFDFDFDFD,
|
||||
0xFDFDFDFD, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFDFDFDFD, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFDFDFDFD, 0x00000000, 0xFDFDFDFD, 0x00000000,
|
||||
0xFDFDFDFD, 0x00000000, 0xFDFDFDFD, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x02020202,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x02020202,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x00000000,
|
||||
0x02020202, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0x02020202, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD
|
||||
},
|
||||
{
|
||||
0x04040404, 0x00000000, 0x04040404, 0xFFFFFFFF,
|
||||
0x04040404, 0x00000000, 0x04040404, 0xFFFFFFFF,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0xFBFBFBFB,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0xFBFBFBFB,
|
||||
0x04040404, 0xFBFBFBFB, 0x04040404, 0x04040404,
|
||||
0x04040404, 0xFBFBFBFB, 0x04040404, 0x04040404,
|
||||
0xFBFBFBFB, 0x04040404, 0xFBFBFBFB, 0x00000000,
|
||||
0xFBFBFBFB, 0x04040404, 0xFBFBFBFB, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x04040404,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x04040404,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xFBFBFBFB,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xFBFBFBFB,
|
||||
0xFBFBFBFB, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFBFBFBFB, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFBFBFBFB, 0x00000000, 0xFBFBFBFB, 0x00000000,
|
||||
0xFBFBFBFB, 0x00000000, 0xFBFBFBFB, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x04040404,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x04040404,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x00000000,
|
||||
0x04040404, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0x04040404, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB
|
||||
},
|
||||
{
|
||||
0x08080808, 0x00000000, 0x08080808, 0xFFFFFFFF,
|
||||
0x08080808, 0x00000000, 0x08080808, 0xFFFFFFFF,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0xF7F7F7F7,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0xF7F7F7F7,
|
||||
0x08080808, 0xF7F7F7F7, 0x08080808, 0x08080808,
|
||||
0x08080808, 0xF7F7F7F7, 0x08080808, 0x08080808,
|
||||
0xF7F7F7F7, 0x08080808, 0xF7F7F7F7, 0x00000000,
|
||||
0xF7F7F7F7, 0x08080808, 0xF7F7F7F7, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x08080808,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x08080808,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xF7F7F7F7,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xF7F7F7F7,
|
||||
0xF7F7F7F7, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xF7F7F7F7, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xF7F7F7F7, 0x00000000, 0xF7F7F7F7, 0x00000000,
|
||||
0xF7F7F7F7, 0x00000000, 0xF7F7F7F7, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x08080808,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x08080808,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x00000000,
|
||||
0x08080808, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0x08080808, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7
|
||||
},
|
||||
{
|
||||
0x10101010, 0x00000000, 0x10101010, 0xFFFFFFFF,
|
||||
0x10101010, 0x00000000, 0x10101010, 0xFFFFFFFF,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0xEFEFEFEF,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0xEFEFEFEF,
|
||||
0x10101010, 0xEFEFEFEF, 0x10101010, 0x10101010,
|
||||
0x10101010, 0xEFEFEFEF, 0x10101010, 0x10101010,
|
||||
0xEFEFEFEF, 0x10101010, 0xEFEFEFEF, 0x00000000,
|
||||
0xEFEFEFEF, 0x10101010, 0xEFEFEFEF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x10101010,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x10101010,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xEFEFEFEF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xEFEFEFEF,
|
||||
0xEFEFEFEF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xEFEFEFEF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xEFEFEFEF, 0x00000000, 0xEFEFEFEF, 0x00000000,
|
||||
0xEFEFEFEF, 0x00000000, 0xEFEFEFEF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x10101010,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x10101010,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x00000000,
|
||||
0x10101010, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0x10101010, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF
|
||||
},
|
||||
{
|
||||
0x20202020, 0x00000000, 0x20202020, 0xFFFFFFFF,
|
||||
0x20202020, 0x00000000, 0x20202020, 0xFFFFFFFF,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0xDFDFDFDF,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0xDFDFDFDF,
|
||||
0x20202020, 0xDFDFDFDF, 0x20202020, 0x20202020,
|
||||
0x20202020, 0xDFDFDFDF, 0x20202020, 0x20202020,
|
||||
0xDFDFDFDF, 0x20202020, 0xDFDFDFDF, 0x00000000,
|
||||
0xDFDFDFDF, 0x20202020, 0xDFDFDFDF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x20202020,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x20202020,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xDFDFDFDF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xDFDFDFDF,
|
||||
0xDFDFDFDF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xDFDFDFDF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xDFDFDFDF, 0x00000000, 0xDFDFDFDF, 0x00000000,
|
||||
0xDFDFDFDF, 0x00000000, 0xDFDFDFDF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x20202020,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x20202020,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x00000000,
|
||||
0x20202020, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0x20202020, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF
|
||||
},
|
||||
{
|
||||
0x40404040, 0x00000000, 0x40404040, 0xFFFFFFFF,
|
||||
0x40404040, 0x00000000, 0x40404040, 0xFFFFFFFF,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0xBFBFBFBF,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0xBFBFBFBF,
|
||||
0x40404040, 0xBFBFBFBF, 0x40404040, 0x40404040,
|
||||
0x40404040, 0xBFBFBFBF, 0x40404040, 0x40404040,
|
||||
0xBFBFBFBF, 0x40404040, 0xBFBFBFBF, 0x00000000,
|
||||
0xBFBFBFBF, 0x40404040, 0xBFBFBFBF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x40404040,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x40404040,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xBFBFBFBF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xBFBFBFBF,
|
||||
0xBFBFBFBF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xBFBFBFBF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xBFBFBFBF, 0x00000000, 0xBFBFBFBF, 0x00000000,
|
||||
0xBFBFBFBF, 0x00000000, 0xBFBFBFBF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x40404040,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x40404040,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x00000000,
|
||||
0x40404040, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0x40404040, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF
|
||||
},
|
||||
{
|
||||
0x80808080, 0x00000000, 0x80808080, 0xFFFFFFFF,
|
||||
0x80808080, 0x00000000, 0x80808080, 0xFFFFFFFF,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x7F7F7F7F,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x7F7F7F7F,
|
||||
0x80808080, 0x7F7F7F7F, 0x80808080, 0x80808080,
|
||||
0x80808080, 0x7F7F7F7F, 0x80808080, 0x80808080,
|
||||
0x7F7F7F7F, 0x80808080, 0x7F7F7F7F, 0x00000000,
|
||||
0x7F7F7F7F, 0x80808080, 0x7F7F7F7F, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x80808080,
|
||||
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x80808080,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x7F7F7F7F,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x7F7F7F7F,
|
||||
0x7F7F7F7F, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x7F7F7F7F, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
||||
0x7F7F7F7F, 0x00000000, 0x7F7F7F7F, 0x00000000,
|
||||
0x7F7F7F7F, 0x00000000, 0x7F7F7F7F, 0x00000000,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x80808080,
|
||||
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x80808080,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x00000000,
|
||||
0x80808080, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x80808080, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F
|
||||
}
|
||||
};
|
||||
|
||||
u32 killer_pattern_64b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
|
||||
{
|
||||
0x01010101, 0x01010101, 0x00000000, 0x00000000,
|
||||
0x01010101, 0x01010101, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0x01010101, 0x01010101, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0x01010101, 0x01010101, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0x01010101, 0x01010101, 0x01010101, 0x01010101,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0x01010101,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x01010101,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x00000000, 0x00000000,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x01010101,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x01010101, 0x01010101, 0x00000000, 0x00000000,
|
||||
0x01010101, 0x01010101, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE
|
||||
},
|
||||
{
|
||||
0x02020202, 0x02020202, 0x00000000, 0x00000000,
|
||||
0x02020202, 0x02020202, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0x02020202, 0x02020202, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0x02020202, 0x02020202, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0x02020202, 0x02020202, 0x02020202, 0x02020202,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0x02020202,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x02020202,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x00000000, 0x00000000,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x02020202,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x02020202, 0x02020202, 0x00000000, 0x00000000,
|
||||
0x02020202, 0x02020202, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD
|
||||
},
|
||||
{
|
||||
0x04040404, 0x04040404, 0x00000000, 0x00000000,
|
||||
0x04040404, 0x04040404, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0x04040404, 0x04040404, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0x04040404, 0x04040404, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0x04040404, 0x04040404, 0x04040404, 0x04040404,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0x04040404,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x04040404,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x00000000, 0x00000000,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x04040404,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x04040404, 0x04040404, 0x00000000, 0x00000000,
|
||||
0x04040404, 0x04040404, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB
|
||||
},
|
||||
{
|
||||
0x08080808, 0x08080808, 0x00000000, 0x00000000,
|
||||
0x08080808, 0x08080808, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0x08080808, 0x08080808, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0x08080808, 0x08080808, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0x08080808, 0x08080808, 0x08080808, 0x08080808,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0x08080808,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x08080808,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x00000000, 0x00000000,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x08080808,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x08080808, 0x08080808, 0x00000000, 0x00000000,
|
||||
0x08080808, 0x08080808, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7
|
||||
},
|
||||
{
|
||||
0x10101010, 0x10101010, 0x00000000, 0x00000000,
|
||||
0x10101010, 0x10101010, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0x10101010, 0x10101010, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0x10101010, 0x10101010, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0x10101010, 0x10101010, 0x10101010, 0x10101010,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0x10101010,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x10101010,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x00000000, 0x00000000,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x10101010,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x10101010, 0x10101010, 0x00000000, 0x00000000,
|
||||
0x10101010, 0x10101010, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF
|
||||
},
|
||||
{
|
||||
0x20202020, 0x20202020, 0x00000000, 0x00000000,
|
||||
0x20202020, 0x20202020, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0x20202020, 0x20202020, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0x20202020, 0x20202020, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0x20202020,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x20202020,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x00000000, 0x00000000,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x20202020,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x20202020, 0x20202020, 0x00000000, 0x00000000,
|
||||
0x20202020, 0x20202020, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF
|
||||
},
|
||||
{
|
||||
0x40404040, 0x40404040, 0x00000000, 0x00000000,
|
||||
0x40404040, 0x40404040, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0x40404040, 0x40404040, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0x40404040, 0x40404040, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0x40404040, 0x40404040, 0x40404040, 0x40404040,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0x40404040,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x40404040,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x00000000, 0x00000000,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x40404040,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x40404040, 0x40404040, 0x00000000, 0x00000000,
|
||||
0x40404040, 0x40404040, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF
|
||||
},
|
||||
{
|
||||
0x80808080, 0x80808080, 0x00000000, 0x00000000,
|
||||
0x80808080, 0x80808080, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x80808080, 0x80808080, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x80808080, 0x80808080, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x80808080, 0x80808080, 0x80808080, 0x80808080,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x80808080,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x80808080,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x00000000, 0x00000000,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x80808080,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x80808080, 0x80808080, 0x00000000, 0x00000000,
|
||||
0x80808080, 0x80808080, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F
|
||||
}
|
||||
};
|
||||
|
||||
u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN] __aligned(32) = {
|
||||
{
|
||||
0x00000000, 0x00000000, 0x01010101, 0x01010101,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0x01010101,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0x01010101,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0x01010101,
|
||||
0x01010101, 0x01010101, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0x01010101, 0x01010101, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x01010101, 0x01010101, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0x00000000, 0x00000000, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x01010101, 0x01010101, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x01010101,
|
||||
0x00000000, 0x00000000, 0x01010101, 0x01010101,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE,
|
||||
0xFEFEFEFE, 0xFEFEFEFE, 0x00000000, 0x00000000
|
||||
},
|
||||
{
|
||||
0x00000000, 0x00000000, 0x02020202, 0x02020202,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0x02020202,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0x02020202,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0x02020202,
|
||||
0x02020202, 0x02020202, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0x02020202, 0x02020202, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x02020202, 0x02020202, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0x00000000, 0x00000000, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x02020202, 0x02020202, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x02020202,
|
||||
0x00000000, 0x00000000, 0x02020202, 0x02020202,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD,
|
||||
0xFDFDFDFD, 0xFDFDFDFD, 0x00000000, 0x00000000
|
||||
},
|
||||
{
|
||||
0x00000000, 0x00000000, 0x04040404, 0x04040404,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0x04040404,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0x04040404,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0x04040404,
|
||||
0x04040404, 0x04040404, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0x04040404, 0x04040404, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x04040404, 0x04040404, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0x00000000, 0x00000000, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x04040404, 0x04040404, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x04040404,
|
||||
0x00000000, 0x00000000, 0x04040404, 0x04040404,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB,
|
||||
0xFBFBFBFB, 0xFBFBFBFB, 0x00000000, 0x00000000
|
||||
},
|
||||
{
|
||||
0x00000000, 0x00000000, 0x08080808, 0x08080808,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0x08080808,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0x08080808,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0x08080808,
|
||||
0x08080808, 0x08080808, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0x08080808, 0x08080808, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x08080808, 0x08080808, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0x00000000, 0x00000000, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x08080808, 0x08080808, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x08080808,
|
||||
0x00000000, 0x00000000, 0x08080808, 0x08080808,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7,
|
||||
0xF7F7F7F7, 0xF7F7F7F7, 0x00000000, 0x00000000
|
||||
},
|
||||
{
|
||||
0x00000000, 0x00000000, 0x10101010, 0x10101010,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0x10101010,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0x10101010,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0x10101010,
|
||||
0x10101010, 0x10101010, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0x10101010, 0x10101010, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x10101010, 0x10101010, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0x00000000, 0x00000000, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x10101010, 0x10101010, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x10101010,
|
||||
0x00000000, 0x00000000, 0x10101010, 0x10101010,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF,
|
||||
0xEFEFEFEF, 0xEFEFEFEF, 0x00000000, 0x00000000
|
||||
},
|
||||
{
|
||||
0x00000000, 0x00000000, 0x20202020, 0x20202020,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0x20202020,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0x20202020,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0x20202020, 0x20202020, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x20202020, 0x20202020, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0x00000000, 0x00000000, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x20202020, 0x20202020, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x20202020,
|
||||
0x00000000, 0x00000000, 0x20202020, 0x20202020,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF,
|
||||
0xDFDFDFDF, 0xDFDFDFDF, 0x00000000, 0x00000000
|
||||
},
|
||||
{
|
||||
0x00000000, 0x00000000, 0x40404040, 0x40404040,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0x40404040,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0x40404040,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0x40404040,
|
||||
0x40404040, 0x40404040, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0x40404040, 0x40404040, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x40404040, 0x40404040, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0x00000000, 0x00000000, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x40404040, 0x40404040, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x40404040,
|
||||
0x00000000, 0x00000000, 0x40404040, 0x40404040,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF,
|
||||
0xBFBFBFBF, 0xBFBFBFBF, 0x00000000, 0x00000000
|
||||
},
|
||||
{
|
||||
0x00000000, 0x00000000, 0x80808080, 0x80808080,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x80808080,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x80808080,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x80808080,
|
||||
0x80808080, 0x80808080, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x80808080, 0x80808080, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x80808080, 0x80808080, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x00000000, 0x00000000, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x80808080, 0x80808080, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x80808080,
|
||||
0x00000000, 0x00000000, 0x80808080, 0x80808080,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F,
|
||||
0x7F7F7F7F, 0x7F7F7F7F, 0x00000000, 0x00000000
|
||||
}
|
||||
};
|
||||
|
||||
/* Fabric ratios table */
|
||||
u32 fabric_ratio[FAB_OPT] = {
|
||||
0x04010204,
|
||||
0x04020202,
|
||||
0x08020306,
|
||||
0x08020303,
|
||||
0x04020303,
|
||||
0x04020204,
|
||||
0x04010202,
|
||||
0x08030606,
|
||||
0x08030505,
|
||||
0x04020306,
|
||||
0x0804050A,
|
||||
0x04030606,
|
||||
0x04020404,
|
||||
0x04030306,
|
||||
0x04020505,
|
||||
0x08020505,
|
||||
0x04010303,
|
||||
0x08050A0A,
|
||||
0x04030408,
|
||||
0x04010102,
|
||||
0x08030306
|
||||
};
|
||||
|
||||
u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM] = {
|
||||
{3, 2, 5, 7, 1, 0, 6, 4},
|
||||
{2, 3, 6, 7, 1, 0, 4, 5},
|
||||
{1, 3, 5, 6, 0, 2, 4, 7},
|
||||
{0, 2, 4, 7, 1, 3, 5, 6},
|
||||
{3, 0, 4, 6, 1, 2, 5, 7},
|
||||
{0, 3, 5, 7, 1, 2, 4, 6},
|
||||
{2, 3, 5, 7, 1, 0, 4, 6},
|
||||
{0, 2, 5, 4, 1, 3, 6, 7},
|
||||
{2, 3, 4, 7, 0, 1, 5, 6}
|
||||
};
|
||||
|
||||
#endif /* __DDR3_PATTERNS_64_H */
|
||||
1592
drivers/ddr/mvebu/ddr3_pbs.c
Normal file
1592
drivers/ddr/mvebu/ddr3_pbs.c
Normal file
File diff suppressed because it is too large
Load Diff
1214
drivers/ddr/mvebu/ddr3_read_leveling.c
Normal file
1214
drivers/ddr/mvebu/ddr3_read_leveling.c
Normal file
File diff suppressed because it is too large
Load Diff
669
drivers/ddr/mvebu/ddr3_sdram.c
Normal file
669
drivers/ddr/mvebu/ddr3_sdram.c
Normal file
|
|
@ -0,0 +1,669 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#include "ddr3_hw_training.h"
|
||||
#include "xor.h"
|
||||
#include "xor_regs.h"
|
||||
|
||||
static void ddr3_flush_l1_line(u32 line);
|
||||
|
||||
extern u32 pbs_pattern[2][LEN_16BIT_PBS_PATTERN];
|
||||
extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN];
|
||||
#if defined(MV88F78X60)
|
||||
extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN];
|
||||
#endif
|
||||
extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
|
||||
|
||||
#if defined(MV88F78X60) || defined(MV88F672X)
|
||||
/* PBS locked dq (per pup) */
|
||||
u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
|
||||
u32 pbs_locked_dm[MAX_PUP_NUM] = { 0 };
|
||||
u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
|
||||
|
||||
int per_bit_data[MAX_PUP_NUM][DQ_NUM];
|
||||
#endif
|
||||
|
||||
static u32 sdram_data[LEN_KILLER_PATTERN] __aligned(32) = { 0 };
|
||||
|
||||
static struct crc_dma_desc dma_desc __aligned(32) = { 0 };
|
||||
|
||||
#define XOR_TIMEOUT 0x8000000
|
||||
|
||||
struct xor_channel_t {
|
||||
struct crc_dma_desc *desc;
|
||||
unsigned long desc_phys_addr;
|
||||
};
|
||||
|
||||
#define XOR_CAUSE_DONE_MASK(chan) ((0x1 | 0x2) << (chan * 16))
|
||||
|
||||
void xor_waiton_eng(int chan)
|
||||
{
|
||||
int timeout;
|
||||
|
||||
timeout = 0;
|
||||
while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) &
|
||||
XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))) {
|
||||
if (timeout > XOR_TIMEOUT)
|
||||
goto timeout;
|
||||
|
||||
timeout++;
|
||||
}
|
||||
|
||||
timeout = 0;
|
||||
while (mv_xor_state_get(chan) != MV_IDLE) {
|
||||
if (timeout > XOR_TIMEOUT)
|
||||
goto timeout;
|
||||
|
||||
timeout++;
|
||||
}
|
||||
|
||||
/* Clear int */
|
||||
reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)),
|
||||
~(XOR_CAUSE_DONE_MASK(XOR_CHAN(chan))));
|
||||
|
||||
timeout:
|
||||
return;
|
||||
}
|
||||
|
||||
static int special_compare_pattern(u32 uj)
|
||||
{
|
||||
if ((uj == 30) || (uj == 31) || (uj == 61) || (uj == 62) ||
|
||||
(uj == 93) || (uj == 94) || (uj == 126) || (uj == 127))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Compare code extracted as its used by multiple functions. This
|
||||
* reduces code-size and makes it easier to maintain it. Additionally
|
||||
* the code is not indented that much and therefore easier to read.
|
||||
*/
|
||||
static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern,
|
||||
u32 pup_groups, int debug_dqs)
|
||||
{
|
||||
u32 val;
|
||||
u32 uk;
|
||||
u32 var1;
|
||||
u32 var2;
|
||||
__maybe_unused u32 dq;
|
||||
|
||||
if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) {
|
||||
for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
|
||||
val = CMP_BYTE_SHIFT * uk;
|
||||
var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
|
||||
var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
|
||||
|
||||
if (var1 != var2) {
|
||||
*pup |= (1 << (uk + (PUP_NUM_32BIT *
|
||||
(uj % pup_groups))));
|
||||
|
||||
#ifdef MV_DEBUG_DQS
|
||||
if (!debug_dqs)
|
||||
continue;
|
||||
|
||||
for (dq = 0; dq < DQ_NUM; dq++) {
|
||||
val = uk + (PUP_NUM_32BIT *
|
||||
(uj % pup_groups));
|
||||
if (((var1 >> dq) & 0x1) !=
|
||||
((var2 >> dq) & 0x1))
|
||||
per_bit_data[val][dq] = 1;
|
||||
else
|
||||
per_bit_data[val][dq] = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern)
|
||||
{
|
||||
u32 val;
|
||||
u32 uk;
|
||||
u32 var1;
|
||||
u32 var2;
|
||||
|
||||
if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) {
|
||||
/* Found error */
|
||||
for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
|
||||
val = CMP_BYTE_SHIFT * uk;
|
||||
var1 = (sdram_data[uj] >> val) & CMP_BYTE_MASK;
|
||||
var2 = (pattern[uj] >> val) & CMP_BYTE_MASK;
|
||||
if (var1 != var2)
|
||||
*pup |= (1 << (uk % PUP_NUM_16BIT));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Name: ddr3_sdram_compare
|
||||
* Desc: Execute compare per PUP
|
||||
* Args: unlock_pup Bit array of the unlock pups
|
||||
* new_locked_pup Output bit array of the pups with failed compare
|
||||
* pattern Pattern to compare
|
||||
* pattern_len Length of pattern (in bytes)
|
||||
* sdram_offset offset address to the SDRAM
|
||||
* write write to the SDRAM before read
|
||||
* mask compare pattern with mask;
|
||||
* mask_pattern Mask to compare pattern
|
||||
*
|
||||
* Notes:
|
||||
* Returns: MV_OK if success, other error code if fail.
|
||||
*/
|
||||
int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
||||
u32 *new_locked_pup, u32 *pattern,
|
||||
u32 pattern_len, u32 sdram_offset, int write,
|
||||
int mask, u32 *mask_pattern,
|
||||
int special_compare)
|
||||
{
|
||||
u32 uj;
|
||||
__maybe_unused u32 pup_groups;
|
||||
__maybe_unused u32 dq;
|
||||
|
||||
#if !defined(MV88F67XX)
|
||||
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
|
||||
pup_groups = 2;
|
||||
else
|
||||
pup_groups = 1;
|
||||
#endif
|
||||
|
||||
ddr3_reset_phy_read_fifo();
|
||||
|
||||
/* Check if need to write to sdram before read */
|
||||
if (write == 1)
|
||||
ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
|
||||
|
||||
ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
|
||||
|
||||
/* Compare read result to write */
|
||||
for (uj = 0; uj < pattern_len; uj++) {
|
||||
if (special_compare && special_compare_pattern(uj))
|
||||
continue;
|
||||
|
||||
#if defined(MV88F78X60) || defined(MV88F672X)
|
||||
compare_pattern_v1(uj, new_locked_pup, pattern, pup_groups, 1);
|
||||
#elif defined(MV88F67XX)
|
||||
compare_pattern_v2(uj, new_locked_pup, pattern);
|
||||
#endif
|
||||
}
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
#if defined(MV88F78X60) || defined(MV88F672X)
|
||||
/*
|
||||
* Name: ddr3_sdram_dm_compare
|
||||
* Desc: Execute compare per PUP
|
||||
* Args: unlock_pup Bit array of the unlock pups
|
||||
* new_locked_pup Output bit array of the pups with failed compare
|
||||
* pattern Pattern to compare
|
||||
* pattern_len Length of pattern (in bytes)
|
||||
* sdram_offset offset address to the SDRAM
|
||||
* write write to the SDRAM before read
|
||||
* mask compare pattern with mask;
|
||||
* mask_pattern Mask to compare pattern
|
||||
*
|
||||
* Notes:
|
||||
* Returns: MV_OK if success, other error code if fail.
|
||||
*/
|
||||
int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
||||
u32 *new_locked_pup, u32 *pattern,
|
||||
u32 sdram_offset)
|
||||
{
|
||||
u32 uj, uk, var1, var2, pup_groups;
|
||||
u32 val;
|
||||
u32 pup = 0;
|
||||
|
||||
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
|
||||
pup_groups = 2;
|
||||
else
|
||||
pup_groups = 1;
|
||||
|
||||
ddr3_dram_sram_burst((u32)pattern, SDRAM_PBS_TX_OFFS,
|
||||
LEN_PBS_PATTERN);
|
||||
ddr3_dram_sram_burst(SDRAM_PBS_TX_OFFS, (u32)sdram_data,
|
||||
LEN_PBS_PATTERN);
|
||||
|
||||
/* Validate the correctness of the results */
|
||||
for (uj = 0; uj < LEN_PBS_PATTERN; uj++)
|
||||
compare_pattern_v1(uj, &pup, pattern, pup_groups, 0);
|
||||
|
||||
/* Test the DM Signals */
|
||||
*(u32 *)(SDRAM_PBS_TX_OFFS + 0x10) = 0x12345678;
|
||||
*(u32 *)(SDRAM_PBS_TX_OFFS + 0x14) = 0x12345678;
|
||||
|
||||
sdram_data[0] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10);
|
||||
sdram_data[1] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14);
|
||||
|
||||
for (uj = 0; uj < 2; uj++) {
|
||||
if (((sdram_data[uj]) != (pattern[uj])) &&
|
||||
(*new_locked_pup != 0xFF)) {
|
||||
for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
|
||||
val = CMP_BYTE_SHIFT * uk;
|
||||
var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
|
||||
var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
|
||||
if (var1 != var2) {
|
||||
*new_locked_pup |= (1 << (uk +
|
||||
(PUP_NUM_32BIT * (uj % pup_groups))));
|
||||
*new_locked_pup |= pup;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Name: ddr3_sdram_pbs_compare
|
||||
* Desc: Execute SRAM compare per PUP and DQ.
|
||||
* Args: pup_locked bit array of locked pups
|
||||
* is_tx Indicate whether Rx or Tx
|
||||
* pbs_pattern_idx Index of PBS pattern
|
||||
* pbs_curr_val The PBS value
|
||||
* pbs_lock_val The value to set to locked PBS
|
||||
* skew_array Global array to update with the compare results
|
||||
* ai_unlock_pup_dq_array bit array of the locked / unlocked pups per dq.
|
||||
* Notes:
|
||||
* Returns: MV_OK if success, other error code if fail.
|
||||
*/
|
||||
int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked,
|
||||
int is_tx, u32 pbs_pattern_idx,
|
||||
u32 pbs_curr_val, u32 pbs_lock_val,
|
||||
u32 *skew_array, u8 *unlock_pup_dq_array,
|
||||
u32 ecc)
|
||||
{
|
||||
/* bit array failed dq per pup for current compare */
|
||||
u32 pbs_write_pup[DQ_NUM] = { 0 };
|
||||
u32 update_pup; /* pup as HW convention */
|
||||
u32 max_pup; /* maximal pup index */
|
||||
u32 pup_addr;
|
||||
u32 ui, dq, pup;
|
||||
int var1, var2;
|
||||
u32 sdram_offset, pup_groups, tmp_pup;
|
||||
u32 *pattern_ptr;
|
||||
u32 val;
|
||||
|
||||
/* Choose pattern */
|
||||
switch (dram_info->ddr_width) {
|
||||
#if defined(MV88F672X)
|
||||
case 16:
|
||||
pattern_ptr = (u32 *)&pbs_pattern[pbs_pattern_idx];
|
||||
break;
|
||||
#endif
|
||||
case 32:
|
||||
pattern_ptr = (u32 *)&pbs_pattern_32b[pbs_pattern_idx];
|
||||
break;
|
||||
#if defined(MV88F78X60)
|
||||
case 64:
|
||||
pattern_ptr = (u32 *)&pbs_pattern_64b[pbs_pattern_idx];
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return MV_FAIL;
|
||||
}
|
||||
|
||||
max_pup = dram_info->num_of_std_pups;
|
||||
|
||||
sdram_offset = SDRAM_PBS_I_OFFS + pbs_pattern_idx * SDRAM_PBS_NEXT_OFFS;
|
||||
|
||||
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
|
||||
pup_groups = 2;
|
||||
else
|
||||
pup_groups = 1;
|
||||
|
||||
ddr3_reset_phy_read_fifo();
|
||||
|
||||
/* Check if need to write to sdram before read */
|
||||
if (is_tx == 1) {
|
||||
ddr3_dram_sram_burst((u32)pattern_ptr, sdram_offset,
|
||||
LEN_PBS_PATTERN);
|
||||
}
|
||||
|
||||
ddr3_dram_sram_read(sdram_offset, (u32)sdram_data, LEN_PBS_PATTERN);
|
||||
|
||||
/* Compare read result to write */
|
||||
for (ui = 0; ui < LEN_PBS_PATTERN; ui++) {
|
||||
if ((sdram_data[ui]) != (pattern_ptr[ui])) {
|
||||
/* found error */
|
||||
/* error in low pup group */
|
||||
for (pup = 0; pup < PUP_NUM_32BIT; pup++) {
|
||||
val = CMP_BYTE_SHIFT * pup;
|
||||
var1 = ((sdram_data[ui] >> val) &
|
||||
CMP_BYTE_MASK);
|
||||
var2 = ((pattern_ptr[ui] >> val) &
|
||||
CMP_BYTE_MASK);
|
||||
|
||||
if (var1 != var2) {
|
||||
if (dram_info->ddr_width > 16) {
|
||||
tmp_pup = (pup + PUP_NUM_32BIT *
|
||||
(ui % pup_groups));
|
||||
} else {
|
||||
tmp_pup = (pup % PUP_NUM_16BIT);
|
||||
}
|
||||
|
||||
update_pup = (1 << tmp_pup);
|
||||
if (ecc && (update_pup != 0x1))
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Pup is failed - Go over all DQs and
|
||||
* look for failures
|
||||
*/
|
||||
for (dq = 0; dq < DQ_NUM; dq++) {
|
||||
val = tmp_pup * (1 - ecc) +
|
||||
ecc * ECC_PUP;
|
||||
if (((var1 >> dq) & 0x1) !=
|
||||
((var2 >> dq) & 0x1)) {
|
||||
if (pbs_locked_dq[val][dq] == 1 &&
|
||||
pbs_locked_value[val][dq] != pbs_curr_val)
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Activate write to
|
||||
* update PBS to
|
||||
* pbs_lock_val
|
||||
*/
|
||||
pbs_write_pup[dq] |=
|
||||
update_pup;
|
||||
|
||||
/*
|
||||
* Update the
|
||||
* unlock_pup_dq_array
|
||||
*/
|
||||
unlock_pup_dq_array[dq] &=
|
||||
~update_pup;
|
||||
|
||||
/*
|
||||
* Lock PBS value for
|
||||
* failed bits in
|
||||
* compare operation
|
||||
*/
|
||||
skew_array[tmp_pup * DQ_NUM + dq] =
|
||||
pbs_curr_val;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pup_addr = (is_tx == 1) ? PUP_PBS_TX : PUP_PBS_RX;
|
||||
|
||||
/* Set last failed bits PBS to min / max pbs value */
|
||||
for (dq = 0; dq < DQ_NUM; dq++) {
|
||||
for (pup = 0; pup < max_pup; pup++) {
|
||||
if (pbs_write_pup[dq] & (1 << pup)) {
|
||||
val = pup * (1 - ecc) + ecc * ECC_PUP;
|
||||
if (pbs_locked_dq[val][dq] == 1 &&
|
||||
pbs_locked_value[val][dq] != pbs_curr_val)
|
||||
continue;
|
||||
|
||||
/* Mark the dq as locked */
|
||||
pbs_locked_dq[val][dq] = 1;
|
||||
pbs_locked_value[val][dq] = pbs_curr_val;
|
||||
ddr3_write_pup_reg(pup_addr +
|
||||
pbs_dq_mapping[val][dq],
|
||||
CS0, val, 0, pbs_lock_val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Name: ddr3_sdram_direct_compare
|
||||
* Desc: Execute compare per PUP without DMA (no burst mode)
|
||||
* Args: unlock_pup Bit array of the unlock pups
|
||||
* new_locked_pup Output bit array of the pups with failed compare
|
||||
* pattern Pattern to compare
|
||||
* pattern_len Length of pattern (in bytes)
|
||||
* sdram_offset offset address to the SDRAM
|
||||
* write write to the SDRAM before read
|
||||
* mask compare pattern with mask;
|
||||
* auiMaskPatter Mask to compare pattern
|
||||
*
|
||||
* Notes:
|
||||
* Returns: MV_OK if success, other error code if fail.
|
||||
*/
|
||||
int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
||||
u32 *new_locked_pup, u32 *pattern,
|
||||
u32 pattern_len, u32 sdram_offset,
|
||||
int write, int mask, u32 *mask_pattern)
|
||||
{
|
||||
u32 uj, uk, pup_groups;
|
||||
u32 *sdram_addr; /* used to read from SDRAM */
|
||||
|
||||
sdram_addr = (u32 *)sdram_offset;
|
||||
|
||||
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
|
||||
pup_groups = 2;
|
||||
else
|
||||
pup_groups = 1;
|
||||
|
||||
/* Check if need to write before read */
|
||||
if (write == 1) {
|
||||
for (uk = 0; uk < pattern_len; uk++) {
|
||||
*sdram_addr = pattern[uk];
|
||||
sdram_addr++;
|
||||
}
|
||||
}
|
||||
|
||||
sdram_addr = (u32 *)sdram_offset;
|
||||
|
||||
for (uk = 0; uk < pattern_len; uk++) {
|
||||
sdram_data[uk] = *sdram_addr;
|
||||
sdram_addr++;
|
||||
}
|
||||
|
||||
/* Compare read result to write */
|
||||
for (uj = 0; uj < pattern_len; uj++) {
|
||||
if (dram_info->ddr_width > 16) {
|
||||
compare_pattern_v1(uj, new_locked_pup, pattern,
|
||||
pup_groups, 0);
|
||||
} else {
|
||||
compare_pattern_v2(uj, new_locked_pup, pattern);
|
||||
}
|
||||
}
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Name: ddr3_dram_sram_burst
|
||||
* Desc: Read from the SDRAM in burst of 64 bytes
|
||||
* Args: src
|
||||
* dst
|
||||
* Notes: Using the XOR mechanism
|
||||
* Returns: MV_OK if success, other error code if fail.
|
||||
*/
|
||||
int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len)
|
||||
{
|
||||
u32 chan, byte_count, cs_num, byte;
|
||||
struct xor_channel_t channel;
|
||||
|
||||
chan = 0;
|
||||
byte_count = len * 4;
|
||||
|
||||
/* Wait for previous transfer completion */
|
||||
while (mv_xor_state_get(chan) != MV_IDLE)
|
||||
;
|
||||
|
||||
/* Build the channel descriptor */
|
||||
channel.desc = &dma_desc;
|
||||
|
||||
/* Enable Address Override and set correct src and dst */
|
||||
if (src < SRAM_BASE) {
|
||||
/* src is DRAM CS, dst is SRAM */
|
||||
cs_num = (src / (1 + SDRAM_CS_SIZE));
|
||||
reg_write(XOR_ADDR_OVRD_REG(0, 0),
|
||||
((cs_num << 1) | (1 << 0)));
|
||||
channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE));
|
||||
channel.desc->dst_addr = dst;
|
||||
} else {
|
||||
/* src is SRAM, dst is DRAM CS */
|
||||
cs_num = (dst / (1 + SDRAM_CS_SIZE));
|
||||
reg_write(XOR_ADDR_OVRD_REG(0, 0),
|
||||
((cs_num << 25) | (1 << 24)));
|
||||
channel.desc->src_addr0 = (src);
|
||||
channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
|
||||
channel.desc->src_addr0 = src;
|
||||
channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
|
||||
}
|
||||
|
||||
channel.desc->src_addr1 = 0;
|
||||
channel.desc->byte_cnt = byte_count;
|
||||
channel.desc->next_desc_ptr = 0;
|
||||
channel.desc->status = 1 << 31;
|
||||
channel.desc->desc_cmd = 0x0;
|
||||
channel.desc_phys_addr = (unsigned long)&dma_desc;
|
||||
|
||||
ddr3_flush_l1_line((u32)&dma_desc);
|
||||
|
||||
/* Issue the transfer */
|
||||
if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK)
|
||||
return MV_FAIL;
|
||||
|
||||
/* Wait for completion */
|
||||
xor_waiton_eng(chan);
|
||||
|
||||
if (dst > SRAM_BASE) {
|
||||
for (byte = 0; byte < byte_count; byte += 0x20)
|
||||
cache_inv(dst + byte);
|
||||
}
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Name: ddr3_flush_l1_line
|
||||
* Desc:
|
||||
* Args:
|
||||
* Notes:
|
||||
* Returns: MV_OK if success, other error code if fail.
|
||||
*/
|
||||
static void ddr3_flush_l1_line(u32 line)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
#if defined(MV88F672X)
|
||||
reg = 1;
|
||||
#else
|
||||
reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) &
|
||||
(1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
|
||||
#ifdef MV88F67XX
|
||||
reg = ~reg & (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (reg) {
|
||||
/* V7 Arch mode */
|
||||
flush_l1_v7(line);
|
||||
flush_l1_v7(line + CACHE_LINE_SIZE);
|
||||
} else {
|
||||
/* V6 Arch mode */
|
||||
flush_l1_v6(line);
|
||||
flush_l1_v6(line + CACHE_LINE_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
int ddr3_dram_sram_read(u32 src, u32 dst, u32 len)
|
||||
{
|
||||
u32 ui;
|
||||
u32 *dst_ptr, *src_ptr;
|
||||
|
||||
dst_ptr = (u32 *)dst;
|
||||
src_ptr = (u32 *)src;
|
||||
|
||||
for (ui = 0; ui < len; ui++) {
|
||||
*dst_ptr = *src_ptr;
|
||||
dst_ptr++;
|
||||
src_ptr++;
|
||||
}
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
||||
u32 *new_locked_pup, u32 *pattern,
|
||||
u32 pattern_len, u32 sdram_offset, int write,
|
||||
int mask, u32 *mask_pattern,
|
||||
int special_compare)
|
||||
{
|
||||
u32 uj, pup_groups;
|
||||
|
||||
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
|
||||
pup_groups = 2;
|
||||
else
|
||||
pup_groups = 1;
|
||||
|
||||
ddr3_reset_phy_read_fifo();
|
||||
|
||||
/* Check if need to write to sdram before read */
|
||||
if (write == 1)
|
||||
ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
|
||||
|
||||
ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
|
||||
|
||||
/* Compare read result to write */
|
||||
for (uj = 0; uj < pattern_len; uj++) {
|
||||
if (special_compare && special_compare_pattern(uj))
|
||||
continue;
|
||||
|
||||
if (dram_info->ddr_width > 16) {
|
||||
compare_pattern_v1(uj, new_locked_pup, pattern,
|
||||
pup_groups, 1);
|
||||
} else {
|
||||
compare_pattern_v2(uj, new_locked_pup, pattern);
|
||||
}
|
||||
}
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
void ddr3_reset_phy_read_fifo(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/* reset read FIFO */
|
||||
reg = reg_read(REG_DRAM_TRAINING_ADDR);
|
||||
/* Start Auto Read Leveling procedure */
|
||||
reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
|
||||
|
||||
/* 0x15B0 - Training Register */
|
||||
reg_write(REG_DRAM_TRAINING_ADDR, reg);
|
||||
|
||||
reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
|
||||
reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) +
|
||||
(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
|
||||
|
||||
/* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */
|
||||
/* 0x15B8 - Training SW 2 Register */
|
||||
reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
|
||||
|
||||
do {
|
||||
reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
|
||||
(1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS);
|
||||
} while (reg); /* Wait for '0' */
|
||||
|
||||
reg = reg_read(REG_DRAM_TRAINING_ADDR);
|
||||
|
||||
/* Clear Auto Read Leveling procedure */
|
||||
reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
|
||||
|
||||
/* 0x15B0 - Training Register */
|
||||
reg_write(REG_DRAM_TRAINING_ADDR, reg);
|
||||
}
|
||||
1300
drivers/ddr/mvebu/ddr3_spd.c
Normal file
1300
drivers/ddr/mvebu/ddr3_spd.c
Normal file
File diff suppressed because it is too large
Load Diff
1366
drivers/ddr/mvebu/ddr3_write_leveling.c
Normal file
1366
drivers/ddr/mvebu/ddr3_write_leveling.c
Normal file
File diff suppressed because it is too large
Load Diff
436
drivers/ddr/mvebu/xor.c
Normal file
436
drivers/ddr/mvebu/xor.c
Normal file
|
|
@ -0,0 +1,436 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#include "xor.h"
|
||||
#include "xor_regs.h"
|
||||
|
||||
static u32 xor_regs_ctrl_backup;
|
||||
static u32 xor_regs_base_backup[MAX_CS];
|
||||
static u32 xor_regs_mask_backup[MAX_CS];
|
||||
|
||||
static void mv_xor_hal_init(u32 chan_num);
|
||||
static int mv_xor_cmd_set(u32 chan, int command);
|
||||
static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
|
||||
|
||||
void mv_sys_xor_init(MV_DRAM_INFO *dram_info)
|
||||
{
|
||||
u32 reg, ui, base, cs_count;
|
||||
|
||||
xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0));
|
||||
for (ui = 0; ui < MAX_CS; ui++)
|
||||
xor_regs_base_backup[ui] = reg_read(XOR_BASE_ADDR_REG(0, ui));
|
||||
for (ui = 0; ui < MAX_CS; ui++)
|
||||
xor_regs_mask_backup[ui] = reg_read(XOR_SIZE_MASK_REG(0, ui));
|
||||
|
||||
reg = 0;
|
||||
for (ui = 0; ui < (dram_info->num_cs + 1); ui++) {
|
||||
/* Enable Window x for each CS */
|
||||
reg |= (0x1 << (ui));
|
||||
/* Enable Window x for each CS */
|
||||
reg |= (0x3 << ((ui * 2) + 16));
|
||||
}
|
||||
|
||||
reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg);
|
||||
|
||||
/* Last window - Base - 0x40000000, Attribute 0x1E - SRAM */
|
||||
base = (SRAM_BASE & 0xFFFF0000) | 0x1E00;
|
||||
reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base);
|
||||
/* Last window - Size - 64 MB */
|
||||
reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000);
|
||||
|
||||
cs_count = 0;
|
||||
for (ui = 0; ui < MAX_CS; ui++) {
|
||||
if (dram_info->cs_ena & (1 << ui)) {
|
||||
/*
|
||||
* Window x - Base - 0x00000000, Attribute 0x0E - DRAM
|
||||
*/
|
||||
base = 0;
|
||||
switch (ui) {
|
||||
case 0:
|
||||
base |= 0xE00;
|
||||
break;
|
||||
case 1:
|
||||
base |= 0xD00;
|
||||
break;
|
||||
case 2:
|
||||
base |= 0xB00;
|
||||
break;
|
||||
case 3:
|
||||
base |= 0x700;
|
||||
break;
|
||||
}
|
||||
|
||||
reg_write(XOR_BASE_ADDR_REG(0, cs_count), base);
|
||||
|
||||
/* Window x - Size - 256 MB */
|
||||
reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000);
|
||||
cs_count++;
|
||||
}
|
||||
}
|
||||
|
||||
mv_xor_hal_init(1);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void mv_sys_xor_finish(void)
|
||||
{
|
||||
u32 ui;
|
||||
|
||||
reg_write(XOR_WINDOW_CTRL_REG(0, 0), xor_regs_ctrl_backup);
|
||||
for (ui = 0; ui < MAX_CS; ui++)
|
||||
reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]);
|
||||
for (ui = 0; ui < MAX_CS; ui++)
|
||||
reg_write(XOR_SIZE_MASK_REG(0, ui), xor_regs_mask_backup[ui]);
|
||||
|
||||
reg_write(XOR_ADDR_OVRD_REG(0, 0), 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* mv_xor_hal_init - Initialize XOR engine
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This function initialize XOR unit.
|
||||
* INPUT:
|
||||
* None.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
|
||||
*/
|
||||
static void mv_xor_hal_init(u32 chan_num)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
/* Abort any XOR activity & set default configuration */
|
||||
for (i = 0; i < chan_num; i++) {
|
||||
mv_xor_cmd_set(i, MV_STOP);
|
||||
mv_xor_ctrl_set(i, (1 << XEXCR_REG_ACC_PROTECT_OFFS) |
|
||||
(4 << XEXCR_DST_BURST_LIMIT_OFFS) |
|
||||
(4 << XEXCR_SRC_BURST_LIMIT_OFFS));
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* mv_xor_ctrl_set - Set XOR channel control registers
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* INPUT:
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
|
||||
* NOTE:
|
||||
* This function does not modify the OperationMode field of control register.
|
||||
*
|
||||
*/
|
||||
static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Update the XOR Engine [0..1] Configuration Registers (XExCR) */
|
||||
val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)))
|
||||
& XEXCR_OPERATION_MODE_MASK;
|
||||
xor_ctrl &= ~XEXCR_OPERATION_MODE_MASK;
|
||||
xor_ctrl |= val;
|
||||
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl);
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
|
||||
u32 init_val_low)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* Parameter checking */
|
||||
if (chan >= MV_XOR_MAX_CHAN)
|
||||
return MV_BAD_PARAM;
|
||||
|
||||
if (MV_ACTIVE == mv_xor_state_get(chan))
|
||||
return MV_BUSY;
|
||||
|
||||
if ((block_size < XEXBSR_BLOCK_SIZE_MIN_VALUE) ||
|
||||
(block_size > XEXBSR_BLOCK_SIZE_MAX_VALUE))
|
||||
return MV_BAD_PARAM;
|
||||
|
||||
/* Set the operation mode to Memory Init */
|
||||
tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
|
||||
tmp &= ~XEXCR_OPERATION_MODE_MASK;
|
||||
tmp |= XEXCR_OPERATION_MODE_MEM_INIT;
|
||||
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), tmp);
|
||||
|
||||
/*
|
||||
* Update the start_ptr field in XOR Engine [0..1] Destination Pointer
|
||||
* Register (XExDPR0)
|
||||
*/
|
||||
reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr);
|
||||
|
||||
/*
|
||||
* Update the BlockSize field in the XOR Engine[0..1] Block Size
|
||||
* Registers (XExBSR)
|
||||
*/
|
||||
reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
|
||||
block_size);
|
||||
|
||||
/*
|
||||
* Update the field InitValL in the XOR Engine Initial Value Register
|
||||
* Low (XEIVRL)
|
||||
*/
|
||||
reg_write(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), init_val_low);
|
||||
|
||||
/*
|
||||
* Update the field InitValH in the XOR Engine Initial Value Register
|
||||
* High (XEIVRH)
|
||||
*/
|
||||
reg_write(XOR_INIT_VAL_HIGH_REG(XOR_UNIT(chan)), init_val_high);
|
||||
|
||||
/* Start transfer */
|
||||
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
|
||||
XEXACTR_XESTART_MASK);
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* mv_xor_transfer - Transfer data from source to destination on one of
|
||||
* three modes (XOR,CRC32,DMA)
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This function initiates XOR channel, according to function parameters,
|
||||
* in order to perform XOR or CRC32 or DMA transaction.
|
||||
* To gain maximum performance the user is asked to keep the following
|
||||
* restrictions:
|
||||
* 1) Selected engine is available (not busy).
|
||||
* 1) This module does not take into consideration CPU MMU issues.
|
||||
* In order for the XOR engine to access the appropreate source
|
||||
* and destination, address parameters must be given in system
|
||||
* physical mode.
|
||||
* 2) This API does not take care of cache coherency issues. The source,
|
||||
* destination and in case of chain the descriptor list are assumed
|
||||
* to be cache coherent.
|
||||
* 4) Parameters validity. For example, does size parameter exceeds
|
||||
* maximum byte count of descriptor mode (16M or 64K).
|
||||
*
|
||||
* INPUT:
|
||||
* chan - XOR channel number. See MV_XOR_CHANNEL enumerator.
|
||||
* xor_type - One of three: XOR, CRC32 and DMA operations.
|
||||
* xor_chain_ptr - address of chain pointer
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURS:
|
||||
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
|
||||
*
|
||||
*/
|
||||
int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* Parameter checking */
|
||||
if (chan >= MV_XOR_MAX_CHAN) {
|
||||
debug("%s: ERR. Invalid chan num %d\n", __func__, chan);
|
||||
return MV_BAD_PARAM;
|
||||
}
|
||||
|
||||
if (MV_ACTIVE == mv_xor_state_get(chan)) {
|
||||
debug("%s: ERR. Channel is already active\n", __func__);
|
||||
return MV_BUSY;
|
||||
}
|
||||
|
||||
if (0x0 == xor_chain_ptr) {
|
||||
debug("%s: ERR. xor_chain_ptr is NULL pointer\n", __func__);
|
||||
return MV_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* Read configuration register and mask the operation mode field */
|
||||
tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
|
||||
tmp &= ~XEXCR_OPERATION_MODE_MASK;
|
||||
|
||||
switch (xor_type) {
|
||||
case MV_XOR:
|
||||
if (0 != (xor_chain_ptr & XEXDPR_DST_PTR_XOR_MASK)) {
|
||||
debug("%s: ERR. Invalid chain pointer (bits [5:0] must be cleared)\n",
|
||||
__func__);
|
||||
return MV_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* Set the operation mode to XOR */
|
||||
tmp |= XEXCR_OPERATION_MODE_XOR;
|
||||
break;
|
||||
|
||||
case MV_DMA:
|
||||
if (0 != (xor_chain_ptr & XEXDPR_DST_PTR_DMA_MASK)) {
|
||||
debug("%s: ERR. Invalid chain pointer (bits [4:0] must be cleared)\n",
|
||||
__func__);
|
||||
return MV_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* Set the operation mode to DMA */
|
||||
tmp |= XEXCR_OPERATION_MODE_DMA;
|
||||
break;
|
||||
|
||||
case MV_CRC32:
|
||||
if (0 != (xor_chain_ptr & XEXDPR_DST_PTR_CRC_MASK)) {
|
||||
debug("%s: ERR. Invalid chain pointer (bits [4:0] must be cleared)\n",
|
||||
__func__);
|
||||
return MV_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* Set the operation mode to CRC32 */
|
||||
tmp |= XEXCR_OPERATION_MODE_CRC;
|
||||
break;
|
||||
|
||||
default:
|
||||
return MV_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* Write the operation mode to the register */
|
||||
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), tmp);
|
||||
|
||||
/*
|
||||
* Update the NextDescPtr field in the XOR Engine [0..1] Next Descriptor
|
||||
* Pointer Register (XExNDPR)
|
||||
*/
|
||||
reg_write(XOR_NEXT_DESC_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
|
||||
xor_chain_ptr);
|
||||
|
||||
/* Start transfer */
|
||||
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
|
||||
XEXACTR_XESTART_MASK);
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* mv_xor_state_get - Get XOR channel state.
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* XOR channel activity state can be active, idle, paused.
|
||||
* This function retrunes the channel activity state.
|
||||
*
|
||||
* INPUT:
|
||||
* chan - the channel number
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* XOR_CHANNEL_IDLE - If the engine is idle.
|
||||
* XOR_CHANNEL_ACTIVE - If the engine is busy.
|
||||
* XOR_CHANNEL_PAUSED - If the engine is paused.
|
||||
* MV_UNDEFINED_STATE - If the engine state is undefind or there is no
|
||||
* such engine
|
||||
*
|
||||
*/
|
||||
int mv_xor_state_get(u32 chan)
|
||||
{
|
||||
u32 state;
|
||||
|
||||
/* Parameter checking */
|
||||
if (chan >= MV_XOR_MAX_CHAN) {
|
||||
debug("%s: ERR. Invalid chan num %d\n", __func__, chan);
|
||||
return MV_UNDEFINED_STATE;
|
||||
}
|
||||
|
||||
/* Read the current state */
|
||||
state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
|
||||
state &= XEXACTR_XESTATUS_MASK;
|
||||
|
||||
/* Return the state */
|
||||
switch (state) {
|
||||
case XEXACTR_XESTATUS_IDLE:
|
||||
return MV_IDLE;
|
||||
case XEXACTR_XESTATUS_ACTIVE:
|
||||
return MV_ACTIVE;
|
||||
case XEXACTR_XESTATUS_PAUSED:
|
||||
return MV_PAUSED;
|
||||
}
|
||||
|
||||
return MV_UNDEFINED_STATE;
|
||||
}
|
||||
|
||||
/*
|
||||
* mv_xor_cmd_set - Set command of XOR channel
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* XOR channel can be started, idle, paused and restarted.
|
||||
* Paused can be set only if channel is active.
|
||||
* Start can be set only if channel is idle or paused.
|
||||
* Restart can be set only if channel is paused.
|
||||
* Stop can be set only if channel is active.
|
||||
*
|
||||
* INPUT:
|
||||
* chan - The channel number
|
||||
* command - The command type (start, stop, restart, pause)
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* MV_OK on success , MV_BAD_PARAM on erroneous parameter, MV_ERROR on
|
||||
* undefind XOR engine mode
|
||||
*
|
||||
*/
|
||||
static int mv_xor_cmd_set(u32 chan, int command)
|
||||
{
|
||||
int state;
|
||||
|
||||
/* Parameter checking */
|
||||
if (chan >= MV_XOR_MAX_CHAN) {
|
||||
debug("%s: ERR. Invalid chan num %d\n", __func__, chan);
|
||||
return MV_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* Get the current state */
|
||||
state = mv_xor_state_get(chan);
|
||||
|
||||
/* Command is start and current state is idle */
|
||||
if ((command == MV_START) && (state == MV_IDLE)) {
|
||||
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
|
||||
XEXACTR_XESTART_MASK);
|
||||
return MV_OK;
|
||||
}
|
||||
/* Command is stop and current state is active */
|
||||
else if ((command == MV_STOP) && (state == MV_ACTIVE)) {
|
||||
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
|
||||
XEXACTR_XESTOP_MASK);
|
||||
return MV_OK;
|
||||
}
|
||||
/* Command is paused and current state is active */
|
||||
else if ((command == MV_PAUSED) && (state == MV_ACTIVE)) {
|
||||
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
|
||||
XEXACTR_XEPAUSE_MASK);
|
||||
return MV_OK;
|
||||
}
|
||||
/* Command is restart and current state is paused */
|
||||
else if ((command == MV_RESTART) && (state == MV_PAUSED)) {
|
||||
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
|
||||
XEXACTR_XERESTART_MASK);
|
||||
return MV_OK;
|
||||
}
|
||||
/* Command is stop and current state is active */
|
||||
else if ((command == MV_STOP) && (state == MV_IDLE))
|
||||
return MV_OK;
|
||||
|
||||
/* Illegal command */
|
||||
debug("%s: ERR. Illegal command\n", __func__);
|
||||
|
||||
return MV_BAD_PARAM;
|
||||
}
|
||||
70
drivers/ddr/mvebu/xor.h
Normal file
70
drivers/ddr/mvebu/xor.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __XOR_H
|
||||
#define __XOR_H
|
||||
|
||||
#include "ddr3_hw_training.h"
|
||||
|
||||
#define MV_XOR_MAX_CHAN 4 /* total channels for all units together */
|
||||
|
||||
/*
|
||||
* This enumerator describes the type of functionality the XOR channel
|
||||
* can have while using the same data structures.
|
||||
*/
|
||||
enum xor_type {
|
||||
MV_XOR, /* XOR channel functions as XOR accelerator */
|
||||
MV_DMA, /* XOR channel functions as IDMA channel */
|
||||
MV_CRC32 /* XOR channel functions as CRC 32 calculator */
|
||||
};
|
||||
|
||||
/*
|
||||
* This enumerator describes the set of commands that can be applied on
|
||||
* an engine (e.g. IDMA, XOR). Appling a comman depends on the current
|
||||
* status (see MV_STATE enumerator)
|
||||
* Start can be applied only when status is IDLE
|
||||
* Stop can be applied only when status is IDLE, ACTIVE or PAUSED
|
||||
* Pause can be applied only when status is ACTIVE
|
||||
* Restart can be applied only when status is PAUSED
|
||||
*/
|
||||
enum mv_command {
|
||||
MV_START, /* Start */
|
||||
MV_STOP, /* Stop */
|
||||
MV_PAUSE, /* Pause */
|
||||
MV_RESTART /* Restart */
|
||||
};
|
||||
|
||||
/*
|
||||
* This enumerator describes the set of state conditions.
|
||||
* Moving from one state to other is stricted.
|
||||
*/
|
||||
enum mv_state {
|
||||
MV_IDLE,
|
||||
MV_ACTIVE,
|
||||
MV_PAUSED,
|
||||
MV_UNDEFINED_STATE
|
||||
};
|
||||
|
||||
/* XOR descriptor structure for CRC and DMA descriptor */
|
||||
struct crc_dma_desc {
|
||||
u32 status; /* Successful descriptor execution indication */
|
||||
u32 crc32_result; /* Result of CRC-32 calculation */
|
||||
u32 desc_cmd; /* type of operation to be carried out on the data */
|
||||
u32 next_desc_ptr; /* Next descriptor address pointer */
|
||||
u32 byte_cnt; /* Size of source block part represented by the descriptor */
|
||||
u32 dst_addr; /* Destination Block address pointer (not used in CRC32 */
|
||||
u32 src_addr0; /* Mode: Source Block address pointer */
|
||||
u32 src_addr1; /* Mode: Source Block address pointer */
|
||||
} __packed;
|
||||
|
||||
int mv_xor_state_get(u32 chan);
|
||||
void mv_sys_xor_init(MV_DRAM_INFO *dram_info);
|
||||
void mv_sys_xor_finish(void);
|
||||
int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr);
|
||||
int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
|
||||
u32 init_val_low);
|
||||
|
||||
#endif /* __XOR_H */
|
||||
103
drivers/ddr/mvebu/xor_regs.h
Normal file
103
drivers/ddr/mvebu/xor_regs.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __XOR_REGS_H
|
||||
#define __XOR_REGS_H
|
||||
|
||||
/*
|
||||
* For controllers that have two XOR units, then chans 2 & 3 will be mapped
|
||||
* to channels 0 & 1 of unit 1
|
||||
*/
|
||||
#define XOR_UNIT(chan) ((chan) >> 1)
|
||||
#define XOR_CHAN(chan) ((chan) & 1)
|
||||
|
||||
#define MV_XOR_REGS_OFFSET(unit) (0x60900)
|
||||
#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
|
||||
|
||||
/* XOR Engine Control Register Map */
|
||||
#define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit))
|
||||
#define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4)))
|
||||
#define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4)))
|
||||
|
||||
/* XOR Engine Interrupt Register Map */
|
||||
#define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30)
|
||||
#define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40)
|
||||
#define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50)
|
||||
#define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60)
|
||||
|
||||
/* XOR Engine Descriptor Register Map */
|
||||
#define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4)))
|
||||
#define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4)))
|
||||
#define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4)))
|
||||
|
||||
#define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4)))
|
||||
#define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4)))
|
||||
#define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D0)
|
||||
#define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D4)
|
||||
#define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D8)
|
||||
#define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E0)
|
||||
#define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E4)
|
||||
|
||||
/* XOR register fileds */
|
||||
|
||||
/* XOR Engine [0..1] Configuration Registers (XExCR) */
|
||||
#define XEXCR_OPERATION_MODE_OFFS (0)
|
||||
#define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS)
|
||||
#define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS)
|
||||
#define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS)
|
||||
#define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS)
|
||||
#define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS)
|
||||
#define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS)
|
||||
|
||||
#define XEXCR_SRC_BURST_LIMIT_OFFS (4)
|
||||
#define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS)
|
||||
#define XEXCR_DST_BURST_LIMIT_OFFS (8)
|
||||
#define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS)
|
||||
#define XEXCR_DRD_RES_SWP_OFFS (12)
|
||||
#define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS)
|
||||
#define XEXCR_DWR_REQ_SWP_OFFS (13)
|
||||
#define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS)
|
||||
#define XEXCR_DES_SWP_OFFS (14)
|
||||
#define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS)
|
||||
#define XEXCR_REG_ACC_PROTECT_OFFS (15)
|
||||
#define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS)
|
||||
|
||||
/* XOR Engine [0..1] Activation Registers (XExACTR) */
|
||||
#define XEXACTR_XESTART_OFFS (0)
|
||||
#define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS)
|
||||
#define XEXACTR_XESTOP_OFFS (1)
|
||||
#define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS)
|
||||
#define XEXACTR_XEPAUSE_OFFS (2)
|
||||
#define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS)
|
||||
#define XEXACTR_XERESTART_OFFS (3)
|
||||
#define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS)
|
||||
#define XEXACTR_XESTATUS_OFFS (4)
|
||||
#define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS)
|
||||
#define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS)
|
||||
#define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS)
|
||||
#define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS)
|
||||
|
||||
/* XOR Engine [0..1] Destination Pointer Register (XExDPR0) */
|
||||
#define XEXDPR_DST_PTR_OFFS (0)
|
||||
#define XEXDPR_DST_PTR_MASK (0xFFFFFFFF << XEXDPR_DST_PTR_OFFS)
|
||||
#define XEXDPR_DST_PTR_XOR_MASK (0x3F)
|
||||
#define XEXDPR_DST_PTR_DMA_MASK (0x1F)
|
||||
#define XEXDPR_DST_PTR_CRC_MASK (0x1F)
|
||||
|
||||
/* XOR Engine[0..1] Block Size Registers (XExBSR) */
|
||||
#define XEXBSR_BLOCK_SIZE_OFFS (0)
|
||||
#define XEXBSR_BLOCK_SIZE_MASK (0xFFFFFFFF << XEXBSR_BLOCK_SIZE_OFFS)
|
||||
#define XEXBSR_BLOCK_SIZE_MIN_VALUE (128)
|
||||
#define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xFFFFFFFF)
|
||||
|
||||
/* XOR Engine Address Decoding Register Map */
|
||||
#define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4)))
|
||||
#define XOR_BASE_ADDR_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x250 + ((win) * 4)))
|
||||
#define XOR_SIZE_MASK_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x270 + ((win) * 4)))
|
||||
#define XOR_HIGH_ADDR_REMAP_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x290 + ((win) * 4)))
|
||||
#define XOR_ADDR_OVRD_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x2A0 + ((win) * 4)))
|
||||
|
||||
#endif /* __XOR_REGS_H */
|
||||
|
|
@ -11,6 +11,8 @@
|
|||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARMADA_XP /* SOC Family Name */
|
||||
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
|
@ -65,4 +67,51 @@
|
|||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Memory layout while starting into the bin_hdr via the
|
||||
* BootROM:
|
||||
*
|
||||
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
|
||||
* 0x4000.4030 bin_hdr start address
|
||||
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
|
||||
* 0x4007.fffc BootROM stack top
|
||||
*
|
||||
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
|
||||
* L2 cache thus cannot be used.
|
||||
*/
|
||||
|
||||
/* SPL */
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40004030
|
||||
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
||||
|
||||
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
|
||||
CONFIG_SPL_BSS_MAX_SIZE)
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
|
||||
|
||||
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
||||
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
|
||||
|
||||
/* SPL related SPI defines */
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SPL_SPI_BUS 0
|
||||
#define CONFIG_SPL_SPI_CS 0
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
|
||||
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
|
||||
#define CONFIG_SYS_MVEBU_DDR
|
||||
#define CONFIG_SPD_EEPROM 0x4e
|
||||
|
||||
#endif /* _CONFIG_DB_MV7846MP_GP_H */
|
||||
|
|
|
|||
|
|
@ -43,6 +43,8 @@
|
|||
#define CONFIG_SF_DEFAULT_SPEED 1000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
|
||||
/* Environment in SPI NOR flash */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
|
|
@ -65,4 +67,51 @@
|
|||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Memory layout while starting into the bin_hdr via the
|
||||
* BootROM:
|
||||
*
|
||||
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
|
||||
* 0x4000.4030 bin_hdr start address
|
||||
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
|
||||
* 0x4007.fffc BootROM stack top
|
||||
*
|
||||
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
|
||||
* L2 cache thus cannot be used.
|
||||
*/
|
||||
|
||||
/* SPL */
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40004030
|
||||
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
||||
|
||||
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
|
||||
CONFIG_SPL_BSS_MAX_SIZE)
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
|
||||
|
||||
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
||||
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
|
||||
|
||||
/* SPL related SPI defines */
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SPL_SPI_BUS 0
|
||||
#define CONFIG_SPL_SPI_CS 0
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
|
||||
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
|
||||
#define CONFIG_SYS_MVEBU_DDR
|
||||
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
|
||||
|
||||
#endif /* _CONFIG_DB_MV7846MP_GP_H */
|
||||
|
|
|
|||
|
|
@ -32,6 +32,11 @@
|
|||
#define CONFIG_LZMA
|
||||
#define CONFIG_LZO
|
||||
|
||||
/*
|
||||
* Enable device tree support
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
|
@ -51,6 +56,7 @@
|
|||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
|
|
@ -141,6 +147,5 @@
|
|||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_LZO
|
||||
|
||||
#endif /* _CONFIG_SHEEVAPLUG_H */
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/
|
|||
libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
|
||||
libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
|
||||
libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
|
||||
libs-$(CONFIG_SYS_MVEBU_DDR) += drivers/ddr/mvebu/
|
||||
libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
|
||||
libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
|
||||
libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include <image.h>
|
||||
#include <stdint.h>
|
||||
#include "kwbimage.h"
|
||||
#include <config.h>
|
||||
|
||||
#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
|
||||
|
||||
|
|
@ -868,6 +869,16 @@ static int kwbimage_generate(struct image_tool_params *params,
|
|||
sizeof(struct ext_hdr_v0);
|
||||
} else {
|
||||
alloc_len = image_headersz_v1(params, NULL);
|
||||
#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
|
||||
if (alloc_len > CONFIG_SYS_SPI_U_BOOT_OFFS) {
|
||||
fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n");
|
||||
fprintf(stderr, "header=0x%x CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n",
|
||||
alloc_len, CONFIG_SYS_SPI_U_BOOT_OFFS);
|
||||
fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n");
|
||||
} else {
|
||||
alloc_len = CONFIG_SYS_SPI_U_BOOT_OFFS;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
hdr = malloc(alloc_len);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user