arm: socfpga: arria10: Add qts-filter for Arria10 socfpga
Add a script to process HPS handoff data and generate a header for inclusion in u-boot specific devicetree addons. The header should be included in the top level of u-boot.dtsi. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Dalon Westergreen
Ley Foon Tan
parent
5bbeaaefec
commit
5c0adb0a71
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@ -0,0 +1,141 @@
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#!/bin/bash
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#
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# helper function to convert from DOS to Unix, if necessary, and handle
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# lines ending in '\'.
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#
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fix_newlines_in_macros() {
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sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
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}
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#filter out only what we need from a10 hps.xml
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grep_a10_hps_config() {
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egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER"
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}
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#
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# Process hps.xml
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# $1: hps.xml
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# $2: Output File
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#
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process_a10_hps_config() {
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hps_xml="$1"
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outfile="$2"
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(cat << EOF
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Intel Arria 10 SoCFPGA configuration
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*/
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#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
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#define __SOCFPGA_ARRIA10_CONFIG_H__
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EOF
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echo "/* Clocks */"
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fix_newlines_in_macros \
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${hps_xml} | egrep "clk_hz" |
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awk -F"'" '{ gsub("\\.","_",$2) ; \
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print "#define" " " toupper($2) " " $4}' |
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sed 's/\.[0-9]//' |
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sed 's/I_CLK_MGR_//' |
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sort
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fix_newlines_in_macros \
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${hps_xml} | egrep "i_clk_mgr_mainpll" |
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awk -F"'" '{ gsub("\\.","_",$2) ; \
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print "#define" " " toupper($2) " " $4}' |
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sed 's/\.[0-9]//' |
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sed 's/I_CLK_MGR_//' |
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sort
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fix_newlines_in_macros \
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${hps_xml} | egrep "i_clk_mgr_perpll" |
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awk -F"'" '{ gsub("\\.","_",$2) ; \
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print "#define" " " toupper($2) " " $4}' |
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sed 's/\.[0-9]//' |
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sed 's/I_CLK_MGR_//' |
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sort
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fix_newlines_in_macros \
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${hps_xml} | egrep "i_clk_mgr_clkmgr" |
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awk -F"'" '{ gsub("\\.","_",$2) ; \
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print "#define" " " toupper($2) " " $4}' |
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sed 's/\.[0-9]//' |
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sed 's/I_CLK_MGR_//' |
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sort
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fix_newlines_in_macros \
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${hps_xml} | egrep "i_clk_mgr_alteragrp" |
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awk -F"'" '{ gsub("\\.","_",$2) ; \
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print "#define" " " toupper($2) " " $4}' |
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sed 's/\.[0-9]//' |
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sed 's/I_CLK_MGR_//' |
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sort
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echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\"
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echo " (ALTERAGRP_MPUCLK_MAINCNT))"
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echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\"
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echo " (ALTERAGRP_NOCCLK_MAINCNT))"
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echo
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echo "/* Pin Mux Configuration */"
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fix_newlines_in_macros \
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${hps_xml} | egrep "i_io48_pin_mux" |
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awk -F"'" '{ gsub("\\.","_",$2) ; \
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print "#define" " " toupper($2) " " $4}' |
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sed 's/I_IO48_PIN_MUX_//' |
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sed 's/SHARED_3V_IO_GRP_//' |
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sed 's/FPGA_INTERFACE_GRP_//' |
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sed 's/DEDICATED_IO_GRP_//' |
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sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
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sort
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echo
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echo "/* Bridge Configuration */"
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fix_newlines_in_macros \
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${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" |
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awk -F"'" '{ gsub("\\.","_",$2) ; \
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print "#define" " " toupper($2) " " $4}' |
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sed 's/true/1/' |
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sed 's/false/0/' |
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sort
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echo
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echo "/* Voltage Select for Config IO */"
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echo "#define CONFIG_IO_BANK_VSEL \\"
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echo " (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
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echo " (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
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echo
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echo "/* Macro for Config IO bit mapping */"
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echo -n "#define CONFIG_IO_MACRO(NAME) "
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echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
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echo " ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
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echo " ((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
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echo " ((NAME ## _PU_SLW_RT & 0x1) << 13) | \\"
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echo " ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\"
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echo " ((NAME ## _PD_SLW_RT & 0x1) << 5) | \\"
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echo " (NAME ## _PD_DRV_STRG & 0x1f))"
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cat << EOF
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#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
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EOF
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) > "${outfile}"
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}
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usage() {
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echo "$0 [hps_xml] [output_file]"
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echo "Process QTS-generated hps.xml into devicetree header."
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echo ""
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echo " hps_xml - hps.xml file from hps_isw_handoff"
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echo " output_file - Output header file for dtsi include"
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echo ""
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}
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hps_xml="$1"
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outfile="$2"
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if [ "$#" -ne 2 ] ; then
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usage
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exit 1
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fi
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process_a10_hps_config "${hps_xml}" "${outfile}"
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@ -16,9 +16,9 @@ controller support within SOCFPGA
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
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-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
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--------------------------------------------------
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Generating the handoff header files for U-Boot SPL
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--------------------------------------------------
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---------------------------------------------------------------------
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Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
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---------------------------------------------------------------------
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This text is assuming quartus 16.1, but newer versions will probably work just fine too;
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verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
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@ -32,7 +32,7 @@ Rebuilding your Quartus project
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Choose one of the follwing methods, either command line or GUI.
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Using the comaand line
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Using the command line
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~~~~~~~~~~~~~~~~~~~~~~
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First run the embedded command shell, using your path to the Quartus install:
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@ -147,3 +147,32 @@ Note: file sizes will differ slightly depending on the selected board.
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Now your board is ready for full mainline support including U-Boot SPL.
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The Preloader will not be needed any more.
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----------------------------------------------------------
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Arria 10 generating the handoff header files for U-Boot SPL
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----------------------------------------------------------
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A header file for inclusion in a devicetree for Arria10 can be generated
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by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml
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file generated during the FPGA project compilation. The header contains
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all PLL, clock, pinmux, and bridge configurations required.
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Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example
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that includes use of the generated handoff header.
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Devicetree header generation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The qts-filter-a10.sh script can process the compile time genetated hps.xml
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to create the appropriate devicetree header.
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$ ./arch/arm/mach-socfpga/qts-filter-a10.sh \
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<hps_xml> \
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<output_file>
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hps_xml - hps_isw_handoff/hps.xml from Quartus project
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output_file - Output filename and location for header file
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The script generates a single header file names <output_file> that should
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be placed in arch/arm/dts.
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