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mx6sx: Adjust enable_fec_anatop_clock() for mx6solox
Configure and enable the ethernet clock for mx6solox. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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@ -373,6 +373,27 @@ int enable_fec_anatop_clock(enum enet_freq freq)
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reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
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reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
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writel(reg, &anatop->pll_enet);
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writel(reg, &anatop->pll_enet);
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#ifdef CONFIG_MX6SX
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/*
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* Set enet ahb clock to 200MHz
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* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
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*/
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reg = readl(&imx_ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
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| MXC_CCM_CHSCCDR_ENET_PODF_MASK
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| MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
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/* PLL2 PFD2 */
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reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
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/* Div = 2*/
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reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
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reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
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writel(reg, &imx_ccm->chsccdr);
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/* Enable enet system clock */
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reg = readl(&imx_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_ENET_MASK;
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writel(reg, &imx_ccm->CCGR3);
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#endif
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return 0;
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return 0;
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}
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}
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#endif
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#endif
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