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powerpc/doc: Update the README.srio-pcie-boot-corenet
1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet file when the tabs are set to 8 characters. And the standard for u-boot should be 8 character tabs! So this issue should be amended. 2. Add a NOTE for the ENV parameters of the Slave. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@ -21,13 +21,13 @@ Environment of the SRIO or PCIE boot:
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e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
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e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
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the boot location to SRIO or PCIE, and holdoff all the cores.
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the boot location to SRIO or PCIE, and holdoff all the cores.
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---------- ----------- -----------
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----------- ----------- -----------
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| | | | | |
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| NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
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| NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
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| | | |<===========>| |
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| | | |<===========>| |
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---------- ----------- -----------
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----------- ----------- -----------
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The example based on P4080DS platform:
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The example based on P4080DS platform:
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Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
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Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
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@ -110,3 +110,9 @@ How to use this feature:
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4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
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4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
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or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
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or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
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perform the role as a master for boot from SRIO or PCIE.
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perform the role as a master for boot from SRIO or PCIE.
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NOTE: When the Slave's ENV parameters are stored in Master's NorFlash,
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it can fetch them through PCIE or SRIO interface. But the ENV
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parameters can not be modified by "saveenv" or other commands under
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the Slave's u-boot environment, because the Slave can not erase,
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write Master's NorFlash by PCIE or SRIO link.
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