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https://github.com/brain-hackers/u-boot-brain
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Socrates: Added FPGA mapping. LAWs and TLBs cleanup.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
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@ -33,13 +33,12 @@
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x0000_0000 0x2fff_ffff DDR 512M
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xc000_0000 0xdfff_ffff RapidIO 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xc000_0000 0xc00f_ffff FPGA 1M
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* 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR)
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xf800_0000 0xf80f_ffff BCSR 1M
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* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
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* 0xfc00_0000 0xffff_ffff FLASH 64M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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@ -49,9 +48,11 @@
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struct law_entry law_table[] = {
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SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
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SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
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SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
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SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
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SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
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SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
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#if defined(CFG_FPGA_BASE)
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SET_LAW_ENTRY(5, CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -37,6 +37,9 @@
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#include <fdt_support.h>
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#include <asm/io.h>
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#if defined(CFG_FPGA_BASE)
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#include "upm_table.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[]; /* FLASH chips info */
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@ -76,7 +79,10 @@ int checkboard (void)
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* Initialize local bus.
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*/
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local_bus_init ();
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#if defined(CFG_FPGA_BASE)
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/* Init UPMA for FPGA access */
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upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
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#endif
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return 0;
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}
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@ -46,16 +46,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
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/*
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* TLB 0, 1: 128M Non-cacheable, guarded
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* 0xf8000000 128M FLASH
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* TLB 0: 64M Non-cacheable, guarded
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* 0xfc000000 64M FLASH
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_64M, 1),
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SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 2: 256M Non-cacheable, guarded
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@ -73,21 +70,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_256M, 1),
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#if defined(CFG_FPGA_BASE)
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/*
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* TLB 4: 256M Non-cacheable, guarded
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* 0xc0000000 256M Rapid IO MEM First half
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* TLB 4: 1M Non-cacheable, guarded
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* 0xc0000000 1M FPGA and NAND
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*/
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SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
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SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 5: 256M Non-cacheable, guarded
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* 0xd0000000 256M Rapid IO MEM Second half
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*/
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SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256M, 1),
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0, 4, BOOKE_PAGESZ_1M, 1),
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#endif
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/*
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* TLB 6: 64M Non-cacheable, guarded
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@ -216,11 +216,6 @@
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#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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/* RapidIO MMU */
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#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
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#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
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#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
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/*
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* General PCI
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* Memory space is mapped 1-1.
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@ -414,4 +409,8 @@
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_USB_STORAGE 1
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/* FPGA and NAND */
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#define CFG_FPGA_BASE 0xc0000000
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#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
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#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */
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#endif /* __CONFIG_H */
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