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https://github.com/brain-hackers/u-boot-brain
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spi: add config option to enable the WP pin function on st micron flashes
enable the W#/Vpp signal to disable writing to the status register on ST MICRON flashes like the N25Q128 thorugh the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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11
README
11
README
@ -2930,6 +2930,17 @@ CBFS (Coreboot Filesystem) support
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memories can be connected with a given cs line.
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memories can be connected with a given cs line.
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currently Xilinx Zynq qspi support these type of connections.
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currently Xilinx Zynq qspi support these type of connections.
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CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
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enable the W#/Vpp signal to disable writing to the status
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register on ST MICRON flashes like the N25Q128.
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The status register write enable/disable bit, combined with
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the W#/VPP signal provides hardware data protection for the
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device as follows: When the enable/disable bit is set to 1,
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and the W#/VPP signal is driven LOW, the status register
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nonvolatile bits become read-only and the WRITE STATUS REGISTER
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operation will not execute. The only way to exit this
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hardware-protected mode is to drive W#/VPP HIGH.
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- SystemACE Support:
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- SystemACE Support:
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CONFIG_SYSTEMACE
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CONFIG_SYSTEMACE
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@ -60,6 +60,10 @@
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#define STATUS_QEB_MXIC (1 << 6)
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#define STATUS_QEB_MXIC (1 << 6)
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#define STATUS_PEC (1 << 7)
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#define STATUS_PEC (1 << 7)
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#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
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#define STATUS_SRWD (1 << 7) /* SR write protect */
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#endif
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/* Flash timeout values */
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/* Flash timeout values */
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#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
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#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
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#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
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#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
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@ -281,6 +281,34 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
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}
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}
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#endif /* CONFIG_OF_CONTROL */
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#endif /* CONFIG_OF_CONTROL */
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#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
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/* enable the W#/Vpp signal to disable writing to the status register */
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static int spi_enable_wp_pin(struct spi_flash *flash)
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{
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u8 status;
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int ret;
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ret = spi_flash_cmd_read_status(flash, &status);
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if (ret < 0)
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return ret;
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ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
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if (ret < 0)
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return ret;
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ret = spi_flash_cmd_write_disable(flash);
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if (ret < 0)
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return ret;
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return 0;
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}
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#else
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static int spi_enable_wp_pin(struct spi_flash *flash)
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{
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return 0;
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}
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#endif
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static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
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static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
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{
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{
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struct spi_flash *flash = NULL;
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struct spi_flash *flash = NULL;
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@ -351,6 +379,8 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
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puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
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puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
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}
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}
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#endif
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#endif
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if (spi_enable_wp_pin(flash))
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puts("Enable WP pin failed\n");
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/* Release spi bus */
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/* Release spi bus */
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spi_release_bus(spi);
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spi_release_bus(spi);
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