mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-30 08:30:50 +09:00
ColdFire: MCF52x2 Header files update
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew
John Rigby
parent
83ec20bc43
commit
56115665b4
@ -121,6 +121,41 @@ struct fec_info_s {
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/* Register read/write struct */
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typedef struct fec {
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#ifdef CONFIG_M5272
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u32 ecr; /* 0x00 */
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u32 eir; /* 0x04 */
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u32 eimr; /* 0x08 */
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u32 ivsr; /* 0x0C */
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u32 rdar; /* 0x10 */
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u32 tdar; /* 0x14 */
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u8 resv1[0x28]; /* 0x18 */
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u32 mmfr; /* 0x40 */
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u32 mscr; /* 0x44 */
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u8 resv2[0x44]; /* 0x48 */
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u32 frbr; /* 0x8C */
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u32 frsr; /* 0x90 */
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u8 resv3[0x10]; /* 0x94 */
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u32 tfwr; /* 0xA4 */
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u32 res4; /* 0xA8 */
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u32 tfsr; /* 0xAC */
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u8 resv4[0x50]; /* 0xB0 */
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u32 opd; /* 0x100 - dummy */
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u32 rcr; /* 0x104 */
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u32 mibc; /* 0x108 */
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u8 resv5[0x38]; /* 0x10C */
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u32 tcr; /* 0x144 */
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u8 resv6[0x270]; /* 0x148 */
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u32 iaur; /* 0x3B8 - dummy */
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u32 ialr; /* 0x3BC - dummy */
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u32 palr; /* 0x3C0 */
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u32 paur; /* 0x3C4 */
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u32 gaur; /* 0x3C8 */
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u32 galr; /* 0x3CC */
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u32 erdsr; /* 0x3D0 */
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u32 etdsr; /* 0x3D4 */
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u32 emrbr; /* 0x3D8 */
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u8 resv12[0x74]; /* 0x18C */
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#else
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u8 resv0[0x4];
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u32 eir;
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u32 eimr;
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@ -157,6 +192,7 @@ typedef struct fec {
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u32 etdsr;
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u32 emrbr;
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u8 resv12[0x74];
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#endif
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u32 rmon_t_drop;
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u32 rmon_t_packets;
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@ -26,6 +26,97 @@
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#ifndef __IMMAP_H
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#define __IMMAP_H
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#ifdef CONFIG_M5249
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#include <asm/immap_5249.h>
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#include <asm/m5249.h>
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC)
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#define CFG_NUM_IRQS (64)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR1)
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#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
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#define CFG_TMRINTR_NO (31)
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#define CFG_TMRINTR_MASK (0x00000400)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5249 */
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#ifdef CONFIG_M5271
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#include <asm/immap_5271.h>
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#include <asm/m5271.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR3)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
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#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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#endif /* CONFIG_M5271 */
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#ifdef CONFIG_M5272
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#include <asm/immap_5272.h>
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#include <asm/m5272.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC)
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#define CFG_NUM_IRQS (64)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_TMR0)
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#define CFG_TMR_BASE (MMAP_TMR3)
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#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
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#define CFG_TMRINTR_NO (INT_TMR3)
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#define CFG_TMRINTR_MASK (INT_ISR_INT24)
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#define CFG_TMRINTR_PEND (0)
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#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5272 */
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#ifdef CONFIG_M5282
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#include <asm/immap_5282.h>
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#include <asm/m5282.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (128)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR3)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
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#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5282 */
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#ifdef CONFIG_M5329
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#include <asm/immap_5329.h>
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#include <asm/m5329.h>
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@ -25,19 +25,11 @@
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#ifndef __IMMAP_5249__
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#define __IMMAP_5249__
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/* Timer module registers
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*/
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typedef struct timer_ctrl {
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ushort timer_tmr;
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ushort res1;
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ushort timer_trr;
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ushort res2;
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ushort timer_tcap;
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ushort res3;
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ushort timer_tcn;
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ushort res4;
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ushort timer_ter;
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uchar res5[14];
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} timer_t;
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#define MMAP_INTC (CFG_MBAR + 0x00000040)
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
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#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
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#define MMAP_UART1 (CFG_MBAR + 0x00000200)
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#define MMAP_QSPI (CFG_MBAR + 0x00000400)
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#endif /* __IMMAP_5249__ */
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@ -26,73 +26,73 @@
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#ifndef __IMMAP_5271__
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#define __IMMAP_5271__
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/* Interrupt module registers
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*/
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typedef struct int_ctrl {
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uint int_icr1;
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uint int_icr2;
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uint int_icr3;
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uint int_icr4;
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uint int_isr;
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uint int_pitr;
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uint int_piwr;
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uchar res1[3];
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uchar int_pivr;
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} intctrl_t;
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#define MMAP_SCM (CFG_MBAR + 0x00000000)
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#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
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#define MMAP_FBCS (CFG_MBAR + 0x00000080)
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#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
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#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
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#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
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#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
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#define MMAP_UART0 (CFG_MBAR + 0x00000200)
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#define MMAP_UART1 (CFG_MBAR + 0x00000240)
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#define MMAP_UART2 (CFG_MBAR + 0x00000280)
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#define MMAP_I2C (CFG_MBAR + 0x00000300)
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#define MMAP_QSPI (CFG_MBAR + 0x00000340)
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
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#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
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#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
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#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
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#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
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#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
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#define MMAP_FEC (CFG_MBAR + 0x00001000)
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#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
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#define MMAP_GPIO (CFG_MBAR + 0x00100000)
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#define MMAP_CCM (CFG_MBAR + 0x00110000)
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#define MMAP_PLL (CFG_MBAR + 0x00120000)
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#define MMAP_EPORT (CFG_MBAR + 0x00130000)
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#define MMAP_WDOG (CFG_MBAR + 0x00140000)
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#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
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#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
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#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
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#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
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#define MMAP_MDHA (CFG_MBAR + 0x00190000)
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#define MMAP_RNG (CFG_MBAR + 0x001A0000)
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#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
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#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
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#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
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#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
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/* Timer module registers
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*/
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typedef struct timer_ctrl {
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ushort timer_tmr;
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ushort res1;
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ushort timer_trr;
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ushort res2;
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ushort timer_tcap;
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ushort res3;
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ushort timer_tcn;
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ushort res4;
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ushort timer_ter;
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uchar res5[14];
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} timer_t;
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/* Fast ethernet controller registers
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*/
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typedef struct fec {
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uint res1;
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uint fec_ievent;
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uint fec_imask;
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uint res2;
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uint fec_r_des_active;
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uint fec_x_des_active;
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uint res3[3];
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uint fec_ecntrl;
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uint res4[6];
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uint fec_mii_data;
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uint fec_mii_speed;
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uint res5[7];
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uint fec_mibc;
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uint res6[7];
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uint fec_r_cntrl;
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uint res7[15];
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uint fec_x_cntrl;
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uint res8[7];
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uint fec_addr_low;
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uint fec_addr_high;
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uint fec_opd;
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uint res9[10];
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uint fec_ihash_table_high;
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uint fec_ihash_table_low;
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uint fec_ghash_table_high;
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uint fec_ghash_table_low;
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uint res10[7];
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uint fec_tfwr;
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uint res11;
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uint fec_r_bound;
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uint fec_r_fstart;
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uint res12[11];
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uint fec_r_des_start;
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uint fec_x_des_start;
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uint fec_r_buff_size;
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} fec_t;
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/* Interrupt module registers */
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typedef struct int0_ctrl {
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/* Interrupt Controller 0 */
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u32 iprh0; /* 0x00 Pending Register High */
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u32 iprl0; /* 0x04 Pending Register Low */
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u32 imrh0; /* 0x08 Mask Register High */
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u32 imrl0; /* 0x0C Mask Register Low */
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u32 frch0; /* 0x10 Force Register High */
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u32 frcl0; /* 0x14 Force Register Low */
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u8 irlr; /* 0x18 */
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u8 iacklpr; /* 0x19 */
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u16 res1[19]; /* 0x1a - 0x3c */
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u8 icr0[64]; /* 0x40 - 0x7F Control registers */
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u32 res3[24]; /* 0x80 - 0xDF */
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u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
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u8 res4[3]; /* 0xE1 - 0xE3 */
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u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
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u8 res5[3]; /* 0xE5 - 0xE7 */
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u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
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u8 res6[3]; /* 0xE9 - 0xEB */
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u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
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u8 res7[3]; /* 0xED - 0xEF */
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u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
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u8 res8[3]; /* 0xF1 - 0xF3 */
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u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
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u8 res9[3]; /* 0xF5 - 0xF7 */
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u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
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u8 resa[3]; /* 0xF9 - 0xFB */
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u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
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u8 resb[3]; /* 0xFD - 0xFF */
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} int0_t;
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#endif /* __IMMAP_5271__ */
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@ -25,8 +25,26 @@
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#ifndef __IMMAP_5272__
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#define __IMMAP_5272__
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/* System configuration registers
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*/
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#define MMAP_CFG (CFG_MBAR + 0x00000000)
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#define MMAP_INTC (CFG_MBAR + 0x00000020)
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#define MMAP_FBCS (CFG_MBAR + 0x00000040)
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#define MMAP_GPIO (CFG_MBAR + 0x00000080)
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#define MMAP_QSPI (CFG_MBAR + 0x000000A0)
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#define MMAP_PWM (CFG_MBAR + 0x000000C0)
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#define MMAP_DMA0 (CFG_MBAR + 0x000000E0)
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#define MMAP_UART0 (CFG_MBAR + 0x00000100)
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#define MMAP_UART1 (CFG_MBAR + 0x00000140)
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#define MMAP_SDRAM (CFG_MBAR + 0x00000180)
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#define MMAP_TMR0 (CFG_MBAR + 0x00000200)
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#define MMAP_TMR1 (CFG_MBAR + 0x00000220)
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#define MMAP_TMR2 (CFG_MBAR + 0x00000240)
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#define MMAP_TMR3 (CFG_MBAR + 0x00000260)
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#define MMAP_WDOG (CFG_MBAR + 0x00000280)
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#define MMAP_PLIC (CFG_MBAR + 0x00000300)
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#define MMAP_FEC (CFG_MBAR + 0x00000840)
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#define MMAP_USB (CFG_MBAR + 0x00001000)
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/* System configuration registers */
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typedef struct sys_ctrl {
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uint sc_mbar;
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ushort sc_scr;
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@ -38,8 +56,7 @@ typedef struct sys_ctrl {
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char res2[12];
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} sysctrl_t;
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/* Interrupt module registers
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*/
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/* Interrupt module registers */
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typedef struct int_ctrl {
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uint int_icr1;
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uint int_icr2;
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@ -52,8 +69,7 @@ typedef struct int_ctrl {
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uchar int_pivr;
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} intctrl_t;
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/* Chip select module registers.
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*/
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/* Chip select module registers */
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typedef struct cs_ctlr {
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uint cs_br0;
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uint cs_or0;
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@ -73,8 +89,7 @@ typedef struct cs_ctlr {
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uint cs_or7;
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} csctrl_t;
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/* GPIO port registers
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*/
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/* GPIO port registers */
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typedef struct gpio_ctrl {
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uint gpio_pacnt;
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ushort gpio_paddr;
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@ -89,8 +104,7 @@ typedef struct gpio_ctrl {
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uchar res2[4];
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} gpio_t;
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/* QSPI module registers
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*/
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/* QSPI module registers */
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typedef struct qspi_ctrl {
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ushort qspi_qmr;
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uchar res1[2];
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@ -106,8 +120,7 @@ typedef struct qspi_ctrl {
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uchar res6[10];
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} qspi_t;
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/* PWM module registers
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*/
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/* PWM module registers */
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typedef struct pwm_ctrl {
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uchar pwm_pwcr0;
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uchar res1[3];
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@ -123,8 +136,7 @@ typedef struct pwm_ctrl {
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uchar res6[7];
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} pwm_t;
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/* DMA module registers
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*/
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/* DMA module registers */
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typedef struct dma_ctrl {
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ulong dma_dmr;
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uchar res1[2];
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@ -135,45 +147,7 @@ typedef struct dma_ctrl {
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uchar res2[12];
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} dma_t;
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/* UART module registers
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*/
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typedef struct uart_ctrl {
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uchar uart_umr;
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||||
uchar res1[3];
|
||||
uchar uart_usr_ucsr;
|
||||
uchar res2[3];
|
||||
uchar uart_ucr;
|
||||
uchar res3[3];
|
||||
uchar uart_urb_utb;
|
||||
uchar res4[3];
|
||||
uchar uart_uipcr_uacr;
|
||||
uchar res5[3];
|
||||
uchar uart_uisr_uimr;
|
||||
uchar res6[3];
|
||||
uchar uart_udu;
|
||||
uchar res7[3];
|
||||
uchar uart_udl;
|
||||
uchar res8[3];
|
||||
uchar uart_uabu;
|
||||
uchar res9[3];
|
||||
uchar uart_uabl;
|
||||
uchar res10[3];
|
||||
uchar uart_utf;
|
||||
uchar res11[3];
|
||||
uchar uart_urf;
|
||||
uchar res12[3];
|
||||
uchar uart_ufpd;
|
||||
uchar res13[3];
|
||||
uchar uart_uip;
|
||||
uchar res14[3];
|
||||
uchar uart_uop1;
|
||||
uchar res15[3];
|
||||
uchar uart_uop0;
|
||||
uchar res16[3];
|
||||
} uart_t;
|
||||
|
||||
/* SDRAM controller registers, offset: 0x180
|
||||
*/
|
||||
/* SDRAM controller registers, offset: 0x180 */
|
||||
typedef struct sdram_ctrl {
|
||||
uchar res1[2];
|
||||
ushort sdram_sdcr;
|
||||
@ -182,23 +156,7 @@ typedef struct sdram_ctrl {
|
||||
uchar res3[120];
|
||||
} sdramctrl_t;
|
||||
|
||||
/* Timer module registers
|
||||
*/
|
||||
typedef struct timer_ctrl {
|
||||
ushort timer_tmr;
|
||||
ushort res1;
|
||||
ushort timer_trr;
|
||||
ushort res2;
|
||||
ushort timer_tcap;
|
||||
ushort res3;
|
||||
ushort timer_tcn;
|
||||
ushort res4;
|
||||
ushort timer_ter;
|
||||
uchar res5[14];
|
||||
} timer_t;
|
||||
|
||||
/* Watchdog registers
|
||||
*/
|
||||
/* Watchdog registers */
|
||||
typedef struct wdog_ctrl {
|
||||
ushort wdog_wrrr;
|
||||
ushort res1;
|
||||
@ -210,8 +168,7 @@ typedef struct wdog_ctrl {
|
||||
uchar res4[114];
|
||||
} wdog_t;
|
||||
|
||||
/* PLIC module registers
|
||||
*/
|
||||
/* PLIC module registers */
|
||||
typedef struct plic_ctrl {
|
||||
ulong plic_p0b1rr;
|
||||
ulong plic_p1b1rr;
|
||||
@ -289,42 +246,7 @@ typedef struct plic_ctrl {
|
||||
uchar res10[1184];
|
||||
} plic_t;
|
||||
|
||||
/* Fast ethernet controller registers
|
||||
*/
|
||||
typedef struct fec {
|
||||
uint fec_ecntrl; /* ethernet control register */
|
||||
uint fec_ievent; /* interrupt event register */
|
||||
uint fec_imask; /* interrupt mask register */
|
||||
uint fec_ivec; /* interrupt level and vector status */
|
||||
uint fec_r_des_active; /* Rx ring updated flag */
|
||||
uint fec_x_des_active; /* Tx ring updated flag */
|
||||
uint res3[10]; /* reserved */
|
||||
uint fec_mii_data; /* MII data register */
|
||||
uint fec_mii_speed; /* MII speed control register */
|
||||
uint res4[17]; /* reserved */
|
||||
uint fec_r_bound; /* end of RAM (read-only) */
|
||||
uint fec_r_fstart; /* Rx FIFO start address */
|
||||
uint res5[6]; /* reserved */
|
||||
uint fec_x_fstart; /* Tx FIFO start address */
|
||||
uint res7[21]; /* reserved */
|
||||
uint fec_r_cntrl; /* Rx control register */
|
||||
uint fec_r_hash; /* Rx hash register */
|
||||
uint res8[14]; /* reserved */
|
||||
uint fec_x_cntrl; /* Tx control register */
|
||||
uint res9[0x9e]; /* reserved */
|
||||
uint fec_addr_low; /* lower 32 bits of station address */
|
||||
uint fec_addr_high; /* upper 16 bits of station address */
|
||||
uint fec_hash_table_high; /* upper 32-bits of hash table */
|
||||
uint fec_hash_table_low; /* lower 32-bits of hash table */
|
||||
uint fec_r_des_start; /* beginning of Rx descriptor ring */
|
||||
uint fec_x_des_start; /* beginning of Tx descriptor ring */
|
||||
uint fec_r_buff_size; /* Rx buffer size */
|
||||
uint res2[9]; /* reserved */
|
||||
uchar fec_fifo[960]; /* fifo RAM */
|
||||
} fec_t;
|
||||
|
||||
/* USB module registers
|
||||
*/
|
||||
/* USB module registers */
|
||||
typedef struct usb {
|
||||
ushort res1;
|
||||
ushort usb_fnr;
|
||||
@ -425,23 +347,4 @@ typedef struct usb {
|
||||
uchar usb_cfgram[1024];
|
||||
} usb_t;
|
||||
|
||||
/* Internal memory map.
|
||||
*/
|
||||
typedef struct immap {
|
||||
sysctrl_t sysctrl_reg; /* System configuration registers */
|
||||
intctrl_t intctrl_reg; /* Interrupt controller registers */
|
||||
csctrl_t csctrl_reg; /* Chip select controller registers */
|
||||
gpio_t gpio_reg; /* GPIO controller registers */
|
||||
qspi_t qspi_reg; /* QSPI controller registers */
|
||||
pwm_t pwm_reg; /* Pulse width modulation registers */
|
||||
dma_t dma_reg; /* DMA registers */
|
||||
uart_t uart_reg[2]; /* UART registers */
|
||||
sdramctrl_t sdram_reg; /* SDRAM controller registers */
|
||||
timer_t timer_reg[4]; /* Timer registers */
|
||||
wdog_t wdog_reg; /* Watchdog registers */
|
||||
plic_t plic_reg; /* Physical layer interface registers */
|
||||
fec_t fec_reg; /* Fast ethernet controller registers */
|
||||
usb_t usb_reg; /* USB controller registers */
|
||||
} immap_t;
|
||||
|
||||
#endif /* __IMMAP_5272__ */
|
||||
|
||||
@ -25,61 +25,168 @@
|
||||
#ifndef __IMMAP_5282__
|
||||
#define __IMMAP_5282__
|
||||
|
||||
struct sys_ctrl {
|
||||
uint ipsbar;
|
||||
char res1[4];
|
||||
uint rambar;
|
||||
char res2[4];
|
||||
uchar crsr;
|
||||
uchar cwcr;
|
||||
uchar lpicr;
|
||||
uchar cwsr;
|
||||
uint dmareqc;
|
||||
char res3[4];
|
||||
uint mpark;
|
||||
#define MMAP_SCM (CFG_MBAR + 0x00000000)
|
||||
#define MMAP_SDRAMC (CFG_MBAR + 0x00000040)
|
||||
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
|
||||
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
|
||||
#define MMAP_DMA1 (CFG_MBAR + 0x00000140)
|
||||
#define MMAP_DMA2 (CFG_MBAR + 0x00000180)
|
||||
#define MMAP_DMA3 (CFG_MBAR + 0x000001C0)
|
||||
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
|
||||
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
|
||||
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
|
||||
#define MMAP_I2C (CFG_MBAR + 0x00000300)
|
||||
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
|
||||
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
|
||||
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
|
||||
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
|
||||
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
|
||||
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
|
||||
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
|
||||
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
|
||||
#define MMAP_FEC (CFG_MBAR + 0x00001000)
|
||||
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
|
||||
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
|
||||
#define MMAP_CCM (CFG_MBAR + 0x00110000)
|
||||
#define MMAP_PLL (CFG_MBAR + 0x00120000)
|
||||
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
|
||||
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
|
||||
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
|
||||
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
|
||||
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
|
||||
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
|
||||
#define MMAP_QADC (CFG_MBAR + 0x00190000)
|
||||
#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000)
|
||||
#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000)
|
||||
#define MMAP_CAN (CFG_MBAR + 0x001C0000)
|
||||
#define MMAP_CFMC (CFG_MBAR + 0x001D0000)
|
||||
#define MMAP_CFMMEM (CFG_MBAR + 0x04000000)
|
||||
|
||||
/* TODO: finish these */
|
||||
};
|
||||
/* System Control Module */
|
||||
typedef struct scm_ctrl {
|
||||
u32 ipsbar;
|
||||
u32 res1;
|
||||
u32 rambar;
|
||||
u32 res2;
|
||||
u8 crsr;
|
||||
u8 cwcr;
|
||||
u8 lpicr;
|
||||
u8 cwsr;
|
||||
u32 res3;
|
||||
u8 mpark;
|
||||
u8 res4[3];
|
||||
u8 pacr0;
|
||||
u8 pacr1;
|
||||
u8 pacr2;
|
||||
u8 pacr3;
|
||||
u8 pacr4;
|
||||
u8 res5;
|
||||
u8 pacr5;
|
||||
u8 pacr6;
|
||||
u8 pacr7;
|
||||
u8 res6;
|
||||
u8 pacr8;
|
||||
u8 res7;
|
||||
u8 gpacr0;
|
||||
u8 gpacr1;
|
||||
u16 res8;
|
||||
} scm_t;
|
||||
|
||||
/* Fast ethernet controller registers
|
||||
*/
|
||||
typedef struct fec {
|
||||
uint res1; /* reserved 1000*/
|
||||
uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
|
||||
uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
|
||||
uint res2; /* reserved 100c*/
|
||||
uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
|
||||
uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
|
||||
uint res3[3]; /* reserved 1018*/
|
||||
uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
|
||||
uint res4[6]; /* reserved 1028*/
|
||||
uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
|
||||
uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
|
||||
/*1044*/
|
||||
uint res5[7]; /* reserved 1048*/
|
||||
uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
|
||||
uint res6[7]; /* reserved 1068*/
|
||||
uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
|
||||
uint res7[15]; /* reserved 1088*/
|
||||
uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
|
||||
uint res8[7]; /* reserved 10C8*/
|
||||
uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
|
||||
uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
|
||||
uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
|
||||
uint res9[10]; /* reserved 10F0*/
|
||||
uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */
|
||||
uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */
|
||||
uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */
|
||||
uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */
|
||||
uint res10[7]; /* reserved 1128*/
|
||||
uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
|
||||
uint res11; /* reserved 1148*/
|
||||
uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */
|
||||
uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */
|
||||
uint res12[11]; /* reserved 1154*/
|
||||
uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */
|
||||
uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */
|
||||
uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
|
||||
} fec_t;
|
||||
/* Flexbus module Chip select registers */
|
||||
typedef struct fbcs_ctrl {
|
||||
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
|
||||
u16 res0;
|
||||
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
|
||||
u16 res1; /* 0x08 */
|
||||
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
|
||||
|
||||
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
|
||||
u16 res2;
|
||||
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
|
||||
u16 res3; /* 0x14 */
|
||||
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
|
||||
|
||||
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
|
||||
u16 res4;
|
||||
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
|
||||
u16 res5; /* 0x20 */
|
||||
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
|
||||
|
||||
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
|
||||
u16 res6;
|
||||
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
|
||||
u16 res7; /* 0x2C */
|
||||
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
|
||||
|
||||
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
|
||||
u16 res8;
|
||||
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
|
||||
u16 res9; /* 0x38 */
|
||||
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
|
||||
|
||||
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
|
||||
u16 res10;
|
||||
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
|
||||
u16 res11; /* 0x44 */
|
||||
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
|
||||
|
||||
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
|
||||
u16 res12;
|
||||
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
|
||||
u16 res13; /* 0x50 */
|
||||
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
|
||||
|
||||
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
|
||||
u16 res14;
|
||||
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
|
||||
u16 res15; /* 0x5C */
|
||||
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
|
||||
} fbcs_t;
|
||||
|
||||
/* Interrupt module registers */
|
||||
typedef struct int0_ctrl {
|
||||
/* Interrupt Controller 0 */
|
||||
u32 iprh0; /* 0x00 Pending Register High */
|
||||
u32 iprl0; /* 0x04 Pending Register Low */
|
||||
u32 imrh0; /* 0x08 Mask Register High */
|
||||
u32 imrl0; /* 0x0C Mask Register Low */
|
||||
u32 frch0; /* 0x10 Force Register High */
|
||||
u32 frcl0; /* 0x14 Force Register Low */
|
||||
u8 irlr; /* 0x18 */
|
||||
u8 iacklpr; /* 0x19 */
|
||||
u16 res1[19]; /* 0x1a - 0x3c */
|
||||
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
|
||||
u32 res3[24]; /* 0x80 - 0xDF */
|
||||
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
|
||||
u8 res4[3]; /* 0xE1 - 0xE3 */
|
||||
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
|
||||
u8 res5[3]; /* 0xE5 - 0xE7 */
|
||||
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
|
||||
u8 res6[3]; /* 0xE9 - 0xEB */
|
||||
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
|
||||
u8 res7[3]; /* 0xED - 0xEF */
|
||||
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
|
||||
u8 res8[3]; /* 0xF1 - 0xF3 */
|
||||
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
|
||||
u8 res9[3]; /* 0xF5 - 0xF7 */
|
||||
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
|
||||
u8 resa[3]; /* 0xF9 - 0xFB */
|
||||
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
|
||||
u8 resb[3]; /* 0xFD - 0xFF */
|
||||
} int0_t;
|
||||
|
||||
/* Clock Module registers */
|
||||
typedef struct pll_ctrl {
|
||||
u16 syncr; /* 0x00 synthesizer control register */
|
||||
u16 synsr; /* 0x02 synthesizer status register */
|
||||
} pll_t;
|
||||
|
||||
/* Watchdog registers */
|
||||
typedef struct wdog_ctrl {
|
||||
ushort wcr;
|
||||
ushort wmr;
|
||||
ushort wcntr;
|
||||
ushort wsr;
|
||||
} wdog_t;
|
||||
|
||||
#endif /* __IMMAP_5282__ */
|
||||
|
||||
@ -24,7 +24,6 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef mcf5249_h
|
||||
#define mcf5249_h
|
||||
/****************************************************************************/
|
||||
@ -41,7 +40,6 @@
|
||||
#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
|
||||
#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
|
||||
|
||||
|
||||
/*
|
||||
* Size of internal RAM
|
||||
*/
|
||||
@ -98,10 +96,6 @@
|
||||
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
|
||||
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
|
||||
|
||||
/** UART Bases **/
|
||||
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
|
||||
|
||||
/*****************
|
||||
***** MBAR2 *****
|
||||
*****************/
|
||||
@ -173,7 +167,6 @@
|
||||
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
|
||||
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
|
||||
|
||||
|
||||
/*
|
||||
* Macros to read/set IMR register. It is 32 bits on the 5249.
|
||||
*/
|
||||
|
||||
@ -25,7 +25,6 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MCF5271_H_
|
||||
#define _MCF5271_H_
|
||||
|
||||
@ -117,4 +116,104 @@
|
||||
|
||||
#define MCFSIM_ICR1 0x000C41
|
||||
|
||||
/*********************************************************************
|
||||
* Interrupt Controller (INTC)
|
||||
*********************************************************************/
|
||||
#define INT0_LO_RSVD0 (0)
|
||||
#define INT0_LO_EPORT1 (1)
|
||||
#define INT0_LO_EPORT2 (2)
|
||||
#define INT0_LO_EPORT3 (3)
|
||||
#define INT0_LO_EPORT4 (4)
|
||||
#define INT0_LO_EPORT5 (5)
|
||||
#define INT0_LO_EPORT6 (6)
|
||||
#define INT0_LO_EPORT7 (7)
|
||||
#define INT0_LO_SCM (8)
|
||||
#define INT0_LO_DMA0 (9)
|
||||
#define INT0_LO_DMA1 (10)
|
||||
#define INT0_LO_DMA2 (11)
|
||||
#define INT0_LO_DMA3 (12)
|
||||
#define INT0_LO_UART0 (13)
|
||||
#define INT0_LO_UART1 (14)
|
||||
#define INT0_LO_UART2 (15)
|
||||
#define INT0_LO_RSVD1 (16)
|
||||
#define INT0_LO_I2C (17)
|
||||
#define INT0_LO_QSPI (18)
|
||||
#define INT0_LO_DTMR0 (19)
|
||||
#define INT0_LO_DTMR1 (20)
|
||||
#define INT0_LO_DTMR2 (21)
|
||||
#define INT0_LO_DTMR3 (22)
|
||||
#define INT0_LO_FEC_TXF (23)
|
||||
#define INT0_LO_FEC_TXB (24)
|
||||
#define INT0_LO_FEC_UN (25)
|
||||
#define INT0_LO_FEC_RL (26)
|
||||
#define INT0_LO_FEC_RXF (27)
|
||||
#define INT0_LO_FEC_RXB (28)
|
||||
#define INT0_LO_FEC_MII (29)
|
||||
#define INT0_LO_FEC_LC (30)
|
||||
#define INT0_LO_FEC_HBERR (31)
|
||||
#define INT0_HI_FEC_GRA (32)
|
||||
#define INT0_HI_FEC_EBERR (33)
|
||||
#define INT0_HI_FEC_BABT (34)
|
||||
#define INT0_HI_FEC_BABR (35)
|
||||
#define INT0_HI_PIT0 (36)
|
||||
#define INT0_HI_PIT1 (37)
|
||||
#define INT0_HI_PIT2 (38)
|
||||
#define INT0_HI_PIT3 (39)
|
||||
#define INT0_HI_RNG (40)
|
||||
#define INT0_HI_SKHA (41)
|
||||
#define INT0_HI_MDHA (42)
|
||||
#define INT0_HI_CAN1_BUF0I (43)
|
||||
#define INT0_HI_CAN1_BUF1I (44)
|
||||
#define INT0_HI_CAN1_BUF2I (45)
|
||||
#define INT0_HI_CAN1_BUF3I (46)
|
||||
#define INT0_HI_CAN1_BUF4I (47)
|
||||
#define INT0_HI_CAN1_BUF5I (48)
|
||||
#define INT0_HI_CAN1_BUF6I (49)
|
||||
#define INT0_HI_CAN1_BUF7I (50)
|
||||
#define INT0_HI_CAN1_BUF8I (51)
|
||||
#define INT0_HI_CAN1_BUF9I (52)
|
||||
#define INT0_HI_CAN1_BUF10I (53)
|
||||
#define INT0_HI_CAN1_BUF11I (54)
|
||||
#define INT0_HI_CAN1_BUF12I (55)
|
||||
#define INT0_HI_CAN1_BUF13I (56)
|
||||
#define INT0_HI_CAN1_BUF14I (57)
|
||||
#define INT0_HI_CAN1_BUF15I (58)
|
||||
#define INT0_HI_CAN1_ERRINT (59)
|
||||
#define INT0_HI_CAN1_BOFFINT (60)
|
||||
/* 60-63 Reserved */
|
||||
|
||||
/* Bit definitions and macros for INTC_IPRL */
|
||||
#define INTC_IPRL_INT31 (0x80000000)
|
||||
#define INTC_IPRL_INT30 (0x40000000)
|
||||
#define INTC_IPRL_INT29 (0x20000000)
|
||||
#define INTC_IPRL_INT28 (0x10000000)
|
||||
#define INTC_IPRL_INT27 (0x08000000)
|
||||
#define INTC_IPRL_INT26 (0x04000000)
|
||||
#define INTC_IPRL_INT25 (0x02000000)
|
||||
#define INTC_IPRL_INT24 (0x01000000)
|
||||
#define INTC_IPRL_INT23 (0x00800000)
|
||||
#define INTC_IPRL_INT22 (0x00400000)
|
||||
#define INTC_IPRL_INT21 (0x00200000)
|
||||
#define INTC_IPRL_INT20 (0x00100000)
|
||||
#define INTC_IPRL_INT19 (0x00080000)
|
||||
#define INTC_IPRL_INT18 (0x00040000)
|
||||
#define INTC_IPRL_INT17 (0x00020000)
|
||||
#define INTC_IPRL_INT16 (0x00010000)
|
||||
#define INTC_IPRL_INT15 (0x00008000)
|
||||
#define INTC_IPRL_INT14 (0x00004000)
|
||||
#define INTC_IPRL_INT13 (0x00002000)
|
||||
#define INTC_IPRL_INT12 (0x00001000)
|
||||
#define INTC_IPRL_INT11 (0x00000800)
|
||||
#define INTC_IPRL_INT10 (0x00000400)
|
||||
#define INTC_IPRL_INT9 (0x00000200)
|
||||
#define INTC_IPRL_INT8 (0x00000100)
|
||||
#define INTC_IPRL_INT7 (0x00000080)
|
||||
#define INTC_IPRL_INT6 (0x00000040)
|
||||
#define INTC_IPRL_INT5 (0x00000020)
|
||||
#define INTC_IPRL_INT4 (0x00000010)
|
||||
#define INTC_IPRL_INT3 (0x00000008)
|
||||
#define INTC_IPRL_INT2 (0x00000004)
|
||||
#define INTC_IPRL_INT1 (0x00000002)
|
||||
#define INTC_IPRL_INT0 (0x00000001)
|
||||
|
||||
#endif /* _MCF5271_H_ */
|
||||
|
||||
@ -24,7 +24,6 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef mcf5272_h
|
||||
#define mcf5272_h
|
||||
/****************************************************************************/
|
||||
@ -35,65 +34,173 @@
|
||||
|
||||
#define INT_RAM_SIZE 4096
|
||||
|
||||
#define GPIO_PACNT_PA15MSK (0xC0000000)
|
||||
#define GPIO_PACNT_DGNT1 (0x40000000)
|
||||
#define GPIO_PACNT_PA14MSK (0x30000000)
|
||||
#define GPIO_PACNT_DREQ1 (0x10000000)
|
||||
#define GPIO_PACNT_PA13MSK (0x0C000000)
|
||||
#define GPIO_PACNT_DFSC3 (0x04000000)
|
||||
#define GPIO_PACNT_PA12MSK (0x03000000)
|
||||
#define GPIO_PACNT_DFSC2 (0x01000000)
|
||||
#define GPIO_PACNT_PA11MSK (0x00C00000)
|
||||
#define GPIO_PACNT_QSPI_CS1 (0x00800000)
|
||||
#define GPIO_PACNT_PA10MSK (0x00300000)
|
||||
#define GPIO_PACNT_DREQ0 (0x00100000)
|
||||
#define GPIO_PACNT_PA9MSK (0x000C0000)
|
||||
#define GPIO_PACNT_DGNT0 (0x00040000)
|
||||
#define GPIO_PACNT_PA8MSK (0x00030000)
|
||||
#define GPIO_PACNT_FSC0 (0x00010000)
|
||||
#define GPIO_PACNT_FSR0 (0x00010000)
|
||||
#define GPIO_PACNT_PA7MSK (0x0000C000)
|
||||
#define GPIO_PACNT_DOUT3 (0x00008000)
|
||||
#define GPIO_PACNT_QSPI_CS3 (0x00004000)
|
||||
#define GPIO_PACNT_PA6MSK (0x00003000)
|
||||
#define GPIO_PACNT_USB_RXD (0x00001000)
|
||||
#define GPIO_PACNT_PA5MSK (0x00000C00)
|
||||
#define GPIO_PACNT_USB_TXEN (0x00000400)
|
||||
#define GPIO_PACNT_PA4MSK (0x00000300)
|
||||
#define GPIO_PACNT_USB_SUSP (0x00000100)
|
||||
#define GPIO_PACNT_PA3MSK (0x000000C0)
|
||||
#define GPIO_PACNT_USB_TN (0x00000040)
|
||||
#define GPIO_PACNT_PA2MSK (0x00000030)
|
||||
#define GPIO_PACNT_USB_RN (0x00000010)
|
||||
#define GPIO_PACNT_PA1MSK (0x0000000C)
|
||||
#define GPIO_PACNT_USB_RP (0x00000004)
|
||||
#define GPIO_PACNT_PA0MSK (0x00000003)
|
||||
#define GPIO_PACNT_USB_TP (0x00000001)
|
||||
|
||||
/*
|
||||
* Define the 5272 SIM register set addresses.
|
||||
*/
|
||||
#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
|
||||
#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
|
||||
#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
|
||||
#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
|
||||
#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
|
||||
#define GPIO_PBCNT_PB15MSK (0xC0000000)
|
||||
#define GPIO_PBCNT_E_MDC (0x40000000)
|
||||
#define GPIO_PBCNT_PB14MSK (0x30000000)
|
||||
#define GPIO_PBCNT_E_RXER (0x10000000)
|
||||
#define GPIO_PBCNT_PB13MSK (0x0C000000)
|
||||
#define GPIO_PBCNT_E_RXD1 (0x04000000)
|
||||
#define GPIO_PBCNT_PB12MSK (0x03000000)
|
||||
#define GPIO_PBCNT_E_RXD2 (0x01000000)
|
||||
#define GPIO_PBCNT_PB11MSK (0x00C00000)
|
||||
#define GPIO_PBCNT_E_RXD3 (0x00400000)
|
||||
#define GPIO_PBCNT_PB10MSK (0x00300000)
|
||||
#define GPIO_PBCNT_E_TXD1 (0x00100000)
|
||||
#define GPIO_PBCNT_PB9MSK (0x000C0000)
|
||||
#define GPIO_PBCNT_E_TXD2 (0x00040000)
|
||||
#define GPIO_PBCNT_PB8MSK (0x00030000)
|
||||
#define GPIO_PBCNT_E_TXD3 (0x00010000)
|
||||
#define GPIO_PBCNT_PB7MSK (0x0000C000)
|
||||
#define GPIO_PBCNT_TOUT0 (0x00004000)
|
||||
#define GPIO_PBCNT_PB6MSK (0x00003000)
|
||||
#define GPIO_PBCNT_TA (0x00001000)
|
||||
#define GPIO_PBCNT_PB4MSK (0x00000300)
|
||||
#define GPIO_PBCNT_URT0_CLK (0x00000100)
|
||||
#define GPIO_PBCNT_PB3MSK (0x000000C0)
|
||||
#define GPIO_PBCNT_URT0_RTS (0x00000040)
|
||||
#define GPIO_PBCNT_PB2MSK (0x00000030)
|
||||
#define GPIO_PBCNT_URT0_CTS (0x00000010)
|
||||
#define GPIO_PBCNT_PB1MSK (0x0000000C)
|
||||
#define GPIO_PBCNT_URT0_RXD (0x00000004)
|
||||
#define GPIO_PBCNT_URT0_TIN2 (0x00000004)
|
||||
#define GPIO_PBCNT_PB0MSK (0x00000003)
|
||||
#define GPIO_PBCNT_URT0_TXD (0x00000001)
|
||||
|
||||
#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
|
||||
#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
|
||||
#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
|
||||
#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
|
||||
#define GPIO_PDCNT_PD7MSK (0x0000C000)
|
||||
#define GPIO_PDCNT_TIN1 (0x00008000)
|
||||
#define GPIO_PDCNT_PWM_OUT2 (0x00004000)
|
||||
#define GPIO_PDCNT_PD6MSK (0x00003000)
|
||||
#define GPIO_PDCNT_TOUT1 (0x00002000)
|
||||
#define GPIO_PDCNT_PWM_OUT1 (0x00001000)
|
||||
#define GPIO_PDCNT_PD5MSK (0x00000C00)
|
||||
#define GPIO_PDCNT_INT4 (0x00000C00)
|
||||
#define GPIO_PDCNT_DIN3 (0x00000800)
|
||||
#define GPIO_PDCNT_PD4MSK (0x00000300)
|
||||
#define GPIO_PDCNT_URT1_TXD (0x00000200)
|
||||
#define GPIO_PDCNT_DOUT0 (0x00000100)
|
||||
#define GPIO_PDCNT_PD3MSK (0x000000C0)
|
||||
#define GPIO_PDCNT_INT5 (0x000000C0)
|
||||
#define GPIO_PDCNT_URT1_RTS (0x00000080)
|
||||
#define GPIO_PDCNT_PD2MSK (0x00000030)
|
||||
#define GPIO_PDCNT_QSPI_CS2 (0x00000030)
|
||||
#define GPIO_PDCNT_URT1_CTS (0x00000020)
|
||||
#define GPIO_PDCNT_PD1MSK (0x0000000C)
|
||||
#define GPIO_PDCNT_URT1_RXD (0x00000008)
|
||||
#define GPIO_PDCNT_URT1_TIN3 (0x00000008)
|
||||
#define GPIO_PDCNT_DIN0 (0x00000004)
|
||||
#define GPIO_PDCNT_PD0MSK (0x00000003)
|
||||
#define GPIO_PDCNT_URT1_CLK (0x00000002)
|
||||
#define GPIO_PDCNT_DCL0 (0x00000001)
|
||||
|
||||
#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
|
||||
#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
|
||||
#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
|
||||
#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
|
||||
#define INT_RSVD0 (0)
|
||||
#define INT_INT1 (1)
|
||||
#define INT_INT2 (2)
|
||||
#define INT_INT3 (3)
|
||||
#define INT_INT4 (4)
|
||||
#define INT_TMR0 (5)
|
||||
#define INT_TMR1 (6)
|
||||
#define INT_TMR2 (7)
|
||||
#define INT_TMR3 (8)
|
||||
#define INT_UART1 (9)
|
||||
#define INT_UART2 (10)
|
||||
#define INT_PLIP (11)
|
||||
#define INT_PLIA (12)
|
||||
#define INT_USB0 (13)
|
||||
#define INT_USB1 (14)
|
||||
#define INT_USB2 (15)
|
||||
#define INT_USB3 (16)
|
||||
#define INT_USB4 (17)
|
||||
#define INT_USB5 (18)
|
||||
#define INT_USB6 (19)
|
||||
#define INT_USB7 (20)
|
||||
#define INT_DMA (21)
|
||||
#define INT_ERX (22)
|
||||
#define INT_ETX (23)
|
||||
#define INT_ENTC (24)
|
||||
#define INT_QSPI (25)
|
||||
#define INT_INT5 (26)
|
||||
#define INT_INT6 (27)
|
||||
#define INT_SWTO (28)
|
||||
|
||||
#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
|
||||
#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
|
||||
#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
|
||||
#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
|
||||
#define INT_ICR1_TMR0MASK (0x000F000)
|
||||
#define INT_ICR1_TMR0PI (0x0008000)
|
||||
#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12)
|
||||
#define INT_ICR1_TMR1MASK (0x0000F00)
|
||||
#define INT_ICR1_TMR1PI (0x0000800)
|
||||
#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8)
|
||||
#define INT_ICR1_TMR2MASK (0x00000F0)
|
||||
#define INT_ICR1_TMR2PI (0x0000080)
|
||||
#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4)
|
||||
#define INT_ICR1_TMR3MASK (0x000000F)
|
||||
#define INT_ICR1_TMR3PI (0x0000008)
|
||||
#define INT_ICR1_TMR3IPL(x) (((x)&0x7))
|
||||
|
||||
#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
|
||||
#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
|
||||
#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
|
||||
#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
|
||||
#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
|
||||
#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
|
||||
#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
|
||||
#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
|
||||
|
||||
#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
|
||||
#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
|
||||
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
|
||||
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
|
||||
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
|
||||
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
|
||||
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
|
||||
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
|
||||
|
||||
#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
|
||||
#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
|
||||
#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
|
||||
#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
|
||||
#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
|
||||
#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
|
||||
#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
|
||||
#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
|
||||
#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
|
||||
#define INT_ISR_INT31 (0x80000000)
|
||||
#define INT_ISR_INT30 (0x40000000)
|
||||
#define INT_ISR_INT29 (0x20000000)
|
||||
#define INT_ISR_INT28 (0x10000000)
|
||||
#define INT_ISR_INT27 (0x08000000)
|
||||
#define INT_ISR_INT26 (0x04000000)
|
||||
#define INT_ISR_INT25 (0x02000000)
|
||||
#define INT_ISR_INT24 (0x01000000)
|
||||
#define INT_ISR_INT23 (0x00800000)
|
||||
#define INT_ISR_INT22 (0x00400000)
|
||||
#define INT_ISR_INT21 (0x00200000)
|
||||
#define INT_ISR_INT20 (0x00100000)
|
||||
#define INT_ISR_INT19 (0x00080000)
|
||||
#define INT_ISR_INT18 (0x00040000)
|
||||
#define INT_ISR_INT17 (0x00020000)
|
||||
#define INT_ISR_INT16 (0x00010000)
|
||||
#define INT_ISR_INT15 (0x00008000)
|
||||
#define INT_ISR_INT14 (0x00004000)
|
||||
#define INT_ISR_INT13 (0x00002000)
|
||||
#define INT_ISR_INT12 (0x00001000)
|
||||
#define INT_ISR_INT11 (0x00000800)
|
||||
#define INT_ISR_INT10 (0x00000400)
|
||||
#define INT_ISR_INT9 (0x00000200)
|
||||
#define INT_ISR_INT8 (0x00000100)
|
||||
#define INT_ISR_INT7 (0x00000080)
|
||||
#define INT_ISR_INT6 (0x00000040)
|
||||
#define INT_ISR_INT5 (0x00000020)
|
||||
#define INT_ISR_INT4 (0x00000010)
|
||||
#define INT_ISR_INT3 (0x00000008)
|
||||
#define INT_ISR_INT2 (0x00000004)
|
||||
#define INT_ISR_INT1 (0x00000002)
|
||||
#define INT_ISR_INT0 (0x00000001)
|
||||
|
||||
#endif /* mcf5272_h */
|
||||
|
||||
@ -23,7 +23,99 @@
|
||||
/****************************************************************************/
|
||||
#ifndef m5282_h
|
||||
#define m5282_h
|
||||
/****************************************************************************/
|
||||
|
||||
/*********************************************************************
|
||||
* PLL Clock Module
|
||||
*********************************************************************/
|
||||
/* Bit definitions and macros for PLL_SYNCR */
|
||||
#define PLL_SYNCR_LOLRE (0x8000)
|
||||
#define PLL_SYNCR_MFD2 (0x4000)
|
||||
#define PLL_SYNCR_MFD1 (0x2000)
|
||||
#define PLL_SYNCR_MFD0 (0x1000)
|
||||
#define PLL_SYNCR_LOCRE (0x0800)
|
||||
#define PLL_SYNCR_RFC2 (0x0400)
|
||||
#define PLL_SYNCR_RFC1 (0x0200)
|
||||
#define PLL_SYNCR_RFC0 (0x0100)
|
||||
#define PLL_SYNCR_LOCEN (0x0080)
|
||||
#define PLL_SYNCR_DISCLK (0x0040)
|
||||
#define PLL_SYNCR_FWKUP (0x0020)
|
||||
#define PLL_SYNCR_STPMD1 (0x0008)
|
||||
#define PLL_SYNCR_STPMD0 (0x0004)
|
||||
|
||||
/* Bit definitions and macros for PLL_SYNSR */
|
||||
#define PLL_SYNSR_MODE (0x0080)
|
||||
#define PLL_SYNSR_PLLSEL (0x0040)
|
||||
#define PLL_SYNSR_PLLREF (0x0020)
|
||||
#define PLL_SYNSR_LOCKS (0x0010)
|
||||
#define PLL_SYNSR_LOCK (0x0008)
|
||||
#define PLL_SYNSR_LOCS (0x0004)
|
||||
|
||||
/*********************************************************************
|
||||
* Interrupt Controller (INTC)
|
||||
*********************************************************************/
|
||||
#define INT0_LO_RSVD0 (0)
|
||||
#define INT0_LO_EPORT1 (1)
|
||||
#define INT0_LO_EPORT2 (2)
|
||||
#define INT0_LO_EPORT3 (3)
|
||||
#define INT0_LO_EPORT4 (4)
|
||||
#define INT0_LO_EPORT5 (5)
|
||||
#define INT0_LO_EPORT6 (6)
|
||||
#define INT0_LO_EPORT7 (7)
|
||||
#define INT0_LO_SCM_SWT1 (8)
|
||||
#define INT0_LO_DMA_00 (9)
|
||||
#define INT0_LO_DMA_01 (10)
|
||||
#define INT0_LO_DMA_02 (11)
|
||||
#define INT0_LO_DMA_03 (12)
|
||||
#define INT0_LO_UART0 (13)
|
||||
#define INT0_LO_UART1 (14)
|
||||
#define INT0_LO_UART2 (15)
|
||||
#define INT0_LO_RSVD1 (16)
|
||||
#define INT0_LO_I2C (17)
|
||||
#define INT0_LO_QSPI (18)
|
||||
#define INT0_LO_DTMR0 (19)
|
||||
#define INT0_LO_DTMR1 (20)
|
||||
#define INT0_LO_DTMR2 (21)
|
||||
#define INT0_LO_DTMR3 (22)
|
||||
#define INT0_LO_FEC_TXF (23)
|
||||
#define INT0_LO_FEC_TXB (24)
|
||||
#define INT0_LO_FEC_UN (25)
|
||||
#define INT0_LO_FEC_RL (26)
|
||||
#define INT0_LO_FEC_RXF (27)
|
||||
#define INT0_LO_FEC_RXB (28)
|
||||
#define INT0_LO_FEC_MII (29)
|
||||
#define INT0_LO_FEC_LC (30)
|
||||
#define INT0_LO_FEC_HBERR (31)
|
||||
#define INT0_HI_FEC_GRA (32)
|
||||
#define INT0_HI_FEC_EBERR (33)
|
||||
#define INT0_HI_FEC_BABT (34)
|
||||
#define INT0_HI_FEC_BABR (35)
|
||||
#define INT0_HI_PMM_LVDF (36)
|
||||
#define INT0_HI_QADC_CF1 (37)
|
||||
#define INT0_HI_QADC_CF2 (38)
|
||||
#define INT0_HI_QADC_PF1 (39)
|
||||
#define INT0_HI_QADC_PF2 (40)
|
||||
#define INT0_HI_GPTA_TOF (41)
|
||||
#define INT0_HI_GPTA_PAIF (42)
|
||||
#define INT0_HI_GPTA_PAOVF (43)
|
||||
#define INT0_HI_GPTA_C0F (44)
|
||||
#define INT0_HI_GPTA_C1F (45)
|
||||
#define INT0_HI_GPTA_C2F (46)
|
||||
#define INT0_HI_GPTA_C3F (47)
|
||||
#define INT0_HI_GPTB_TOF (48)
|
||||
#define INT0_HI_GPTB_PAIF (49)
|
||||
#define INT0_HI_GPTB_PAOVF (50)
|
||||
#define INT0_HI_GPTB_C0F (51)
|
||||
#define INT0_HI_GPTB_C1F (52)
|
||||
#define INT0_HI_GPTB_C2F (53)
|
||||
#define INT0_HI_GPTB_C3F (54)
|
||||
#define INT0_HI_PIT0 (55)
|
||||
#define INT0_HI_PIT1 (56)
|
||||
#define INT0_HI_PIT2 (57)
|
||||
#define INT0_HI_PIT3 (58)
|
||||
#define INT0_HI_CFM_CBEIF (59)
|
||||
#define INT0_HI_CFM_CCIF (60)
|
||||
#define INT0_HI_CFM_PVIF (61)
|
||||
#define INT0_HI_CFM_AEIF (62)
|
||||
|
||||
/*
|
||||
* Size of internal RAM
|
||||
@ -171,7 +263,6 @@
|
||||
#define MCFGPIO_Px0 (0x01)
|
||||
#define MCFGPIO_Px(x) (0x01<<x)
|
||||
|
||||
|
||||
#define MCFGPIO_PBCDPAR_PBPA (0x80)
|
||||
#define MCFGPIO_PBCDPAR_PCDPA (0x40)
|
||||
|
||||
@ -256,7 +347,6 @@
|
||||
#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
|
||||
#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
|
||||
|
||||
|
||||
#define MCFSCM_CRSR_EXT (0x80)
|
||||
#define MCFSCM_CRSR_CWDR (0x20)
|
||||
#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
|
||||
@ -291,7 +381,6 @@
|
||||
#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
|
||||
#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
|
||||
|
||||
|
||||
/* Bit level definitions and macros */
|
||||
#define MCFCCM_CCR_LOAD (0x8000)
|
||||
#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
|
||||
@ -375,9 +464,7 @@
|
||||
#define MCFCSM_CSCR_PS_16 (0x0080)
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose Timer (GPT) Module
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
|
||||
@ -403,7 +490,6 @@
|
||||
#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
|
||||
#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
|
||||
|
||||
|
||||
#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
|
||||
#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
|
||||
#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
|
||||
|
||||
@ -1,111 +0,0 @@
|
||||
/*
|
||||
* mcftimer.h -- ColdFire internal TIMER support defines.
|
||||
*
|
||||
* Based on mcftimer.h of uCLinux distribution:
|
||||
* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
|
||||
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
#ifndef mcftimer_h
|
||||
#define mcftimer_h
|
||||
/****************************************************************************/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
/*
|
||||
* Get address specific defines for this ColdFire member.
|
||||
*/
|
||||
#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
|
||||
#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
|
||||
#elif defined(CONFIG_M5272)
|
||||
#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
|
||||
#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
|
||||
#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
|
||||
#elif defined(CONFIG_M5282) | defined(CONFIG_M5271)
|
||||
#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
|
||||
#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
|
||||
#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the TIMER register set addresses.
|
||||
*/
|
||||
#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
|
||||
#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
|
||||
#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
|
||||
#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
|
||||
#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
|
||||
|
||||
/*
|
||||
* Define the TIMER register set addresses for 5282.
|
||||
*/
|
||||
#define MCFTIMER_PCSR 0
|
||||
#define MCFTIMER_PMR 1
|
||||
#define MCFTIMER_PCNTR 2
|
||||
|
||||
/*
|
||||
* Bit definitions for the Timer Mode Register (TMR).
|
||||
* Register bit flags are common accross ColdFires.
|
||||
*/
|
||||
#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
|
||||
#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
|
||||
#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
|
||||
#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
|
||||
#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
|
||||
#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
|
||||
#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
|
||||
#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
|
||||
#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
|
||||
#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
|
||||
#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
|
||||
#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
|
||||
#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
|
||||
#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
|
||||
#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
|
||||
#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
|
||||
#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Timer Event Registers (TER).
|
||||
*/
|
||||
#define MCFTIMER_TER_CAP 0x01 /* Capture event */
|
||||
#define MCFTIMER_TER_REF 0x02 /* Refernece event */
|
||||
|
||||
/*
|
||||
* Bit definitions for the 5282 PIT Control and Status Register (PCSR).
|
||||
*/
|
||||
#define MCFTIMER_PCSR_EN 0x0001
|
||||
#define MCFTIMER_PCSR_RLD 0x0002
|
||||
#define MCFTIMER_PCSR_PIF 0x0004
|
||||
#define MCFTIMER_PCSR_PIE 0x0008
|
||||
#define MCFTIMER_PCSR_OVW 0x0010
|
||||
#define MCFTIMER_PCSR_HALTED 0x0020
|
||||
#define MCFTIMER_PCSR_DOZE 0x0040
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* mcftimer_h */
|
||||
@ -1,217 +0,0 @@
|
||||
/*
|
||||
* mcfuart.h -- ColdFire internal UART support defines.
|
||||
*
|
||||
* File copied from mcfuart.h of uCLinux distribution:
|
||||
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
|
||||
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
#ifndef mcfuart_h
|
||||
#define mcfuart_h
|
||||
/****************************************************************************/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
/*
|
||||
* Define the base address of the UARTS within the MBAR address
|
||||
* space.
|
||||
*/
|
||||
#if defined(CONFIG_M5272)
|
||||
#define MCFUART_BASE1 0x100 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
|
||||
#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
|
||||
#if defined(CONFIG_NETtel)
|
||||
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
|
||||
#else
|
||||
#define MCFUART_BASE1 0x140 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x180 /* Base address of UART2 */
|
||||
#endif
|
||||
#elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
|
||||
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
|
||||
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
|
||||
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
|
||||
#else
|
||||
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the ColdFire UART register set addresses.
|
||||
*/
|
||||
#define MCFUART_UMR 0x00 /* Mode register (r/w) */
|
||||
#define MCFUART_USR 0x04 /* Status register (r) */
|
||||
#define MCFUART_UCSR 0x04 /* Clock Select (w) */
|
||||
#define MCFUART_UCR 0x08 /* Command register (w) */
|
||||
#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
|
||||
#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
|
||||
#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
|
||||
#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
|
||||
#define MCFUART_UISR 0x14 /* Interrup Status (r) */
|
||||
#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
|
||||
#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
|
||||
#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
|
||||
#ifdef CONFIG_M5272
|
||||
#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
|
||||
#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
|
||||
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
|
||||
#else
|
||||
#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
|
||||
#endif
|
||||
#define MCFUART_UIPR 0x34 /* Input Port (r) */
|
||||
#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
|
||||
#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
|
||||
|
||||
#ifdef CONFIG_M5249
|
||||
/* Note: This isn't in the 5249 docs */
|
||||
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define bit flags in Mode Register 1 (MR1).
|
||||
*/
|
||||
#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
|
||||
#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
|
||||
#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
|
||||
#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
|
||||
#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
|
||||
|
||||
#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
|
||||
#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
|
||||
#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
|
||||
#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
|
||||
#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
|
||||
|
||||
#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
|
||||
#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
|
||||
#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
|
||||
#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
|
||||
|
||||
/*
|
||||
* Define bit flags in Mode Register 2 (MR2).
|
||||
*/
|
||||
#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
|
||||
#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
|
||||
#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
|
||||
#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
|
||||
#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
|
||||
|
||||
#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
|
||||
#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
|
||||
#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
|
||||
|
||||
/*
|
||||
* Define bit flags in Status Register (USR).
|
||||
*/
|
||||
#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
|
||||
#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
|
||||
#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
|
||||
#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
|
||||
#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
|
||||
#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
|
||||
#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
|
||||
#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
|
||||
|
||||
#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
|
||||
MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
|
||||
|
||||
/*
|
||||
* Define bit flags in Clock Select Register (UCSR).
|
||||
*/
|
||||
#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
|
||||
#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
|
||||
#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
|
||||
|
||||
#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
|
||||
#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
|
||||
#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
|
||||
|
||||
/*
|
||||
* Define bit flags in Command Register (UCR).
|
||||
*/
|
||||
#define MCFUART_UCR_CMDNULL 0x00 /* No command */
|
||||
#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
|
||||
#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
|
||||
#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
|
||||
#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
|
||||
#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
|
||||
#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
|
||||
#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
|
||||
|
||||
#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
|
||||
#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
|
||||
#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
|
||||
#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
|
||||
#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
|
||||
#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
|
||||
|
||||
/*
|
||||
* Define bit flags in Input Port Change Register (UIPCR).
|
||||
*/
|
||||
#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
|
||||
#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
|
||||
|
||||
/*
|
||||
* Define bit flags in Input Port Register (UIP).
|
||||
*/
|
||||
#define MCFUART_UIPR_CTS 0x01 /* CTS value */
|
||||
|
||||
/*
|
||||
* Define bit flags in Output Port Registers (UOP).
|
||||
* Clear bit by writing to UOP0, set by writing to UOP1.
|
||||
*/
|
||||
#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
|
||||
|
||||
/*
|
||||
* Define bit flags in the Auxiliary Control Register (UACR).
|
||||
*/
|
||||
#define MCFUART_UACR_IEC 0x01 /* Input enable control */
|
||||
|
||||
/*
|
||||
* Define bit flags in Interrupt Status Register (UISR).
|
||||
* These same bits are used for the Interrupt Mask Register (UIMR).
|
||||
*/
|
||||
#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
|
||||
#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
|
||||
#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
|
||||
#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
/*
|
||||
* Define bit flags in the Transmitter FIFO Register (UTF).
|
||||
*/
|
||||
#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
|
||||
#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
|
||||
#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
|
||||
|
||||
/*
|
||||
* Define bit flags in the Receiver FIFO Register (URF).
|
||||
*/
|
||||
#define MCFUART_URF_RXB 0x1f /* receiver data level */
|
||||
#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
|
||||
#define MCFUART_URF_RXS 0xc0 /* receiver status */
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user