brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

nios2: set default cache configuration in start.S

Browse Source 
Set default icache and dcache configuration for start.S.

We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE...
configuration macros. As we are just barely starting from
reset, there is no luxury of device tree.

We will set some maximum cache configuration so that it will
work for most configurations. This is used only in this
start.S. The speed penalty is only once here.

After start up, during board initialization, cpu information
will be extracted from device tree. Then cache flush operations
will have correct cache configurations.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Thomas Chou 2015-10-09 20:09:17 +08:00
parent bbba0714b7
commit 55e2b4d4e5
1 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/nios2/cpu/start.S
View File

@ -9,6 +9,15 @@
#include <config.h>
#include <version.h>
/*
* icache and dcache configuration used only for start.S.
* the values are chosen so that it will work for all configuration.
*/
#define ICACHE_LINE_SIZE 32 /* fixed 32 */
#define ICACHE_SIZE_MAX 0x10000 /* 64k max */
#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */
#define DCACHE_SIZE_MAX 0x10000 /* 64k max */
/* RESTART */
.text
.global _start
@ -22,9 +31,9 @@ _start:
* just be invalidating the cache a second time. If cache
* is not implemented initi behaves as nop.
*/
ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE)
ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
ori r4, r0, %lo(ICACHE_LINE_SIZE)
movhi r5, %hi(ICACHE_SIZE_MAX)
ori r5, r5, %lo(ICACHE_SIZE_MAX)
0: initi r5
sub r5, r5, r4
bgt r5, r0, 0b
@ -51,10 +60,9 @@ _except_end:
* DCACHE INIT -- if dcache not implemented, initd behaves as
* nop.
*/
movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE)
ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE)
movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE)
ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE)
ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
movhi r5, %hi(DCACHE_SIZE_MAX)
ori r5, r5, %lo(DCACHE_SIZE_MAX)
mov r6, r0
1: initd 0(r6)
add r6, r6, r4