diff --git a/CHANGELOG b/CHANGELOG index 5399007b61..e6cd97c550 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,157 @@ +commit 161e4ae46046282fde6a69a0f1f80965f2a1b6f4 +Author: Heiko Schocher +Date: Thu Jun 17 07:01:40 2010 +0200 + + powerpc: fix wrong comment at GOT definitions + + r12 is used for accessing the GOT not r14. Fix this in the + comment. + + Signed-off-by: Heiko Schocher + +commit 7030d56b7946c8db2e8082a9b84cd69b9540a0ca +Author: Becky Bruce +Date: Thu Jun 17 11:37:27 2010 -0500 + + MAKEALL: Add missing powerpc 36-bit targets + + We were missing 8641HPCN_36BIT and MPC8536DS_36BIT. + + Signed-off-by: Becky Bruce + +commit e03b4d296b27790de3b25edd32784d20538240d8 +Author: Anatolij Gustschin +Date: Sat Jun 26 00:39:28 2010 +0200 + + Fix compiler warnings for EVB64260, P3G4 and ZUMA + + Fix following warnings: + + $ ./MAKEALL EVB64260 P3G4 ZUMA + Configuring for EVB64260 board... + mpsc.c: In function 'mpsc_putchar_early': + mpsc.c:121: warning: dereferencing type-punned pointer will break strict-aliasing rules + mpsc.c:127: warning: dereferencing type-punned pointer will break strict-aliasing rules + ... + + Signed-off-by: Anatolij Gustschin + +commit 9fb3b5085787baad8a133e347ad12c5b3a022e98 +Author: Sergei Shtylyov +Date: Mon Jun 28 22:44:49 2010 +0400 + + EHCI: zero out QH transfer overlay in ehci_submit_async() + + ehci_submit_async() doesn't really zero out the QH transfer overlay (as the EHCI + specification suggests) which leads to the controller seeing the "token" field + as the previous call has left it, i.e.: + - if a timeout occured on the previous call (Active bit left as 1), controller + incorrectly tries to complete a previous transaction on a newly programmed + endpoint; + - if a halt occured on the previous call (Halted bit set to 1), controller just + ignores the newly programmed TD(s) and the function then keeps returning error + ad infinitum. + + This turned out to be caused by the wrong orger of the arguments to the memset() + call in ehci_alloc(), so the allocated TDs weren't cleared either. + + While at it, stop needlessly initializing the alternate next TD pointer in the + QH transfer overlay... + + Signed-off-by: Sergei Shtylyov + Acked-by: Remy Bohmer + +commit 0d7f4abcf6bbef06504c82e03f11054468262430 +Author: Remy Bohmer +Date: Thu Jun 17 21:17:08 2010 +0200 + + Fix console_buffer size conflict error. + + The console_buffer size is declared in common/main.c as + -- char console_buffer[CONFIG_SYS_CBSIZE + 1]; + so this extern definition is wrong. + + Signed-off-by: Remy Bohmer + +commit 38c38c344c200ee90cfd243671473c449b6f0815 +Author: Poonam Aggrwal +Date: Tue Jun 22 12:50:46 2010 +0530 + + 85xx/p1_p2_rdb: Added RevD board version support + + - Also modified the code to use io accessors. + + Signed-off-by: Poonam Aggrwal + Signed-off-by: Dipen Dudhat + Acked-by: Kumar Gala + +commit c987f4753b0afadb38acd7e61df7ba11e8a0203f +Author: Felix Radensky +Date: Mon Jun 28 01:57:39 2010 +0300 + + tsec: Fix eTSEC2 link problem on P2020RDB + + On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII. + Current TBI PHY settings for SGMII mode cause link problems on + this platform, link never comes up. + + Fix this by making TBI PHY settings configurable and add a working + configuration for P2020RDB. + + Signed-off-by: Felix Radensky + Acked-by: Andy Fleming + Acked-by: Peter Tyser + Tested-by: Peter Tyser + +commit d3bee08332fbc9cc5b6dc22ecd34050a85d44d0a +Author: Poonam Aggrwal +Date: Wed Jun 23 19:32:28 2010 +0530 + + 85xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHz + + Use a slighly larger value of CLK_CTRL for DDR at 667MHz + which fixes random crashes while linux booting. + + Applicable for both NAND and NOR boot. + + Signed-off-by: Sandeep Gopalpet + Signed-off-by: Poonam Aggrwal + Acked-by: Andy Fleming + +commit cdc6363f423900645265563d705a0a5a964ae40c +Author: Poonam Aggrwal +Date: Wed Jun 23 19:42:07 2010 +0530 + + 85xx/p1_p2_rdb: not able to modify "$bootfile" environment variable + + Because the variable was getting defined twice. + + Signed-off-by: Poonam Aggrwal + Acked-by: Andy Fleming + +commit 4ccd5510e50b5675227a1fe0e5ca099d333f637d +Author: Wolfgang Denk +Date: Tue Jun 29 01:33:35 2010 +0200 + + MPC512x: workaround data corruption for unaligned local bus accesses + + Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned + local bus accesses" fixed the problem for MPC5200 only, but MPC512x is + affected as well, so apply the same fix here, too. + + Signed-off-by: Wolfgang Denk + Cc: Detlev Zundel + Cc: Anatolij Gustschin + Acked-by: Detlev Zundel + +commit 482126e27b3dbf0e69a6445da8b94b3551adf05d +Author: Wolfgang Denk +Date: Wed Jun 23 20:50:54 2010 +0200 + + Prepare v2010.06-rc3 + + Signed-off-by: Wolfgang Denk + commit 460c2ce362e56890c2a029e2c3b1ff2796c7fc54 Author: Wolfgang Denk Date: Mon Jun 21 22:29:59 2010 +0200 diff --git a/MAKEALL b/MAKEALL index d6d5f5b423..27f8bd166e 100755 --- a/MAKEALL +++ b/MAKEALL @@ -393,6 +393,7 @@ LIST_85xx=" \ MPC8536DS_NAND \ MPC8536DS_SDCARD \ MPC8536DS_SPIFLASH \ + MPC8536DS_36BIT \ MPC8540ADS \ MPC8540EVAL \ MPC8541CDS \ @@ -453,6 +454,7 @@ LIST_85xx=" \ LIST_86xx=" \ MPC8610HPCD \ + MPC8641HPCN_36BIT \ MPC8641HPCN \ sbc8641d \ XPEDITE5170 \ diff --git a/Makefile b/Makefile index 87d5214a2d..d7a6921786 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ VERSION = 2010 PATCHLEVEL = 06 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile index 4ab2b7be76..0ee0611550 100644 --- a/arch/powerpc/cpu/mpc5xxx/Makefile +++ b/arch/powerpc/cpu/mpc5xxx/Makefile @@ -30,11 +30,6 @@ SOBJS = io.o firmware_sc_task_bestcomm.impl.o COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \ loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o -# Workaround for local bus unaligned access problem on MPC5200 -#ifdef CONFIG_MPC5200 -COBJS += memcpy_mpc5200.o -#endif - SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index bf23790c42..2065b6d807 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -40,14 +40,22 @@ COBJS-y += interrupts.o COBJS-$(CONFIG_CMD_KGDB) += kgdb.o COBJS-y += time.o -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -# Workaround for local bus unaligned access problem on MPC5200 +# Workaround for local bus unaligned access problems +# on MPC512x and MPC5200 +ifdef CONFIG_MPC512X +$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +COBJS-y += memcpy_mpc5200.o +endif ifdef CONFIG_MPC5200 $(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +COBJS-y += memcpy_mpc5200.o endif +COBJS += $(sort $(COBJS-y)) + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) + $(LIB): $(obj).depend $(OBJS) @if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\ then \ diff --git a/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c b/arch/powerpc/lib/memcpy_mpc5200.c similarity index 100% rename from arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c rename to arch/powerpc/lib/memcpy_mpc5200.c diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c index 8c4a4c8990..3164967fed 100644 --- a/board/evb64260/mpsc.c +++ b/board/evb64260/mpsc.c @@ -88,7 +88,7 @@ static void galsdma_enable_rx(void); /* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */ -#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack)) +#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack[0])) #define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);} #define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M) diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index fccc4f8f58..15b46b0da1 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -76,7 +76,7 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 #define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 #define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000 +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 #define CONFIG_SYS_DDR_MODE_1_667 0x00040852 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 31cdf9ae4c..fae31f28c0 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -54,6 +54,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BOARDREV_MASK 0x10100000 #define BOARDREV_B 0x10100000 #define BOARDREV_C 0x00100000 +#define BOARDREV_D 0x00000000 #define SYSCLK_66 66666666 #define SYSCLK_50 50000000 @@ -64,7 +65,7 @@ unsigned long get_board_sys_clk(ulong dummy) volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); u32 val_gpdat, sysclk_gpio, board_rev_gpio; - val_gpdat = pgpio->gpdat; + val_gpdat = in_be32(&pgpio->gpdat); sysclk_gpio = val_gpdat & SYSCLK_MASK; board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) { @@ -77,6 +78,11 @@ unsigned long get_board_sys_clk(ulong dummy) return SYSCLK_66; else return SYSCLK_50; + } else if (board_rev_gpio == BOARDREV_D) { + if(sysclk_gpio == 0) + return SYSCLK_66; + else + return SYSCLK_100; } return 0; } @@ -100,12 +106,14 @@ int checkboard (void) char board_rev = 0; struct cpu_type *cpu; - val_gpdat = pgpio->gpdat; + val_gpdat = in_be32(&pgpio->gpdat); board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) board_rev = 'C'; else if (board_rev_gpio == BOARDREV_B) board_rev = 'B'; + else if (board_rev_gpio == BOARDREV_D) + board_rev = 'D'; else panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio); @@ -159,6 +167,7 @@ int board_eth_init(bd_t *bis) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; char *tmp; + u32 pordevsr; unsigned int vscfw_addr; #ifdef CONFIG_TSEC1 @@ -171,7 +180,8 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + pordevsr = in_be32(&gur->pordevsr); + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif diff --git a/common/hush.c b/common/hush.c index 06c5ff8df4..9eea90f428 100644 --- a/common/hush.c +++ b/common/hush.c @@ -1018,7 +1018,7 @@ static void get_user_input(struct in_str *i) fflush(stdout); i->p = the_command; #else - extern char console_buffer[CONFIG_SYS_CBSIZE]; + extern char console_buffer[]; int n; static char the_command[CONFIG_SYS_CBSIZE]; diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3e4c3bd31b..5fa6f61008 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -281,12 +281,16 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, | TBIANA_FULL_DUPLEX \ ) -/* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ +/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ +#ifndef CONFIG_TSEC_TBICR_SETTINGS #define TBICR_SETTINGS ( \ TBICR_PHY_RESET \ | TBICR_FULL_DUPLEX \ | TBICR_SPEED1_SET \ ) +#else +#define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS +#endif /* CONFIG_TSEC_TBICR_SETTINGS */ /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 7784d92b6f..37d056e005 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -275,7 +275,7 @@ static void *ehci_alloc(size_t sz, size_t align) return NULL; } - memset(p, sz, 0); + memset(p, 0, sz); return p; } @@ -350,7 +350,6 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, (dev->parent->devnum << 16) | (0 << 8) | (0 << 0); qh->qh_endpt2 = cpu_to_hc32(endpt); qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); - qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); td = NULL; tdp = &qh->qh_overlay.qt_next; diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index a9b4004c36..b891730789 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -425,6 +425,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHPRIME "eTSEC1" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #endif /* CONFIG_TSEC_ENET */ /* @@ -568,7 +577,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ "erase " MK_STR(TEXT_BASE) " +$filesize; " \ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 84de146e5d..2db4784d3b 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -35,7 +35,7 @@ * * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es * - * Uses r14 to access the GOT + * Uses r12 to access the GOT */ #define START_GOT \