From eb412d79e476e871374ed1b8e561287746609018 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 23 Nov 2014 11:52:20 +0800 Subject: [PATCH 01/20] imx:mx6 fix return value of mxc_get_clock mxc_get_clock's return type is unsigned int. 'return -1' is same with 'return 0xffffffff', so 0 should be used as the return value when unsupported mxc_clock type is passed to mxc_get_clock. Also include an err message when unsupported mxc_clock type is passed to mxc_get_clock. Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam --- arch/arm/cpu/armv7/mx6/clock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 93a02adcec..b6983e60d7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -746,10 +746,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_SATA_CLK: return get_ahb_clk(); default: + printf("Unsupported MXC CLK: %d\n", clk); break; } - return -1; + return 0; } /* From 5a3d63c5cdd839d938a535555d9d57448d212ad9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 2 Dec 2014 09:55:27 +0800 Subject: [PATCH 02/20] imx:mx6sabresd add board level support for usb Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power Signed-off-by: Peng Fan --- board/freescale/mx6sabresd/mx6sabresd.c | 68 +++++++++++++++++++++++++ include/configs/mx6sabresd.h | 14 +++++ 2 files changed, 82 insertions(+) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index ac3757f074..2f7198d3bf 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -29,6 +29,7 @@ #include #include "../common/pfuze.h" #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -537,6 +538,69 @@ int board_eth_init(bd_t *bis) return cpu_eth_init(bis); } +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usb_hc1_pads[] = { + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + + imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, + ARRAY_SIZE(usb_hc1_pads)); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + if (on) + gpio_direction_output(IMX_GPIO_NR(1, 29), 1); + else + gpio_direction_output(IMX_GPIO_NR(1, 29), 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -557,6 +621,10 @@ int board_init(void) #endif setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index a346542130..99d9d4d7cf 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -60,4 +60,18 @@ #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ +#endif + #endif /* __MX6QSABRESD_CONFIG_H */ From fb00bda705cd983bc261fba66ca4b7f5f056fdeb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 2 Dec 2014 09:55:28 +0800 Subject: [PATCH 03/20] imx:mx6qarm2 add board level support for usb Add pinmux settings and implement board_ehci_hcd_init Signed-off-by: Peng Fan --- board/freescale/mx6qarm2/mx6qarm2.c | 42 +++++++++++++++++++++++++++++ include/configs/mx6qarm2.h | 14 ++++++++++ 2 files changed, 56 insertions(+) diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 3a5b26dde7..98ccdb785b 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -16,6 +16,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -213,6 +214,43 @@ int board_eth_init(bd_t *bis) return 0; } +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 1); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 0) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -226,6 +264,10 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 6e01fa0435..76cfef123c 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -189,4 +189,18 @@ #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + #endif /* __CONFIG_H */ From bd2600d375adb898b9ef8227059b14619a5e2cc5 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 4 Dec 2014 09:55:36 +0100 Subject: [PATCH 04/20] ot1200: add fsuuid command Signed-off-by: Christian Gmeiner --- include/configs/ot1200.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 9512b1e150..0d0873d444 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -197,6 +197,8 @@ #define CONFIG_CMD_EXT4 #define CONFIG_DOS_PARTITION #define CONFIG_CMD_FS_GENERIC +#define CONFIG_LIB_UUID +#define CONFIG_CMD_FS_UUID #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTFILE From 7f22307c03c76b46821c3a22cffa45dad25aaa2b Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 4 Dec 2014 09:56:32 +0100 Subject: [PATCH 05/20] ot1200: enable support for USB_STORAGE Signed-off-by: Christian Gmeiner --- include/configs/ot1200.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 0d0873d444..255c933baa 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -85,6 +85,7 @@ /* USB Configs */ #define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX6 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) From 576cd6b3faf76f9a4248a80c7b9c737402c33be7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 4 Dec 2014 13:04:06 +0100 Subject: [PATCH 06/20] arm: mx6: gw_ventana: Change clock init to enable NAND related clocks Otherwise NAND booting is likely to fail. Since this disables the NAND related clocks and SPL can't load the main U-Boot from NAND. This problem was introduced with this patch: e25fbe3f (gw_ventana: Move the DCD settings to spl code) Signed-off-by: Stefan Roese Cc: Fabio Estevam Cc: Tim Harvey Cc: Stefano Babic Reviewed-by: Fabio Estevam --- board/gateworks/gw_ventana/gw_ventana_spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index d6a584745b..97128127fb 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -401,7 +401,7 @@ static void ccgr_init(void) writel(0x0030FC03, &ccm->CCGR1); writel(0x0FFFC000, &ccm->CCGR2); writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); + writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ writel(0x0F0000C3, &ccm->CCGR5); writel(0x000003FF, &ccm->CCGR6); } From 76494f7ac38ef97510c2e9ef13943e472f0d2702 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 12 Dec 2014 12:33:32 -0200 Subject: [PATCH 07/20] mx51evk: Fix MX51EVK_USB_CLK_EN_B definition As per the mx51evk schematics MX51EVK_USB_CLK_EN_B is GPIO2_1, not GPIO2_2. Signed-off-by: Fabio Estevam --- board/freescale/mx51evk/mx51evk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index f1e5eb433a..c7c21f392b 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -112,7 +112,7 @@ static void setup_iomux_spi(void) #ifdef CONFIG_USB_EHCI_MX5 #define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7) #define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27) -#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 2) +#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1) #define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5) static void setup_usb_h1(void) From 7ae350a0305de592faa8903255c988d4e6afb194 Mon Sep 17 00:00:00 2001 From: Jan Luebbe Date: Sun, 14 Dec 2014 16:34:49 +0100 Subject: [PATCH 08/20] arm: mxs: olinuxino: move DRAM config tuning to SPL The weak mxs_adjust_memory_params function is called from spl_mem_init.c, so it must be linked into the SPL to have an effect. Move it from mx23_olinuxino.c to spl_boot.c. This change was verified by reading back the register values. Signed-off-by: Jan Luebbe Cc: Marek Vasut Cc: Stefano Babic --- board/olimex/mx23_olinuxino/mx23_olinuxino.c | 30 -------------------- board/olimex/mx23_olinuxino/spl_boot.c | 30 ++++++++++++++++++++ 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 313ab20e26..65cbbf15b7 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -78,33 +78,3 @@ int board_init(void) return 0; } - -/* Fine-tune the DRAM configuration. */ -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* Enable Auto Precharge. */ - dram_vals[3] |= 1 << 8; - /* Enable Fast Writes. */ - dram_vals[5] |= 1 << 8; - /* tEMRS = 3*tCK */ - dram_vals[10] &= ~(0x3 << 8); - dram_vals[10] |= (0x3 << 8); - /* CASLAT = 3*tCK */ - dram_vals[11] &= ~(0x3 << 0); - dram_vals[11] |= (0x3 << 0); - /* tCKE = 1*tCK */ - dram_vals[12] &= ~(0x7 << 0); - dram_vals[12] |= (0x1 << 0); - /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ - dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0)); - dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0); - /* tDAL = 6*tCK */ - dram_vals[15] &= ~(0xf << 16); - dram_vals[15] |= (0x6 << 16); - /* tREF = 1040*tCK */ - dram_vals[26] &= ~0xffff; - dram_vals[26] |= 0x0410; - /* tRAS_MAX = 9334*tCK */ - dram_vals[32] &= ~0xffff; - dram_vals[32] |= 0x2475; -} diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 5272dfa4e6..de3b0e4c8b 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -89,3 +89,33 @@ void board_init_ll(const uint32_t arg, const uint32_t *resptr) { mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } + +/* Fine-tune the DRAM configuration. */ +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* Enable Auto Precharge. */ + dram_vals[3] |= 1 << 8; + /* Enable Fast Writes. */ + dram_vals[5] |= 1 << 8; + /* tEMRS = 3*tCK */ + dram_vals[10] &= ~(0x3 << 8); + dram_vals[10] |= (0x3 << 8); + /* CASLAT = 3*tCK */ + dram_vals[11] &= ~(0x3 << 0); + dram_vals[11] |= (0x3 << 0); + /* tCKE = 1*tCK */ + dram_vals[12] &= ~(0x7 << 0); + dram_vals[12] |= (0x1 << 0); + /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ + dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0)); + dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0); + /* tDAL = 6*tCK */ + dram_vals[15] &= ~(0xf << 16); + dram_vals[15] |= (0x6 << 16); + /* tREF = 1040*tCK */ + dram_vals[26] &= ~0xffff; + dram_vals[26] |= 0x0410; + /* tRAS_MAX = 9334*tCK */ + dram_vals[32] &= ~0xffff; + dram_vals[32] |= 0x2475; +} From 248802d4013243ec87062c871d58208169c03105 Mon Sep 17 00:00:00 2001 From: Pierre Aubert Date: Fri, 12 Dec 2014 14:38:22 +0100 Subject: [PATCH 09/20] imx SPL: enable boot from eMMC boot partitions. Signed-off-by: Pierre Aubert --- arch/arm/imx-common/spl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index 477c38c1e2..ac6e40e83b 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -68,8 +68,10 @@ u32 spl_boot_mode(void) /* for MMC return either RAW or FAT mode */ case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: -#ifdef CONFIG_SPL_FAT_SUPPORT +#if defined(CONFIG_SPL_FAT_SUPPORT) return MMCSD_MODE_FS; +#elif defined(CONFIG_SUPPORT_EMMC_BOOT) + return MMCSD_MODE_EMMCBOOT; #else return MMCSD_MODE_RAW; #endif From 729d2a34bd29d93e4735db04352d0470a9a922a5 Mon Sep 17 00:00:00 2001 From: Iain Paton Date: Sun, 14 Dec 2014 14:51:32 +0000 Subject: [PATCH 10/20] embestmx6boards: convert to use config_distro_defaults.h Update to use config_distro_defaults.h and remove explicit settings Signed-off-by: Iain Paton Tested-by: Nikolay Dimitrov --- include/configs/embestmx6boards.h | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 185edbe7fe..c62c8ecb27 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -78,14 +78,7 @@ #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET #define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR @@ -114,14 +107,12 @@ /* Command definition */ #include +#undef CONFIG_CMD_FPGA #define CONFIG_CMD_BMODE -#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_SETEXPR #undef CONFIG_CMD_IMLS -#define CONFIG_BOOTDELAY 1 - #define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 @@ -255,10 +246,7 @@ #define CONFIG_ARP_TIMEOUT 200UL /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Print Buffer Size */ @@ -272,7 +260,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_CMDLINE_EDITING #define CONFIG_STACKSIZE (128 * 1024) /* Physical Memory Map */ @@ -312,8 +299,6 @@ #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #endif -#define CONFIG_OF_LIBFDT - #ifndef CONFIG_SYS_DCACHE_OFF #define CONFIG_CMD_CACHE #endif @@ -335,4 +320,6 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#include + #endif /* __RIOTBOARD_CONFIG_H */ From c86efd85e99464f5dfe69b6477f9b0dfd7691063 Mon Sep 17 00:00:00 2001 From: Iain Paton Date: Sun, 14 Dec 2014 14:51:46 +0000 Subject: [PATCH 11/20] embestmx6boards: convert to use config_distro_bootcmd.h Since the Riot & Mars boards are dev boards it's likely people will want to run standard distros on them. So replace the current boot scripts with the standard one from config_distro_bootcmd.h Signed-off-by: Iain Paton Tested-by: Nikolay Dimitrov --- include/configs/embestmx6boards.h | 168 +++++++----------------------- 1 file changed, 39 insertions(+), 129 deletions(-) diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index c62c8ecb27..b4b3ae842f 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -116,133 +116,6 @@ #define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 -#ifdef CONFIG_SUPPORT_EMMC_BOOT -#define EMMC_ENV \ - "emmcdev=2\0" \ - "update_emmc_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "if mmc dev ${emmcdev}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" -#else -#define EMMC_ENV "" -#endif - -#ifdef CONFIG_CMD_SF -#define SF_ENV \ - "update_spi_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_spi_firmware_filename}; then " \ - "if sf probe; then " \ - "sf erase 0 0xc0000; " \ - "sf write ${loadaddr} 0x400 ${filesize}; " \ - "fi; " \ - "fi\0" -#else -#define SF_ENV "" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONFIG_CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - EMMC_ENV \ - SF_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - #define CONFIG_ARP_TIMEOUT 200UL /* Miscellaneous configurable options */ @@ -282,14 +155,14 @@ #if defined(CONFIG_ENV_IS_IN_MMC) /* RiOTboard */ -#define CONFIG_DEFAULT_FDT_FILE "imx6dl-riotboard.dtb" +#define CONFIG_FDTFILE "imx6dl-riotboard.dtb" #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) /* MarSBoard */ -#define CONFIG_DEFAULT_FDT_FILE "imx6q-marsboard.dtb" +#define CONFIG_FDTFILE "imx6q-marsboard.dtb" #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_ENV_OFFSET (768 * 1024) #define CONFIG_ENV_SECT_SIZE (8 * 1024) @@ -322,4 +195,41 @@ #include +/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, + * 1M script, 1M pxe and the ramdisk at the end */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x12000000\0" \ + "fdt_addr_r=0x13000000\0" \ + "scriptaddr=0x13100000\0" \ + "pxefile_addr_r=0x13200000\0" \ + "ramdisk_addr_r=0x13300000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" + +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + BOOTENV + #endif /* __RIOTBOARD_CONFIG_H */ From cd3c5896b6582e73cf6a6d48c7ecc29924fa3089 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:16 +0100 Subject: [PATCH 12/20] imx: i2c: Zap unnecessary malloc() calls The malloc() calls are unnecessary, just allocate the stuff on stack. While at it, reorder the code a little, so that only one variable is used for the text, use snprintf() instead of sprintf() and use %01d as a formatting string to avoid any possible overflows. Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey Reviewed-by: Christian Gmeiner --- arch/arm/imx-common/i2c-mxv7.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c index 34f53872e8..1a632e7203 100644 --- a/arch/arm/imx-common/i2c-mxv7.c +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -73,26 +73,21 @@ static void * const i2c_bases[] = { int setup_i2c(unsigned i2c_index, int speed, int slave_addr, struct i2c_pads_info *p) { - char *name1, *name2; + char name[9]; int ret; if (i2c_index >= ARRAY_SIZE(i2c_bases)) return -EINVAL; - name1 = malloc(9); - name2 = malloc(9); - if (!name1 || !name2) - return -ENOMEM; - - sprintf(name1, "i2c_sda%d", i2c_index); - sprintf(name2, "i2c_scl%d", i2c_index); - ret = gpio_request(p->sda.gp, name1); + snprintf(name, sizeof(name), "i2c_sda%01d", i2c_index); + ret = gpio_request(p->sda.gp, name); if (ret) - goto err_req1; + return ret; - ret = gpio_request(p->scl.gp, name2); + snprintf(name, sizeof(name), "i2c_scl%01d", i2c_index); + ret = gpio_request(p->scl.gp, name); if (ret) - goto err_req2; + goto err_req; /* Enable i2c clock */ ret = enable_i2c_clk(1, i2c_index); @@ -112,11 +107,8 @@ int setup_i2c(unsigned i2c_index, int speed, int slave_addr, err_idle: err_clk: gpio_free(p->scl.gp); -err_req2: +err_req: gpio_free(p->sda.gp); -err_req1: - free(name1); - free(name2); return ret; } From 7efefa9bd6dabaf0dcf4aa5f20254e2a9d99aaa8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:17 +0100 Subject: [PATCH 13/20] arm: mx6: gw_ventana: Define CONFIG_SYS_MALLOC_F_LEN This board uses setup_i2c() in SPL. The setup_i2c() function internally calls gpio_request(), which in turn internally calls strdup(). The strdup() requires a running mallocator, so this patch makes the mallocator available. Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey --- include/configs/gw_ventana.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 620f9501d2..4f137fc96b 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -39,6 +39,7 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* Init Functions */ #define CONFIG_BOARD_EARLY_INIT_F From 8744d3b98f4d798b070b9d303e17804611f1e852 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:18 +0100 Subject: [PATCH 14/20] arm: mx6: novena: Define CONFIG_SYS_MALLOC_F_LEN This board uses setup_i2c() in SPL. The setup_i2c() function internally calls gpio_request(), which in turn internally calls strdup(). The strdup() requires a running mallocator, so this patch makes the mallocator available. Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey --- include/configs/novena.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/novena.h b/include/configs/novena.h index 879141a7ca..0f3621a41b 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -115,6 +115,7 @@ #define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* SPL */ #define CONFIG_SPL_FAT_SUPPORT From 998e121a2edc86f792f376cfc2337a6d9218427c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:19 +0100 Subject: [PATCH 15/20] arm: mx6: novena: Minor coding style fix Just zap multiple spaces and replace them with tabs properly. Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey --- board/kosagi/novena/novena.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index 6add9e5265..e303a57276 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -172,19 +172,19 @@ struct display_info_t const displays[] = { .detect = detect_hdmi, .enable = enable_hdmi, .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } } }; From 00ff950ab775410ee9131f39730f3e503e9911da Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:20 +0100 Subject: [PATCH 16/20] arm: mx6: novena: Minor config file fix Sequence like the following is completely useless and results from an errorneous ordering of the statements during development. Zap it. #ifdef FOO #define FOO Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey --- include/configs/novena.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/novena.h b/include/configs/novena.h index 0f3621a41b..4924cbfe06 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -226,7 +226,6 @@ /* Video output */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE From d59d7b915eb7c891c06e71e7b2a4967c3a488e94 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:21 +0100 Subject: [PATCH 17/20] arm: mx6: novena: Pull GPIO definitions into header Pull the definitions of GPIOs into a separate header file, so that they can be used across all source files. Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey --- board/kosagi/novena/novena.c | 6 ++---- board/kosagi/novena/novena.h | 23 +++++++++++++++++++++++ board/kosagi/novena/novena_spl.c | 10 ++-------- 3 files changed, 27 insertions(+), 12 deletions(-) create mode 100644 board/kosagi/novena/novena.h diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index e303a57276..5493e07c02 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -36,11 +36,9 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; +#include "novena.h" -#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14) -#define NOVENA_SD_WP IMX_GPIO_NR(1, 2) -#define NOVENA_SD_CD IMX_GPIO_NR(1, 4) +DECLARE_GLOBAL_DATA_PTR; /* * GPIO button diff --git a/board/kosagi/novena/novena.h b/board/kosagi/novena/novena.h new file mode 100644 index 0000000000..6613ad469f --- /dev/null +++ b/board/kosagi/novena/novena.h @@ -0,0 +1,23 @@ +/* + * Novena board support + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOARD_KOSAGI_NOVENA_NOVENA_H__ +#define __BOARD_KOSAGI_NOVENA_NOVENA_H__ + +#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) +#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14) +#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) +#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) +#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) +#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) +#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) +#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22) +#define NOVENA_SD_CD IMX_GPIO_NR(1, 4) +#define NOVENA_SD_WP IMX_GPIO_NR(1, 2) + +#endif /* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */ diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index c07735ad03..5ebc59b970 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -25,6 +25,8 @@ #include +#include "novena.h" + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL \ @@ -68,14 +70,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) -#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) -#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) -#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) -#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) -#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22) -#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) - /* * Audio */ From f2e4d6a58cafb219b1850c3db1238887109cd94d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:22 +0100 Subject: [PATCH 18/20] arm: mx6: novena: Pull video handling into separate file Pull all of the video handling into a separate file, since a lot more code will be added and such code would polute the board file. Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey --- board/kosagi/novena/Makefile | 1 + board/kosagi/novena/novena.c | 79 +-------------------------- board/kosagi/novena/novena.h | 2 + board/kosagi/novena/video.c | 102 +++++++++++++++++++++++++++++++++++ 4 files changed, 106 insertions(+), 78 deletions(-) create mode 100644 board/kosagi/novena/video.c diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile index 6fba17718b..6893b6311d 100644 --- a/board/kosagi/novena/Makefile +++ b/board/kosagi/novena/Makefile @@ -8,4 +8,5 @@ ifdef CONFIG_SPL_BUILD obj-y := novena_spl.o else obj-y := novena.o +obj-$(CONFIG_VIDEO_IPUV3) += video.o endif diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index 5493e07c02..e7a6adb611 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -152,87 +152,10 @@ int board_mmc_init(bd_t *bis) } #endif -/* - * Video over HDMI - */ -#if defined(CONFIG_VIDEO_IPUV3) -static void enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -struct display_info_t const displays[] = { - { - /* HDMI Output */ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED - } - } -}; - -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - enable_ipu_clock(); - imx_setup_hdmi(); - - /* Turn on LDB0,IPU,IPU DI0 clocks */ - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); - - /* set LDB0, LDB1 clk select to 011/011 */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK, - (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); - - setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); - - setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - - writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | - IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, - &iomux->gpr[2]); - - clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, - IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); -} -#endif - int board_early_init_f(void) { #if defined(CONFIG_VIDEO_IPUV3) - setup_display(); + setup_display_clock(); #endif return 0; diff --git a/board/kosagi/novena/novena.h b/board/kosagi/novena/novena.h index 6613ad469f..244004d694 100644 --- a/board/kosagi/novena/novena.h +++ b/board/kosagi/novena/novena.h @@ -20,4 +20,6 @@ #define NOVENA_SD_CD IMX_GPIO_NR(1, 4) #define NOVENA_SD_WP IMX_GPIO_NR(1, 2) +void setup_display_clock(void); + #endif /* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */ diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c new file mode 100644 index 0000000000..fdcd100e43 --- /dev/null +++ b/board/kosagi/novena/video.c @@ -0,0 +1,102 @@ +/* + * Novena video output support + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "novena.h" + +static void enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = { + { + /* HDMI Output */ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + }, + }, +}; + +size_t display_count = ARRAY_SIZE(displays); + +void setup_display_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + /* set LDB0, LDB1 clk select to 011/011 */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK, + (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); + + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, + IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); +} From 331ae846ad9fee532cf04268da76701093e4e4ed Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:23 +0100 Subject: [PATCH 19/20] arm: mx6: novena: Add proper LVDS display support Repair the register configuration and add proper support for the display attached to both LVDS channels. Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey --- board/kosagi/novena/novena.c | 8 + board/kosagi/novena/novena.h | 8 + board/kosagi/novena/novena_spl.c | 7 + board/kosagi/novena/video.c | 394 +++++++++++++++++++++++++++++-- include/configs/novena.h | 1 + 5 files changed, 398 insertions(+), 20 deletions(-) diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index e7a6adb611..69f5be3b9c 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -173,6 +173,14 @@ int board_init(void) return 0; } +int board_late_init(void) +{ +#if defined(CONFIG_VIDEO_IPUV3) + setup_display_lvds(); +#endif + return 0; +} + int checkboard(void) { puts("Board: Novena 4x\n"); diff --git a/board/kosagi/novena/novena.h b/board/kosagi/novena/novena.h index 244004d694..8f11583c2d 100644 --- a/board/kosagi/novena/novena.h +++ b/board/kosagi/novena/novena.h @@ -10,9 +10,12 @@ #define __BOARD_KOSAGI_NOVENA_NOVENA_H__ #define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) +#define NOVENA_BACKLIGHT_PWM_GPIO IMX_GPIO_NR(4, 29) +#define NOVENA_BACKLIGHT_PWR_GPIO IMX_GPIO_NR(4, 15) #define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14) #define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) #define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) +#define NOVENA_ITE6251_PWR_GPIO IMX_GPIO_NR(5, 28) #define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) #define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) #define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) @@ -20,6 +23,11 @@ #define NOVENA_SD_CD IMX_GPIO_NR(1, 4) #define NOVENA_SD_WP IMX_GPIO_NR(1, 2) +#define NOVENA_IT6251_I2C_BUS 2 +#define NOVENA_IT6251_CHIPADDR 0x5c +#define NOVENA_IT6251_LVDSADDR 0x5e + void setup_display_clock(void); +void setup_display_lvds(void); #endif /* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */ diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index 5ebc59b970..b1688e0295 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -386,6 +386,13 @@ static void novena_spl_setup_iomux_uart(void) static iomux_v3_cfg_t hdmi_pads[] = { /* "Ghost HPD" pin */ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* LCD_PWR_CTL */ + MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LCD_BL_ON */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPIO_PWM1 */ + MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void novena_spl_setup_iomux_video(void) diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c index fdcd100e43..3bb1b7180b 100644 --- a/board/kosagi/novena/video.c +++ b/board/kosagi/novena/video.c @@ -1,6 +1,10 @@ /* * Novena video output support * + * IT6251 code based on code Copyright (C) 2014 Sean Cross + * from https://github.com/xobs/novena-linux.git commit + * 3d85836ee1377d445531928361809612aa0a18db + * * Copyright (C) 2014 Marek Vasut * * SPDX-License-Identifier: GPL-2.0+ @@ -29,11 +33,275 @@ #include "novena.h" +#define IT6251_VENDOR_ID_LOW 0x00 +#define IT6251_VENDOR_ID_HIGH 0x01 +#define IT6251_DEVICE_ID_LOW 0x02 +#define IT6251_DEVICE_ID_HIGH 0x03 +#define IT6251_SYSTEM_STATUS 0x0d +#define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0) +#define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1) +#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2) +#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3) +#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4) +#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5) +#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6) +#define IT6251_REF_STATE 0x0e +#define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0) +#define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1) +#define IT6251_REF_STATE_CR_PATTERN (1 << 2) +#define IT6251_REF_STATE_EQ_PATTERN (1 << 3) +#define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4) +#define IT6251_REF_STATE_MUTED (1 << 5) + +#define IT6251_REG_PCLK_CNT_LOW 0x57 +#define IT6251_REG_PCLK_CNT_HIGH 0x58 + +#define IT6521_RETRY_MAX 20 + +static int it6251_is_stable(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + const unsigned int laddr = NOVENA_IT6251_LVDSADDR; + int status; + int clkcnt; + int rpclkcnt; + int refstate; + + rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) | + ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00); + debug("RPCLKCnt: %d\n", rpclkcnt); + + status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS); + debug("System status: 0x%02x\n", status); + + clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) | + ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) & + 0x0f00); + debug("Clock: 0x%02x\n", clkcnt); + + refstate = i2c_reg_read(laddr, IT6251_REF_STATE); + debug("Ref Link State: 0x%02x\n", refstate); + + if ((refstate & 0x1f) != 0) + return 0; + + /* If video is muted, that's a failure */ + if (refstate & IT6251_REF_STATE_MUTED) + return 0; + + if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE)) + return 0; + + return 1; +} + +static int it6251_ready(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + + /* Test if the IT6251 came out of reset by reading ID regs. */ + if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15) + return 0; + if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca) + return 0; + if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51) + return 0; + if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62) + return 0; + + return 1; +} + +static void it6251_program_regs(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + const unsigned int laddr = NOVENA_IT6251_LVDSADDR; + + i2c_reg_write(caddr, 0x05, 0x00); + mdelay(1); + + /* set LVDSRX address, and enable */ + i2c_reg_write(caddr, 0xfd, 0xbc); + i2c_reg_write(caddr, 0xfe, 0x01); + + /* + * LVDSRX + */ + /* This write always fails, because the chip goes into reset */ + /* reset LVDSRX */ + i2c_reg_write(laddr, 0x05, 0xff); + i2c_reg_write(laddr, 0x05, 0x00); + + /* reset LVDSRX PLL */ + i2c_reg_write(laddr, 0x3b, 0x42); + i2c_reg_write(laddr, 0x3b, 0x43); + + /* something with SSC PLL */ + i2c_reg_write(laddr, 0x3c, 0x08); + /* don't swap links, but writing reserved registers */ + i2c_reg_write(laddr, 0x0b, 0x88); + + /* JEIDA, 8-bit depth 0x11, orig 0x42 */ + i2c_reg_write(laddr, 0x2c, 0x01); + /* "reserved" */ + i2c_reg_write(laddr, 0x32, 0x04); + /* "reserved" */ + i2c_reg_write(laddr, 0x35, 0xe0); + /* "reserved" + clock delay */ + i2c_reg_write(laddr, 0x2b, 0x24); + + /* reset LVDSRX pix clock */ + i2c_reg_write(laddr, 0x05, 0x02); + i2c_reg_write(laddr, 0x05, 0x00); + + /* + * DPTX + */ + /* set for two lane mode, normal op, no swapping, no downspread */ + i2c_reg_write(caddr, 0x16, 0x02); + + /* some AUX channel EDID magic */ + i2c_reg_write(caddr, 0x23, 0x40); + + /* power down lanes 3-0 */ + i2c_reg_write(caddr, 0x5c, 0xf3); + + /* enable DP scrambling, change EQ CR phase */ + i2c_reg_write(caddr, 0x5f, 0x06); + + /* color mode RGB, pclk/2 */ + i2c_reg_write(caddr, 0x60, 0x02); + /* dual pixel input mode, no EO swap, no RGB swap */ + i2c_reg_write(caddr, 0x61, 0x04); + /* M444B24 video format */ + i2c_reg_write(caddr, 0x62, 0x01); + + /* vesa range / not interlace / vsync high / hsync high */ + i2c_reg_write(caddr, 0xa0, 0x0F); + + /* hpd event timer set to 1.6-ish ms */ + i2c_reg_write(caddr, 0xc9, 0xf5); + + /* more reserved magic */ + i2c_reg_write(caddr, 0xca, 0x4d); + i2c_reg_write(caddr, 0xcb, 0x37); + + /* enhanced framing mode, auto video fifo reset, video mute disable */ + i2c_reg_write(caddr, 0xd3, 0x03); + + /* "vidstmp" and some reserved stuff */ + i2c_reg_write(caddr, 0xd4, 0x45); + + /* queue number -- reserved */ + i2c_reg_write(caddr, 0xe7, 0xa0); + /* info frame packets and reserved */ + i2c_reg_write(caddr, 0xe8, 0x33); + /* more AVI stuff */ + i2c_reg_write(caddr, 0xec, 0x00); + + /* select PC master reg for aux channel? */ + i2c_reg_write(caddr, 0x23, 0x42); + + /* send PC request commands */ + i2c_reg_write(caddr, 0x24, 0x00); + i2c_reg_write(caddr, 0x25, 0x00); + i2c_reg_write(caddr, 0x26, 0x00); + + /* native aux read */ + i2c_reg_write(caddr, 0x2b, 0x00); + /* back to internal */ + i2c_reg_write(caddr, 0x23, 0x40); + + /* voltage swing level 3 */ + i2c_reg_write(caddr, 0x19, 0xff); + /* pre-emphasis level 3 */ + i2c_reg_write(caddr, 0x1a, 0xff); + + /* start link training */ + i2c_reg_write(caddr, 0x17, 0x01); +} + +static int it6251_init(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + int reg; + int tries, retries = 0; + + for (retries = 0; retries < IT6521_RETRY_MAX; retries++) { + /* Program the chip. */ + it6251_program_regs(); + + /* Wait for video stable. */ + for (tries = 0; tries < 100; tries++) { + reg = i2c_reg_read(caddr, 0x17); + /* Test Link CFG, STS, LCS read done. */ + if ((reg & 0xe0) != 0xe0) { + /* Not yet, wait a bit more. */ + mdelay(2); + continue; + } + + /* Test if the video input is stable. */ + if (it6251_is_stable()) + return 0; + } + /* + * If we couldn't stabilize, requeue and try again, + * because it means that the LVDS channel isn't + * stable yet. + */ + printf("Display didn't stabilize.\n"); + printf("This may be because the LVDS port is still in powersave mode.\n"); + mdelay(50); + } + + return -EINVAL; +} + static void enable_hdmi(struct display_info_t const *dev) { imx_enable_hdmi_phy(); } +static int lvds_enabled; + +static void enable_lvds(struct display_info_t const *dev) +{ + if (lvds_enabled) + return; + + /* ITE IT6251 power enable. */ + gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0); + mdelay(10); + gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1); + mdelay(20); + lvds_enabled = 1; +} + +static int detect_lvds(struct display_info_t const *dev) +{ + int ret, loops = 250; + + enable_lvds(dev); + + ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); + if (ret) { + puts("Cannot select IT6251 I2C bus.\n"); + return 0; + } + + /* Wait up-to ~250 mS for the LVDS to come up. */ + while (--loops) { + ret = it6251_ready(); + if (ret) + return ret; + + mdelay(1); + } + + return 0; +} + struct display_info_t const displays[] = { { /* HDMI Output */ @@ -57,46 +325,132 @@ struct display_info_t const displays[] = { .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED }, + }, { + /* LVDS Output: N133HSE-EA1 Rev. C1 */ + .bus = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_lvds, + .enable = enable_lvds, + .mode = { + .name = "Chimei-FHD", + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 15384, + .left_margin = 148, + .right_margin = 88, + .upper_margin = 36, + .lower_margin = 4, + .hsync_len = 44, + .vsync_len = 5, + .sync = FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, + }, }, }; size_t display_count = ARRAY_SIZE(displays); +static void enable_vpll(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int timeout = 100000; + + setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_DIV_SELECT | + BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, + BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | + BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1)); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_BYPASS, + BM_ANADIG_PLL_VIDEO_ENABLE); +} + void setup_display_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; enable_ipu_clock(); + enable_vpll(); imx_setup_hdmi(); - /* Turn on LDB0,IPU,IPU DI0 clocks */ + /* Turn on IPU LDB DI0 clocks */ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); - /* set LDB0, LDB1 clk select to 011/011 */ + /* Switch LDB DI0 to PLL5 (Video PLL) */ clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK, - (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, + (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); - setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + /* LDB clock div by 3.5 */ + clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); - setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + /* DI0 clock derived from ldb_di0_clk */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + ); - writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | - IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | + /* Enable both LVDS channels, both connected to DI0. */ + writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA | + IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_SPLIT_MODE_EN_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, &iomux->gpr[2]); - clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, - IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_LVDS1_MUX_CTL_MASK, + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) + ); +} + +void setup_display_lvds(void) +{ + int ret; + + ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); + if (ret) { + puts("Cannot select LVDS-to-eDP I2C bus.\n"); + return; + } + + /* The IT6251 should be ready now, if it's not, it's not connected. */ + ret = it6251_ready(); + if (!ret) + return; + + /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */ + ret = it6251_init(); + if (!ret) { + /* Backlight power enable. */ + gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1); + /* PWM backlight pin, always on for full brightness. */ + gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1); + } } diff --git a/include/configs/novena.h b/include/configs/novena.h index 4924cbfe06..ea75d2c2b9 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -12,6 +12,7 @@ /* System configurations */ #define CONFIG_MX6 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MISC_INIT_R #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_CPUINFO From 87e47e905887b91c0505495cc6bbab70ba266d51 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 29 Dec 2014 18:05:44 -0200 Subject: [PATCH 20/20] mx6slevk: Remove get_board_rev() get_board_rev() just returns the cpu revision, which does not make it really useful for distinguishing between revisions of the board. Let's get rid of get_board_rev() as it is not being used with its correct meaning. Signed-off-by: Fabio Estevam --- board/freescale/mx6slevk/mx6slevk.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 3834eec60e..838ea6c0f0 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -308,11 +308,6 @@ int board_init(void) return 0; } -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int checkboard(void) { puts("Board: MX6SLEVK\n");