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arm: mx5: Add more register definitions
Add register definitions require for video configuration. Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Reviewed-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
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@ -210,6 +210,14 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
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#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
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/* Define the bits in register CSCMR2 */
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#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26
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#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26)
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#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26)
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#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7)
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#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
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/* Define the bits in register CSCDR2 */
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#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
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#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
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@ -416,6 +416,39 @@ struct iomuxc {
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};
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#endif
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#define IOMUXC_GPR2_BITMAP_SPWG 0
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#define IOMUXC_GPR2_BITMAP_JEIDA 1
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#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
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#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
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#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \
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IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
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#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \
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IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
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#define IOMUXC_GPR2_DATA_WIDTH_18 0
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#define IOMUXC_GPR2_DATA_WIDTH_24 1
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#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
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#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
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#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \
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IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
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#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \
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IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
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#define IOMUXC_GPR2_MODE_DISABLED 0
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#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
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#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
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#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
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#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
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#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
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IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
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#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \
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IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
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#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \
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IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
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/* System Reset Controller (SRC) */
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struct src {
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u32 scr;
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