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https://github.com/brain-hackers/u-boot-brain
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ARC: [plat-hsdk]: migrate to DM_MMC
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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15736e288e
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@ -86,6 +86,32 @@
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reg = <0xf0060000 0x100>;
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reg = <0xf0060000 0x100>;
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};
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};
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mmcclk_ciu: mmcclk-ciu {
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compatible = "fixed-clock";
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/*
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* DW sdio controller has external ciu clock divider
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* controlled via register in SDIO IP. Due to its
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* unexpected default value (it should divide by 1
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* but it divides by 8) SDIO IP uses wrong clock and
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* works unstable (see STAR 9001204800)
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* We switched to the minimum possible value of the
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* divisor (div-by-2) in HSDK platform code.
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* So default mmcclk ciu clock is 50000000 Hz.
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*/
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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mmc: mmc0@f000a000 {
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compatible = "snps,dw-mshc";
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reg = <0xf000a000 0x400>;
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bus-width = <4>;
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fifo-depth = <256>;
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clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
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clock-names = "biu", "ciu";
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max-frequency = <25000000>;
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};
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spi0: spi@f0020000 {
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spi0: spi@f0020000 {
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compatible = "snps,dw-apb-ssi";
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compatible = "snps,dw-apb-ssi";
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reg = <0xf0020000 0x1000>;
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reg = <0xf0020000 0x1000>;
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@ -982,6 +982,12 @@ int board_early_init_f(void)
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*/
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*/
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init_memory_bridge();
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init_memory_bridge();
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/*
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* Switch SDIO external ciu clock divider from default div-by-8 to
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* minimum possible div-by-2.
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*/
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writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
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return 0;
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return 0;
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}
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}
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@ -1019,41 +1025,6 @@ int board_late_init(void)
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return 0;
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return 0;
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}
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct dwmci_host *host = mmc->priv;
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return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
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}
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int board_mmc_init(bd_t *bis)
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{
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struct dwmci_host *host = NULL;
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host = malloc(sizeof(struct dwmci_host));
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if (!host) {
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printf("dwmci_host malloc fail!\n");
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return 1;
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}
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/*
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* Switch SDIO external ciu clock divider from default div-by-8 to
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* minimum possible div-by-2.
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*/
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writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
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memset(host, 0, sizeof(struct dwmci_host));
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host->name = "Synopsys Mobile storage";
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host->ioaddr = (void *)ARC_DWMMC_BASE;
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host->buswidth = 4;
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host->dev_index = 0;
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host->bus_hz = 50000000;
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add_dwmci(host, host->bus_hz / 2, 400000);
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return 0;
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}
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int checkboard(void)
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int checkboard(void)
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{
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{
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puts("Board: Synopsys ARC HS Development Kit\n");
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puts("Board: Synopsys ARC HS Development Kit\n");
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@ -38,7 +38,9 @@ CONFIG_CLK_HSDK=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_GPIO=y
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CONFIG_HSDK_CREG_GPIO=y
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CONFIG_HSDK_CREG_GPIO=y
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CONFIG_MMC=y
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CONFIG_MMC=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_SNPS=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_SST=y
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CONFIG_SPI_FLASH_SST=y
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