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spi: fsl_qspi: support i.MX6UL/6ULLL/7D

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The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.

The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.

Add the compatible entry for 6ul/7d.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit afe8e1b033)
This commit is contained in:
Peng Fan 2018-01-03 08:52:02 +08:00 committed by Otavio Salvador
parent 462ad4138f
commit 54602c7f6b
1 changed files with 16 additions and 2 deletions
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18
drivers/spi/fsl_qspi.c
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@ -20,7 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
#define RX_BUFFER_SIZE 0x80
#ifdef CONFIG_MX6SX
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
#define TX_BUFFER_SIZE 0x200
#else
#define TX_BUFFER_SIZE 0x40
@ -268,7 +269,8 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#endif
#ifdef CONFIG_MX6SX
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
/*
* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
* So, Use IDATSZ in IPCR to determine the size and here set 0.
@ -905,6 +907,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
qspi->slave.max_write_size = TX_BUFFER_SIZE;
mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
/* Set endianness to LE for i.mx */
if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
mcr_val = QSPI_MCR_END_CFD_LE;
qspi_write32(qspi->priv.flags, &regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
(mcr_val & QSPI_MCR_END_CFD_MASK));
@ -1023,6 +1030,11 @@ static int fsl_qspi_probe(struct udevice *bus)
}
mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
/* Set endianness to LE for i.mx */
if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
mcr_val = QSPI_MCR_END_CFD_LE;
qspi_write32(priv->flags, &priv->regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
(mcr_val & QSPI_MCR_END_CFD_MASK));
@ -1227,6 +1239,8 @@ static const struct dm_spi_ops fsl_qspi_ops = {
static const struct udevice_id fsl_qspi_ids[] = {
{ .compatible = "fsl,vf610-qspi" },
{ .compatible = "fsl,imx6sx-qspi" },
{ .compatible = "fsl,imx6ul-qspi" },
{ .compatible = "fsl,imx7d-qspi" },
{ }
};