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DaVinci DM6467: Fix Build Error

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This commit fixes build errors on the DM6467 port.


Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Sandeep Paulraj 2010-12-29 14:31:26 -05:00 committed by Albert Aribaud
parent b157dd51de
commit 5342a710c9
1 changed files with 16 additions and 0 deletions
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16
arch/arm/cpu/arm926ejs/davinci/cpu.c
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@ -60,6 +60,12 @@
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
#ifdef CONFIG_SOC_DM646X
#define DSP_PLLDIV PLLC_PLLDIV1
#define ARM_PLLDIV PLLC_PLLDIV2
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
#ifdef CONFIG_SOC_DA8XX
const dv_reg * const sysdiv[7] = {
&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
@ -145,7 +151,11 @@ static inline unsigned pll_postdiv(volatile void *pllbase)
static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
{
volatile void *pllbase = (volatile void *) pll_addr;
#ifdef CONFIG_SOC_DM646X
unsigned base = CFG_REFCLK_FREQ / 1000;
#else
unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
#endif
/* the PLL might be bypassed */
if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
@ -176,6 +186,12 @@ int print_cpuinfo(void)
return 0;
}
#ifdef DAVINCI_DM6467EVM
unsigned int davinci_arm_clk_get()
{
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
}
#endif
#endif
/*