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rockchip: clk: Add mention of four new clocks

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These clocks are needed to get MMC running. We don't actually support
setting them yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Simon Glass 2019-01-21 14:53:30 -07:00 committed by Philipp Tomsich
parent cf5c8d1880
commit 5328af1774
1 changed files with 12 additions and 0 deletions
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12
drivers/clk/rockchip/clk_rk3399.c
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@ -925,7 +925,13 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_SARADC:
rate = rk3399_saradc_get_clk(priv->cru);
break;
case ACLK_VIO:
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
break;
default:
log_debug("Unknown clock %lu\n", clk->id);
return -ENOENT;
}
@ -993,7 +999,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SARADC:
ret = rk3399_saradc_set_clk(priv->cru, rate);
break;
case ACLK_VIO:
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
return 0;
default:
log_debug("Unknown clock %lu\n", clk->id);
return -ENOENT;
}