mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Update header file. Include dtimer_intr_setup(). Changed timer divider to global define.
Include immap.h and timer.h. Moved dtimer interrupt setup to dtimer_intr_setup() from cpu/mcf532x/interrupts.c. Changed (CFG_CLK /1000000) -1 << 8 to CFG_TIMER_PRESCALER Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew
John Rigby
parent
5cdc07c7ef
commit
52b017604a
120
lib_m68k/time.c
120
lib_m68k/time.c
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@ -26,6 +26,8 @@
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#include <common.h>
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#include <asm/mcftimer.h>
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#include <asm/timer.h>
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#include <asm/immap.h>
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#ifdef CONFIG_M5271
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#include <asm/m5271.h>
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@ -71,8 +73,10 @@ void udelay(unsigned long usec)
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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timerp->timer_tcn = 0;
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/* set period to 1 us */
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timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
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MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
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timerp->timer_tmr =
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(((CFG_CLK / 1000000) -
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1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN |
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MCFTIMER_TMR_ENABLE;
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start = now = timerp->timer_tcn;
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while (now < start + tmp)
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@ -80,7 +84,8 @@ void udelay(unsigned long usec)
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}
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}
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void mcf_timer_interrupt (void * not_used){
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void mcf_timer_interrupt(void *not_used)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
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volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
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@ -91,10 +96,11 @@ void mcf_timer_interrupt (void * not_used){
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/* reset timer */
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timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
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timestamp ++;
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timestamp++;
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}
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void timer_init (void) {
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void timer_init(void)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
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volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
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@ -104,27 +110,29 @@ void timer_init (void) {
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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/* initialize and enable timer 4 interrupt */
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irq_install_handler (72, mcf_timer_interrupt, 0);
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irq_install_handler(72, mcf_timer_interrupt, 0);
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intp->int_icr1 |= 0x0000000d;
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timerp->timer_tcn = 0;
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timerp->timer_trr = 1000; /* Interrupt every ms */
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
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timerp->timer_tmr =
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(((CFG_CLK / 1000000) -
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1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART |
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MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
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}
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void reset_timer (void)
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void reset_timer(void)
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{
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timestamp = 0;
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}
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ulong get_timer (ulong base)
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ulong get_timer(ulong base)
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{
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return (timestamp - base);
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}
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void set_timer (ulong t)
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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@ -137,7 +145,7 @@ void udelay(unsigned long usec)
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volatile unsigned short *timerp;
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uint tmp;
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timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);
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timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE3);
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while (usec > 0) {
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if (usec > 65000)
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@ -152,21 +160,21 @@ void udelay(unsigned long usec)
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/* set period to 1 us */
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timerp[MCFTIMER_PCSR] =
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#ifdef CONFIG_M5271
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(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#else /* !CONFIG_M5271 */
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(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#endif /* CONFIG_M5271 */
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(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#else /* !CONFIG_M5271 */
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(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#endif /* CONFIG_M5271 */
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timerp[MCFTIMER_PMR] = tmp;
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while (timerp[MCFTIMER_PCNTR] > 0);
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while (timerp[MCFTIMER_PCNTR] > 0) ;
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}
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}
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void timer_init (void)
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void timer_init(void)
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{
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volatile unsigned short *timerp;
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timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
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timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
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timestamp = 0;
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/* Set up TIMER 4 as poll clock */
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@ -174,27 +182,27 @@ void timer_init (void)
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timerp[MCFTIMER_PMR] = lastinc = 0;
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timerp[MCFTIMER_PCSR] =
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#ifdef CONFIG_M5271
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(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#else /* !CONFIG_M5271 */
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(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#endif /* CONFIG_M5271 */
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(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#else /* !CONFIG_M5271 */
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(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
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#endif /* CONFIG_M5271 */
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}
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void set_timer (ulong t)
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void set_timer(ulong t)
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{
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volatile unsigned short *timerp;
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timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
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timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
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timestamp = 0;
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timerp[MCFTIMER_PMR] = lastinc = 0;
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}
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ulong get_timer (ulong base)
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ulong get_timer(ulong base)
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{
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unsigned short now, diff;
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volatile unsigned short *timerp;
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timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
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timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
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now = timerp[MCFTIMER_PCNTR];
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diff = -(now - lastinc);
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@ -203,14 +211,13 @@ ulong get_timer (ulong base)
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return timestamp - base;
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}
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void wait_ticks (unsigned long ticks)
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void wait_ticks(unsigned long ticks)
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{
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set_timer (0);
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while (get_timer (0) < ticks);
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set_timer(0);
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while (get_timer(0) < ticks) ;
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}
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#endif
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#if defined(CONFIG_M5249)
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/*
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* We use timer 1 which is running with a period of 1 us
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@ -232,8 +239,10 @@ void udelay(unsigned long usec)
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timerp->timer_tcn = 0;
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/* set period to 1 us */
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/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
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timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
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MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
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timerp->timer_tmr =
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(((CFG_CLK / 2000000) -
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1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN |
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MCFTIMER_TMR_ENABLE;
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start = now = timerp->timer_tcn;
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while (now < start + tmp)
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@ -241,7 +250,8 @@ void udelay(unsigned long usec)
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}
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}
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void mcf_timer_interrupt (void * not_used){
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void mcf_timer_interrupt(void *not_used)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
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/* check for timer 2 interrupts */
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@ -251,10 +261,11 @@ void mcf_timer_interrupt (void * not_used){
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/* reset timer */
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timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
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timestamp ++;
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timestamp++;
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}
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void timer_init (void) {
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void timer_init(void)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
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timestamp = 0;
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@ -263,29 +274,33 @@ void timer_init (void) {
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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/* initialize and enable timer 2 interrupt */
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irq_install_handler (31, mcf_timer_interrupt, 0);
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irq_install_handler(31, mcf_timer_interrupt, 0);
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mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
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mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3);
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mbar_writeByte(MCFSIM_TIMER2ICR,
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MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 |
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MCFSIM_ICR_PRI3);
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timerp->timer_tcn = 0;
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timerp->timer_trr = 1000; /* Interrupt every ms */
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
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timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
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timerp->timer_tmr =
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(((CFG_CLK / 2000000) -
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1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART |
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MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
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}
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void reset_timer (void)
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void reset_timer(void)
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{
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timestamp = 0;
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}
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ulong get_timer (ulong base)
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ulong get_timer(ulong base)
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{
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return (timestamp - base);
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}
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void set_timer (ulong t)
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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@ -299,12 +314,7 @@ void set_timer (ulong t)
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#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK)
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# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
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#endif
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#include <asm/immap_5329.h>
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extern void dtimer_interrupt(void *not_used);
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extern void dtimer_interrupt_setup(void);
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extern void dtimer_interrupt_enable(void);
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extern void dtimer_intr_setup(void);
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void udelay(unsigned long usec)
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{
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@ -323,8 +333,8 @@ void udelay(unsigned long usec)
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timerp->tcn = 0;
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/* set period to 1 us */
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timerp->tmr =
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(((CFG_CLK / 1000000) -
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1) << 8) | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | DTIM_DTMR_RST_EN;
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CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
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DTIM_DTMR_RST_EN;
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start = now = timerp->tcn;
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while (now < start + tmp)
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@ -348,7 +358,6 @@ void dtimer_interrupt(void *not_used)
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void timer_init(void)
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{
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volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
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volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
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timestamp = 0;
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@ -358,14 +367,13 @@ void timer_init(void)
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/* Set up TIMER 4 as clock */
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timerp->tmr = DTIM_DTMR_RST_RST;
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/* initialize and enable timer 4 interrupt */
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/* initialize and enable timer interrupt */
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irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);
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intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
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timerp->tcn = 0;
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timerp->trr = 1000; /* Interrupt every ms */
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intp->imrh0 &= ~CFG_TMRINTR_MASK;
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dtimer_intr_setup();
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
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@ -470,7 +478,7 @@ unsigned long long get_ticks(void)
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* This function is derived from PowerPC code (timebase clock frequency).
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* On M68K it returns the number of timer ticks per second.
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*/
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ulong get_tbclk (void)
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ulong get_tbclk(void)
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{
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ulong tbclk;
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tbclk = CFG_HZ;
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