brain-hackers_pepepper-mirror
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u-boot-brain
mirror of https://github.com/brain-hackers/u-boot-brain
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Merge branch 'u-boot/master' into 'u-boot-arm/master' 

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/Makefile
	include/configs/trats.h
	include/configs/trats2.h
	include/mmc.h
This commit is contained in:
Albert ARIBAUD 2014-04-08 09:25:08 +02:00
parent c71645ad2b 04d2f0a9f3
commit 519fdde9e6
97 changed files with 8943 additions and 10922 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Kbuild
View File

@ -42,13 +42,13 @@ $(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild
# 2) Generate asm-offsets.h
#
ifneq ($(wildcard $(srctree)/$(CPUDIR)/$(SOC)/asm-offsets.c),)
ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),)
offsets-file := include/generated/asm-offsets.h
endif
always += $(offsets-file)
targets += $(offsets-file)
targets += $(CPUDIR)/$(SOC)/asm-offsets.s
targets += arch/$(ARCH)/lib/asm-offsets.s
# Default sed regexp - multiline due to syntax constraints
@ -79,9 +79,9 @@ define cmd_offsets
endef
# We use internal kbuild rules to avoid the "is up to date" message from make
$(CPUDIR)/$(SOC)/asm-offsets.s: $(CPUDIR)/$(SOC)/asm-offsets.c FORCE
arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cc_s_c)
$(obj)/$(offsets-file): $(CPUDIR)/$(SOC)/asm-offsets.s
$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild
$(call cmd,offsets)

14
Makefile
View File

@ -8,7 +8,7 @@
VERSION = 2014
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@ -124,7 +124,8 @@ ifneq ($(KBUILD_OUTPUT),)
# Invoke a second make in the output directory, passing relevant variables
# check that the output directory actually exists
saved-output := $(KBUILD_OUTPUT)
KBUILD_OUTPUT := $(shell cd $(KBUILD_OUTPUT) && /bin/pwd)
KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \
&& /bin/pwd)
$(if $(KBUILD_OUTPUT),, \
$(error output directory "$(saved-output)" does not exist))
@ -408,7 +409,7 @@ timestamp_h := include/generated/timestamp_autogenerated.h
no-dot-config-targets := clean clobber mrproper distclean \
help %docs check% coccicheck \
ubootversion backup
ubootversion backup tools-only
config-targets := 0
mixed-targets := 0
@ -728,7 +729,7 @@ endif
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
quiet_cmd_mkimage = UIMAGE $@
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
@ -1129,6 +1130,9 @@ checkarmreloc: u-boot
env: scripts_basic
$(Q)$(MAKE) $(build)=tools/$@
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
tools-all: export HOST_TOOLS_ALL=y
tools-all: env tools ;
@ -1174,7 +1178,7 @@ MRPROPER_FILES += .config .config.old \
clean: rm-dirs := $(CLEAN_DIRS)
clean: rm-files := $(CLEAN_FILES)
clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $f/Makefile),$f))
clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f))
clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook)

12
README
View File

@ -1014,7 +1014,7 @@ The following options need to be configured:
CONFIG_CMD_CDP * Cisco Discover Protocol support
CONFIG_CMD_MFSL * Microblaze FSL support
CONFIG_CMD_XIMG Load part of Multi Image
CONFIG_CMD_UUID * Generate random UUID or GUID string
EXAMPLE: If you want all functions except of network
support you can write:
@ -1527,6 +1527,16 @@ The following options need to be configured:
this to the maximum filesize (in bytes) for the buffer.
Default is 4 MiB if undefined.
DFU_DEFAULT_POLL_TIMEOUT
Poll timeout [ms], is the timeout a device can send to the
host. The host must wait for this timeout before sending
a subsequent DFU_GET_STATUS request to the device.
DFU_MANIFEST_POLL_TIMEOUT
Poll timeout [ms], which the device sends to the host when
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
CONFIG_JFFS2_NAND_DEV

71
arch/arm/cpu/arm1136/mx35/asm-offsets.c
View File

@ -1,71 +0,0 @@
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* This program is used to generate definitions needed by
* assembly language modules.
*
* We use the technique used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <linux/kbuild.h>
int main(void)
{
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
/* Multi-Layer AHB Crossbar Switch */
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
/* AHB <-> IP-Bus Interface */
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
return 0;
}

62
arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
View File

@ -1,62 +0,0 @@
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* This program is used to generate definitions needed by
* assembly language modules.
*
* We use the technique used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/mb86r0x.h>
#include <linux/kbuild.h>
int main(void)
{
/* ddr2 controller */
DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
/* clock reset generator */
DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
/* chip control module */
DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
/* external bus interface */
DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
return 0;
}

57
arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
View File

@ -1,57 +0,0 @@
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* This program is used to generate definitions needed by
* assembly language modules.
*
* We use the technique used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <linux/kbuild.h>
int main(void)
{
/* Clock Control Module */
DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
/* Enhanced SDRAM Controller */
DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
/* Multi-Layer AHB Crossbar Switch */
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
/* AHB <-> IP-Bus Interface */
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
return 0;
}

47
arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
View File

@ -1,47 +0,0 @@
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* This program is used to generate definitions needed by
* assembly language modules.
*
* We use the technique used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <linux/kbuild.h>
int main(void)
{
DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
offsetof(struct system_control_regs, gpcr));
DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
offsetof(struct system_control_regs, fmcr));
return 0;
}

2
arch/arm/cpu/arm926ejs/mxs/Makefile
View File

@ -74,7 +74,7 @@ u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
%.sig: %.csf
$(call if_changed,mkcst_mxs)
quiet_cmd_mkimage_mxs = UIMAGE $@
quiet_cmd_mkimage_mxs = MKIMAGE $@
cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)

73
arch/arm/cpu/armv7/mx5/asm-offsets.c
View File

@ -1,73 +0,0 @@
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* This program is used to generate definitions needed by
* assembly language modules.
*
* We use the technique used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <linux/kbuild.h>
int main(void)
{
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
#if defined(CONFIG_MX53)
DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
#endif
/* DPLL */
DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
return 0;
}

2
arch/arm/cpu/tegra20-common/Makefile
View File

@ -9,7 +9,7 @@
# The AVP is ARMv4T architecture so we must use special compiler
# flags for any startup files it might use.
CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t
CFLAGS_warmboot_avp.o += -march=armv4t
obj-y += clock.o funcmux.o pinmux.o
obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o

2
arch/arm/imx-common/Makefile
View File

@ -32,7 +32,7 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cpp_cfg)
quiet_cmd_mkimage = UIMAGE $@
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)

2
arch/arm/include/asm/arch-am33xx/spl.h
View File

@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
#define _ASM_ARCH_SPL_H_
#if defined(CONFIG_TI816X)
#define BOOT_DEVICE_XIP 2

1
arch/arm/include/asm/arch-davinci/sdmmc_defs.h
View File

@ -151,6 +151,7 @@ struct davinci_mmc {
uint host_caps; /* Host capabilities */
uint voltages; /* Host supported voltages */
uint version; /* MMC Controller version */
struct mmc_config cfg;
};
enum {

2
arch/arm/include/asm/arch-davinci/spl.h
View File

@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NAND 1
#define BOOT_DEVICE_SPI 2

8
arch/arm/include/asm/arch-exynos/cpu.h
View File

@ -25,8 +25,9 @@
#define EXYNOS4_SYSTIMER_BASE 0x10050000
#define EXYNOS4_WATCHDOG_BASE 0x10060000
#define EXYNOS4_TZPC_BASE 0x10110000
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_DMC_CTRL_BASE 0x10400000
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_ACE_SFR_BASE 0x10830000
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
@ -48,7 +49,6 @@
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
@ -68,6 +68,7 @@
#define EXYNOS4X12_TZPC_BASE 0x10110000
#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
#define EXYNOS4X12_FIMD_BASE 0x11C00000
@ -87,7 +88,6 @@
#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
@ -106,7 +106,7 @@
#define EXYNOS5_SYSREG_BASE 0x10050000
#define EXYNOS5_TZPC_BASE 0x10100000
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY_BASE 0x10C00000
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000

2
arch/arm/include/asm/arch-mx35/spl.h
View File

@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1

2
arch/arm/include/asm/arch-omap3/spl.h
View File

@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1

2
arch/arm/include/asm/arch-omap4/spl.h
View File

@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1

2
arch/arm/include/asm/arch-omap5/spl.h
View File

@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1

4
arch/arm/include/asm/arch-tegra/tegra_mmc.h
View File

@ -11,6 +11,9 @@
#include <fdtdec.h>
/* for mmc_config definition */
#include <mmc.h>
#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
#ifndef __ASSEMBLY__
@ -138,6 +141,7 @@ struct mmc_host {
struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
struct mmc_config cfg; /* mmc configuration */
};
void pad_init_mmc(struct mmc_host *host);

248
arch/arm/lib/asm-offsets.c Normal file
View File

@ -0,0 +1,248 @@
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* This program is used to generate definitions needed by
* assembly language modules.
*
* We use the technique used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/kbuild.h>
#if defined(CONFIG_MB86R0x)
#include <asm/arch/mb86r0x.h>
#endif
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
int main(void)
{
/*
* TODO : Check if each entry in this file is really necessary.
* - struct mb86r0x_ddr2
* - struct mb86r0x_memc
* - struct esdramc_regs
* - struct max_regs
* - struct aips_regs
* - struct aipi_regs
* - struct clkctl
* - struct dpll
* are used only for generating asm-offsets.h.
* It means their offset addresses are referenced only from assembly
* code. Is it better to define the macros directly in headers?
*/
#if defined(CONFIG_MB86R0x)
/* ddr2 controller */
DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
/* clock reset generator */
DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
/* chip control module */
DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
/* external bus interface */
DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
#endif
#if defined(CONFIG_MX25)
/* Clock Control Module */
DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
/* Enhanced SDRAM Controller */
DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
/* Multi-Layer AHB Crossbar Switch */
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
/* AHB <-> IP-Bus Interface */
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
#endif
#if defined(CONFIG_MX27)
DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
offsetof(struct system_control_regs, gpcr));
DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
offsetof(struct system_control_regs, fmcr));
#endif
#if defined(CONFIG_MX35)
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
/* Multi-Layer AHB Crossbar Switch */
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
/* AHB <-> IP-Bus Interface */
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
#endif
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
#if defined(CONFIG_MX53)
DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
#endif
/* DPLL */
DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
#endif
return 0;
}

44
arch/nds32/cpu/n1213/ag101/asm-offsets.c
View File

@ -1,44 +0,0 @@
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* Generate definitions needed by assembly language modules.
* This code generates raw asm output which is post-processed to extract
* and format the required data.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <linux/kbuild.h>
int main(void)
{
#ifdef CONFIG_FTSMC020
OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
#endif
BLANK();
#ifdef CONFIG_FTAHBC020S
OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
#endif
BLANK();
#ifdef CONFIG_FTPMU010
OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
#endif
BLANK();
#ifdef CONFIG_FTSDMC021
OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
#endif
return 0;
}

28
arch/nds32/cpu/n1213/ag102/asm-offsets.c → arch/nds32/lib/asm-offsets.c
View File

@ -15,16 +15,43 @@
int main(void)
{
/*
* TODO : Check if each entry in this file is really necessary.
* - struct ftahbc02s
* - struct ftsdmc021
* - struct andes_pcu
* - struct dwcddr21mctl
* are used only for generating asm-offsets.h.
* It means their offset addresses are referenced only from assembly
* code. Is it better to define the macros directly in headers?
*/
#ifdef CONFIG_FTSMC020
OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
#endif
BLANK();
#ifdef CONFIG_FTAHBC020S
OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
#endif
BLANK();
#ifdef CONFIG_FTPMU010
OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
#endif
BLANK();
#ifdef CONFIG_FTSDMC021
OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
#endif
BLANK();
#ifdef CONFIG_ANDES_PCU
OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
#endif
@ -50,5 +77,6 @@ int main(void)
OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
#endif
return 0;
}

5
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -734,6 +734,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500
@ -778,6 +780,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#elif defined(CONFIG_PPC_C29X)
#define CONFIG_MAX_CPUS 1

0
arch/x86/cpu/coreboot/asm-offsets.c → arch/x86/lib/asm-offsets.c
View File

2
board/cray/L1/Makefile
View File

@ -15,7 +15,7 @@ quiet_cmd_awk = AWK $@
$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
$(call cmd,awk)
quiet_cmd_mkimage = UIMAGE $@
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)

2
board/matrix_vision/mvblm7/Makefile
View File

@ -8,7 +8,7 @@ obj-y := mvblm7.o pci.o fpga.o
extra-y := bootscript.img
quiet_cmd_mkimage = UIMAGE $@
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)

2
board/matrix_vision/mvsmr/Makefile
View File

@ -12,7 +12,7 @@ obj-y := mvsmr.o fpga.o
extra-y := bootscript.img
quiet_cmd_mkimage = UIMAGE $@
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)

4
board/renesas/ecovec/ecovec.c
View File

@ -76,7 +76,7 @@ int board_init(void)
{
/* LED (PTG) */
outw((inw(PGCR) & ~0xFF) | 0x66, PGCR);
outw((inw(PGCR) & ~0xFF) | 0x55, PGCR);
outw((inw(HIZCRA) & ~0x02), HIZCRA);
debug_led(1 << 0);
@ -97,7 +97,7 @@ int board_init(void)
/* USB host */
outw((inw(PBCR) & ~0x300) | 0x100, PBCR);
outb((inb(PBDR) & ~0x10) | 0x10, PBDR);
outl(inl(MSTPCR2) & 0x100000, MSTPCR2);
outl(inl(MSTPCR2) & ~0x100000, MSTPCR2);
outw(0x0600, UPONCR0);
debug_led(1 << 3);

8
board/synopsys/axs101/nand.c
View File

@ -107,6 +107,10 @@ static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
writel(0, &bd->buffer_ptr1);
/* Flush modified buffer descriptor */
flush_dcache_range((unsigned long)bd,
(unsigned long)bd + sizeof(struct nand_bd));
/* Issue "write" command */
NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
@ -137,6 +141,10 @@ static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
writel(0, &bd->buffer_ptr1);
/* Flush modified buffer descriptor */
flush_dcache_range((unsigned long)bd,
(unsigned long)bd + sizeof(struct nand_bd));
/* Issue "read" command */
NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));

18
board/ti/am335x/board.c
View File

@ -573,8 +573,22 @@ static struct cpsw_platform_data cpsw_data = {
};
#endif
#if defined(CONFIG_DRIVER_TI_CPSW) || \
(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
* in the environment
* Perform fixups to the PHY present on certain boards. We only need this
* function in:
* - SPL with either CPSW or USB ethernet support
* - Full U-Boot, with either CPSW or USB ethernet
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
&& defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
!defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv, n = 0;

1
board/ti/dra7xx/README
View File

@ -23,3 +23,4 @@ U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
U-Boot # mmc write ${loadaddr} 300 400
U-Boot # mmc bootbus 1 2 0 2
U-Boot # mmc partconf 1 1 1 0
U-Boot # mmc rst-function 1 1

3
common/Makefile
View File

@ -159,6 +159,9 @@ obj-$(CONFIG_CMD_UBI) += cmd_ubi.o
obj-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
obj-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
obj-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
ifdef CONFIG_LZMA
obj-$(CONFIG_CMD_LZMADEC) += cmd_lzmadec.o
endif
ifdef CONFIG_CMD_USB
obj-y += cmd_usb.o
obj-y += usb.o usb_hub.o

9
common/cmd_eeprom.c
View File

@ -389,8 +389,13 @@ void eeprom_init (void)
#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_init_f ();
#endif
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) || \
defined(CONFIG_SYS_I2C)
#ifdef CONFIG_SYS_I2C
i2c_init_all();
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
#endif
}

61
common/cmd_gpt.c
View File

@ -29,30 +29,53 @@
*
* @return - zero on successful expand and env is set
*/
static char extract_env(const char *str, char **env)
static int extract_env(const char *str, char **env)
{
int ret = -1;
char *e, *s;
#ifdef CONFIG_RANDOM_UUID
char uuid_str[UUID_STR_LEN + 1];
#endif
if (!str || strlen(str) < 4)
return -1;
if ((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')) {
s = strdup(str);
if (s == NULL)
return -1;
memset(s + strlen(s) - 1, '\0', 1);
memmove(s, s + 2, strlen(s) - 1);
if (!((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')))
return -1;
s = strdup(str);
if (s == NULL)
return -1;
memset(s + strlen(s) - 1, '\0', 1);
memmove(s, s + 2, strlen(s) - 1);
e = getenv(s);
if (e == NULL) {
#ifdef CONFIG_RANDOM_UUID
debug("%s unset. ", str);
gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_STD);
setenv(s, uuid_str);
e = getenv(s);
free(s);
if (e == NULL) {
printf("Environmental '%s' not set\n", str);
return -1; /* env not set */
if (e) {
debug("Set to random.\n");
ret = 0;
} else {
debug("Can't get random UUID.\n");
}
*env = e;
return 0;
#else
debug("%s unset.\n", str);
#endif
} else {
debug("%s get from environment.\n", str);
ret = 0;
}
return -1;
*env = e;
free(s);
return ret;
}
/**
@ -299,8 +322,16 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return CMD_RET_FAILURE;
}
if (gpt_default(blk_dev_desc, argv[4]))
puts("Writing GPT: ");
ret = gpt_default(blk_dev_desc, argv[4]);
if (!ret) {
puts("success!\n");
return CMD_RET_SUCCESS;
} else {
puts("error!\n");
return CMD_RET_FAILURE;
}
} else {
return CMD_RET_USAGE;
}

52
common/cmd_lzmadec.c Normal file
View File

@ -0,0 +1,52 @@
/*
* (C) Copyright 2013 Patrice Bouchand <pbfwdlist_gmail_com>
* lzma uncompress command in Uboot
*
* made from existing cmd_unzip.c file of Uboot
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <lzma/LzmaTools.h>
static int do_lzmadec(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
unsigned long src, dst;
unsigned long src_len = ~0UL, dst_len = ~0UL;
int ret;
switch (argc) {
case 4:
dst_len = simple_strtoul(argv[3], NULL, 16);
/* fall through */
case 3:
src = simple_strtoul(argv[1], NULL, 16);
dst = simple_strtoul(argv[2], NULL, 16);
break;
default:
return CMD_RET_USAGE;
}
ret = lzmaBuffToBuffDecompress(map_sysmem(dst, dst_len), &src_len,
map_sysmem(src, 0), dst_len);
if (ret != SZ_OK)
return 1;
printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len);
setenv_hex("filesize", src_len);
return 0;
}
U_BOOT_CMD(
lzmadec, 4, 1, do_lzmadec,
"lzma uncompress a memory region",
"srcaddr dstaddr [dstsize]"
);

39
common/cmd_mmc.c
View File

@ -79,7 +79,7 @@ enum mmc_state {
};
static void print_mmcinfo(struct mmc *mmc)
{
printf("Device: %s\n", mmc->name);
printf("Device: %s\n", mmc->cfg->name);
printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24);
printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff);
printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff,
@ -330,6 +330,40 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf("EMMC boot partition Size change Failed.\n");
return 1;
}
} else if (strcmp(argv[1], "rst-function") == 0) {
/*
* Set the RST_n_ENABLE bit of RST_n_FUNCTION
* The only valid values are 0x0, 0x1 and 0x2 and writing
* a value of 0x1 or 0x2 sets the value permanently.
*/
int dev;
struct mmc *mmc;
u8 enable;
if (argc == 4) {
dev = simple_strtoul(argv[2], NULL, 10);
enable = simple_strtoul(argv[3], NULL, 10);
} else {
return CMD_RET_USAGE;
}
if (enable > 2 || enable < 0) {
puts("Invalid RST_n_ENABLE value\n");
return CMD_RET_USAGE;
}
mmc = find_mmc_device(dev);
if (!mmc) {
printf("no mmc device at slot %x\n", dev);
return 1;
}
if (IS_SD(mmc)) {
puts("RST_n_FUNCTION only exists on eMMC\n");
return 1;
}
return mmc_set_rst_n_function(mmc, enable);
#endif /* CONFIG_SUPPORT_EMMC_BOOT */
}
@ -436,6 +470,9 @@ U_BOOT_CMD(
" - Change sizes of boot and RPMB partitions of specified device\n"
"mmc partconf dev boot_ack boot_partition partition_access\n"
" - Change the bits of the PARTITION_CONFIG field of the specified device\n"
"mmc rst-function dev value\n"
" - Change the RST_n_FUNCTION field of the specified device\n"
" WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n"
#endif
"mmc setdsr - set DSR register value\n"
);

2
common/cmd_mmc_spi.c
View File

@ -72,7 +72,7 @@ static int do_mmc_spi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf("Failed to create MMC Device\n");
return 1;
}
printf("%s: %d at %u:%u hz %u mode %u\n", mmc->name, mmc->block_dev.dev,
printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name, mmc->block_dev.dev,
bus, cs, speed, mode);
mmc_init(mmc);
return 0;

97
disk/part_efi.c
View File

@ -63,26 +63,6 @@ static char *print_efiname(gpt_entry *pte)
return name;
}
static void uuid_string(unsigned char *uuid, char *str)
{
static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11,
12, 13, 14, 15};
int i;
for (i = 0; i < 16; i++) {
sprintf(str, "%02x", uuid[le[i]]);
str += 2;
switch (i) {
case 3:
case 5:
case 7:
case 9:
*str++ = '-';
break;
}
}
}
static efi_guid_t system_guid = PARTITION_SYSTEM_GUID;
static inline int is_bootable(gpt_entry *p)
@ -103,6 +83,7 @@ void print_part_efi(block_dev_desc_t * dev_desc)
gpt_entry *gpt_pte = NULL;
int i = 0;
char uuid[37];
unsigned char *uuid_bin;
if (!dev_desc) {
printf("%s: Invalid Argument(s)\n", __func__);
@ -119,8 +100,8 @@ void print_part_efi(block_dev_desc_t * dev_desc)
printf("Part\tStart LBA\tEnd LBA\t\tName\n");
printf("\tAttributes\n");
printf("\tType UUID\n");
printf("\tPartition UUID\n");
printf("\tType GUID\n");
printf("\tPartition GUID\n");
for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) {
/* Stop at the first non valid PTE */
@ -132,10 +113,12 @@ void print_part_efi(block_dev_desc_t * dev_desc)
le64_to_cpu(gpt_pte[i].ending_lba),
print_efiname(&gpt_pte[i]));
printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw);
uuid_string(gpt_pte[i].partition_type_guid.b, uuid);
uuid_bin = (unsigned char *)gpt_pte[i].partition_type_guid.b;
uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID);
printf("\ttype:\t%s\n", uuid);
uuid_string(gpt_pte[i].unique_partition_guid.b, uuid);
printf("\tuuid:\t%s\n", uuid);
uuid_bin = (unsigned char *)gpt_pte[i].unique_partition_guid.b;
uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID);
printf("\tguid:\t%s\n", uuid);
}
/* Remember to free pte */
@ -182,7 +165,8 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
sprintf((char *)info->type, "U-Boot");
info->bootable = is_bootable(&gpt_pte[part - 1]);
#ifdef CONFIG_PARTITION_UUIDS
uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid);
uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
UUID_STR_FORMAT_GUID);
#endif
debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__,
@ -237,60 +221,6 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc)
return 0;
}
/**
* string_uuid(); Convert UUID stored as string to bytes
*
* @param uuid - UUID represented as string
* @param dst - GUID buffer
*
* @return return 0 on successful conversion
*/
static int string_uuid(char *uuid, u8 *dst)
{
efi_guid_t guid;
u16 b, c, d;
u64 e;
u32 a;
u8 *p;
u8 i;
const u8 uuid_str_len = 36;
/* The UUID is written in text: */
/* 1 9 14 19 24 */
/* xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx */
debug("%s: uuid: %s\n", __func__, uuid);
if (strlen(uuid) != uuid_str_len)
return -1;
for (i = 0; i < uuid_str_len; i++) {
if ((i == 8) || (i == 13) || (i == 18) || (i == 23)) {
if (uuid[i] != '-')
return -1;
} else {
if (!isxdigit(uuid[i]))
return -1;
}
}
a = (u32)simple_strtoul(uuid, NULL, 16);
b = (u16)simple_strtoul(uuid + 9, NULL, 16);
c = (u16)simple_strtoul(uuid + 14, NULL, 16);
d = (u16)simple_strtoul(uuid + 19, NULL, 16);
e = (u64)simple_strtoull(uuid + 24, NULL, 16);
p = (u8 *) &e;
guid = EFI_GUID(a, b, c, d >> 8, d & 0xFF,
*(p + 5), *(p + 4), *(p + 3),
*(p + 2), *(p + 1) , *p);
memcpy(dst, guid.b, sizeof(efi_guid_t));
return 0;
}
int write_gpt_table(block_dev_desc_t *dev_desc,
gpt_header *gpt_h, gpt_entry *gpt_e)
{
@ -358,6 +288,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
size_t efiname_len, dosname_len;
#ifdef CONFIG_PARTITION_UUIDS
char *str_uuid;
unsigned char *bin_uuid;
#endif
for (i = 0; i < parts; i++) {
@ -391,7 +322,9 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
#ifdef CONFIG_PARTITION_UUIDS
str_uuid = partitions[i].uuid;
if (string_uuid(str_uuid, gpt_e[i].unique_partition_guid.b)) {
bin_uuid = gpt_e[i].unique_partition_guid.b;
if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_STD)) {
printf("Partition no. %d: invalid guid: %s\n",
i, str_uuid);
return -1;
@ -438,7 +371,7 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h,
gpt_h->header_crc32 = 0;
gpt_h->partition_entry_array_crc32 = 0;
if (string_uuid(str_guid, gpt_h->disk_guid.b))
if (uuid_str_to_bin(str_guid, gpt_h->disk_guid.b, UUID_STR_FORMAT_GUID))
return -1;
return 0;

22
doc/README.gpt
View File

@ -132,8 +132,8 @@ of the Primary.
----------------------
Offset Size Description
0 16 B Partition type GUID
16 16 B Unique partition GUID
0 16 B Partition type GUID (Big Endian)
16 16 B Unique partition GUID in (Big Endian)
32 8 B First LBA (Little Endian)
40 8 B Last LBA (inclusive)
48 8 B Attribute flags [+]
@ -160,6 +160,9 @@ To restore GUID partition table one needs to:
Fields 'name', 'size' and 'uuid' are mandatory for every partition.
The field 'start' is optional.
option: CONFIG_RANDOM_UUID
If any partition "UUID" no exists then it is randomly generated.
2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT'
2. From u-boot prompt type:
@ -168,11 +171,20 @@ To restore GUID partition table one needs to:
Useful info:
============
Two programs, namely: 'fdisk' and 'parted' are recommended to work with GPT
recovery. Parted is able to handle GUID partitions. Unfortunately the 'fdisk'
hasn't got such ability.
Two programs, namely: 'gdisk' and 'parted' are recommended to work with GPT
recovery. Both are able to handle GUID partitions.
Please, pay attention at -l switch for parted.
"uuid" program is recommended to generate UUID string. Moreover it can decode
(-d switch) passed in UUID string. It can be used to generate partitions UUID
passed to u-boot environment variables.
If optional CONFIG_RANDOM_UUID is defined then for any partition which environment
uuid is unset, uuid is randomly generated and stored in correspond environment
variable.
note:
Each string block of UUID generated by program "uuid" is in big endian and it is
also stored in big endian in disk GPT.
Partitions layout can be printed by typing "mmc part". Note that each partition
GUID has different byte order than UUID generated before, this is because first
three blocks of GUID string are in Little Endian.

23
drivers/block/ahci.c
View File

@ -623,6 +623,7 @@ static int ata_scsiop_inquiry(ccb *pccb)
95 - 4,
};
u8 fis[20];
u16 *idbuf;
ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
u8 port;
@ -649,17 +650,25 @@ static int ata_scsiop_inquiry(ccb *pccb)
return -EIO;
}
if (ataid[port])
free(ataid[port]);
ataid[port] = tmpid;
ata_swap_buf_le16(tmpid, ATA_ID_WORDS);
if (!ataid[port]) {
ataid[port] = malloc(ATA_ID_WORDS * 2);
if (!ataid[port]) {
printf("%s: No memory for ataid[port]\n", __func__);
return -ENOMEM;
}
}
idbuf = ataid[port];
memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
memcpy(&pccb->pdata[8], "ATA ", 8);
ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16);
ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4);
ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
#ifdef DEBUG
ata_dump_id(tmpid);
ata_dump_id(idbuf);
#endif
return 0;
}

73
drivers/crypto/ace_sha.c
View File

@ -5,10 +5,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ace_sha.h"
#ifdef CONFIG_SHA_HW_ACCEL
#include <sha256.h>
#include <sha1.h>
#include <asm/errno.h>
#include "ace_sha.h"
/* SHA1 value for the message of zero length */
static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
@ -111,3 +113,72 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
debug("ACE was not setup properly or it is faulty\n");
}
#endif /* CONFIG_SHA_HW_ACCEL */
#ifdef CONFIG_LIB_HW_RAND
static unsigned int seed_done;
void srand(unsigned int seed)
{
struct exynos_ace_sfr *reg =
(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
int i, status;
/* Seed data */
for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
writel(seed << i, &reg->hash_seed[i]);
/* Wait for seed setup done */
while (1) {
status = readl(&reg->hash_status);
if ((status & ACE_HASH_SEEDSETTING_MASK) ||
(status & ACE_HASH_PRNGERROR_MASK))
break;
}
seed_done = 1;
}
unsigned int rand(void)
{
struct exynos_ace_sfr *reg =
(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
int i, status;
unsigned int seed = (unsigned int)&status;
unsigned int ret = 0;
if (!seed_done)
srand(seed);
/* Start PRNG */
writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, &reg->hash_control);
/* Wait for PRNG done */
while (1) {
status = readl(&reg->hash_status);
if (status & ACE_HASH_PRNGDONE_MASK)
break;
if (status & ACE_HASH_PRNGERROR_MASK) {
seed_done = 0;
return 0;
}
}
/* Clear Done IRQ */
writel(ACE_HASH_PRNGDONE_MASK, &reg->hash_status);
/* Read a PRNG result */
for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
ret += readl(&reg->hash_prng[i]);
seed_done = 0;
return ret;
}
unsigned int rand_r(unsigned int *seedp)
{
srand(*seedp);
return rand();
}
#endif /* CONFIG_LIB_HW_RAND */

8
drivers/crypto/ace_sha.h
View File

@ -72,9 +72,10 @@ struct exynos_ace_sfr {
unsigned char res12[0x30];
unsigned int hash_result[8];
unsigned char res13[0x20];
unsigned int hash_seed[8];
unsigned int hash_prng[8];
unsigned char res14[0x180];
unsigned int hash_seed[5];
unsigned char res14[12];
unsigned int hash_prng[5];
unsigned char res15[0x18c];
unsigned int pka_sfr[5]; /* base + 0x700 */
};
@ -291,6 +292,7 @@ struct exynos_ace_sfr {
#define ACE_HASH_PRNGERROR_MASK (1 << 7)
#define ACE_HASH_PRNGERROR_OFF (0 << 7)
#define ACE_HASH_PRNGERROR_ON (1 << 7)
#define ACE_HASH_PRNG_REG_NUM 5
#define ACE_SHA_TYPE_SHA1 1
#define ACE_SHA_TYPE_SHA256 2

42
drivers/dfu/dfu.c
View File

@ -127,6 +127,28 @@ static int dfu_write_buffer_drain(struct dfu_entity *dfu)
return ret;
}
int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
{
int ret = 0;
if (dfu->flush_medium)
ret = dfu->flush_medium(dfu);
printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc);
/* clear everything */
dfu_free_buf();
dfu->crc = 0;
dfu->offset = 0;
dfu->i_blk_seq_num = 0;
dfu->i_buf_start = dfu_buf;
dfu->i_buf_end = dfu_buf;
dfu->i_buf = dfu->i_buf_start;
dfu->inited = 0;
return ret;
}
int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
{
int ret = 0;
@ -197,26 +219,6 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
ret = tret;
}
/* end? */
if (size == 0) {
/* Now try and flush to the medium if needed. */
if (dfu->flush_medium)
ret = dfu->flush_medium(dfu);
printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc);
/* clear everything */
dfu_free_buf();
dfu->crc = 0;
dfu->offset = 0;
dfu->i_blk_seq_num = 0;
dfu->i_buf_start = dfu_buf;
dfu->i_buf_end = dfu_buf;
dfu->i_buf = dfu->i_buf_start;
dfu->inited = 0;
}
return ret = 0 ? size : ret;
}

31
drivers/dfu/dfu_mmc.c
View File

@ -12,6 +12,7 @@
#include <errno.h>
#include <div64.h>
#include <dfu.h>
#include <mmc.h>
static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE)
dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE];
@ -20,8 +21,8 @@ static long dfu_file_buf_len;
static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
u64 offset, void *buf, long *len)
{
char cmd_buf[DFU_CMD_BUF_SIZE];
u32 blk_start, blk_count;
struct mmc *mmc = find_mmc_device(dfu->dev_num);
u32 blk_start, blk_count, n = 0;
/*
* We must ensure that we work in lba_blk_size chunks, so ALIGN
@ -38,12 +39,28 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
return -EINVAL;
}
sprintf(cmd_buf, "mmc %s %p %x %x",
op == DFU_OP_READ ? "read" : "write",
buf, blk_start, blk_count);
debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__,
op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", dfu->dev_num,
blk_start, blk_count, buf);
switch (op) {
case DFU_OP_READ:
n = mmc->block_dev.block_read(dfu->dev_num, blk_start,
blk_count, buf);
break;
case DFU_OP_WRITE:
n = mmc->block_dev.block_write(dfu->dev_num, blk_start,
blk_count, buf);
break;
default:
error("Operation not supported\n");
}
debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
return run_command(cmd_buf, 0);
if (n != blk_count) {
error("MMC operation failed");
return -EIO;
}
return 0;
}
static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len)

387
drivers/i2c/adi_i2c.c
View File

@ -1,387 +0,0 @@
/*
* i2c.c - driver for ADI TWI/I2C
*
* Copyright (c) 2006-2013 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <i2c.h>
#include <asm/clock.h>
#include <asm/twi.h>
#include <asm/io.h>
/* Every register is 32bit aligned, but only 16bits in size */
#define ureg(name) u16 name; u16 __pad_##name;
struct twi_regs {
ureg(clkdiv);
ureg(control);
ureg(slave_ctl);
ureg(slave_stat);
ureg(slave_addr);
ureg(master_ctl);
ureg(master_stat);
ureg(master_addr);
ureg(int_stat);
ureg(int_mask);
ureg(fifo_ctl);
ureg(fifo_stat);
char __pad[0x50];
ureg(xmt_data8);
ureg(xmt_data16);
ureg(rcv_data8);
ureg(rcv_data16);
};
#undef ureg
/* U-Boot I2C framework allows only one active device at a time. */
#ifdef TWI_CLKDIV
#define TWI0_CLKDIV TWI_CLKDIV
#endif
static struct twi_regs *twi = (void *)TWI0_CLKDIV;
#ifdef DEBUG
# define dmemset(s, c, n) memset(s, c, n)
#else
# define dmemset(s, c, n)
#endif
#define debugi(fmt, args...) \
debug( \
"MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
twi->master_stat, twi->fifo_stat, twi->int_stat, \
__func__, __LINE__, ## args)
#ifdef CONFIG_TWICLK_KHZ
# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
#endif
/*
* The way speed is changed into duty often results in integer truncation
* with 50% duty, so we'll force rounding up to the next duty by adding 1
* to the max. In practice this will get us a speed of something like
* 385 KHz. The other limit is easy to handle as it is only 8 bits.
*/
#define I2C_SPEED_MAX 400000
#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
#define I2C_DUTY_MIN 0xff /* 8 bit limited */
#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
/* Note: duty is inverse of speed, so the comparisons below are correct */
#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
#endif
/* All transfers are described by this data structure */
struct i2c_msg {
u8 flags;
#define I2C_M_COMBO 0x4
#define I2C_M_STOP 0x2
#define I2C_M_READ 0x1
int len; /* msg length */
u8 *buf; /* pointer to msg data */
int alen; /* addr length */
u8 *abuf; /* addr buffer */
};
/* Allow msec timeout per ~byte transfer */
#define I2C_TIMEOUT 10
/**
* wait_for_completion - manage the actual i2c transfer
* @msg: the i2c msg
*/
static int wait_for_completion(struct i2c_msg *msg)
{
u16 int_stat, ctl;
ulong timebase = get_timer(0);
do {
int_stat = readw(&twi->int_stat);
if (int_stat & XMTSERV) {
debugi("processing XMTSERV");
writew(XMTSERV, &twi->int_stat);
if (msg->alen) {
writew(*(msg->abuf++), &twi->xmt_data8);
--msg->alen;
} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
writew(*(msg->buf++), &twi->xmt_data8);
--msg->len;
} else {
ctl = readw(&twi->master_ctl);
if (msg->flags & I2C_M_COMBO)
writew(ctl | RSTART | MDIR,
&twi->master_ctl);
else
writew(ctl | STOP, &twi->master_ctl);
}
}
if (int_stat & RCVSERV) {
debugi("processing RCVSERV");
writew(RCVSERV, &twi->int_stat);
if (msg->len) {
*(msg->buf++) = readw(&twi->rcv_data8);
--msg->len;
} else if (msg->flags & I2C_M_STOP) {
ctl = readw(&twi->master_ctl);
writew(ctl | STOP, &twi->master_ctl);
}
}
if (int_stat & MERR) {
debugi("processing MERR");
writew(MERR, &twi->int_stat);
return msg->len;
}
if (int_stat & MCOMP) {
debugi("processing MCOMP");
writew(MCOMP, &twi->int_stat);
if (msg->flags & I2C_M_COMBO && msg->len) {
ctl = readw(&twi->master_ctl);
ctl = (ctl & ~RSTART) |
(min(msg->len, 0xff) << 6) | MEN | MDIR;
writew(ctl, &twi->master_ctl);
} else
break;
}
/* If we were able to do something, reset timeout */
if (int_stat)
timebase = get_timer(0);
} while (get_timer(timebase) < I2C_TIMEOUT);
return msg->len;
}
/**
* i2c_transfer - setup an i2c transfer
* @return: 0 if things worked, non-0 if things failed
*
* Here we just get the i2c stuff all prepped and ready, and then tail off
* into wait_for_completion() for all the bits to go.
*/
static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
int len, u8 flags)
{
int ret;
u16 ctl;
uchar addr_buffer[] = {
(addr >> 0),
(addr >> 8),
(addr >> 16),
};
struct i2c_msg msg = {
.flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
.buf = buffer,
.len = len,
.abuf = addr_buffer,
.alen = alen,
};
dmemset(buffer, 0xff, len);
debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i ",
chip, addr, alen, buffer[0], len);
debugi("flags=0x%02x[%s] ", flags,
(flags & I2C_M_READ ? "rd" : "wr"));
/* wait for things to settle */
while (readw(&twi->master_stat) & BUSBUSY)
if (ctrlc())
return 1;
/* Set Transmit device address */
writew(chip, &twi->master_addr);
/* Clear the FIFO before starting things */
writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
writew(0, &twi->fifo_ctl);
/* prime the pump */
if (msg.alen) {
len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
debugi("first byte=0x%02x", *msg.abuf);
writew(*(msg.abuf++), &twi->xmt_data8);
--msg.alen;
} else if (!(msg.flags & I2C_M_READ) && msg.len) {
debugi("first byte=0x%02x", *msg.buf);
writew(*(msg.buf++), &twi->xmt_data8);
--msg.len;
}
/* clear int stat */
writew(-1, &twi->master_stat);
writew(-1, &twi->int_stat);
writew(0, &twi->int_mask);
/* Master enable */
ctl = readw(&twi->master_ctl);
ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
((msg.flags & I2C_M_READ) ? MDIR : 0);
writew(ctl, &twi->master_ctl);
/* process the rest */
ret = wait_for_completion(&msg);
debugi("ret=%d", ret);
if (ret) {
ctl = readw(&twi->master_ctl) & ~MEN;
writew(ctl, &twi->master_ctl);
ctl = readw(&twi->control) & ~TWI_ENA;
writew(ctl, &twi->control);
ctl = readw(&twi->control) | TWI_ENA;
writew(ctl, &twi->control);
}
return ret;
}
/**
* i2c_set_bus_speed - set i2c bus speed
* @speed: bus speed (in HZ)
*/
int i2c_set_bus_speed(unsigned int speed)
{
u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
/* Set TWI interface clock */
if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
return -1;
clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
writew(clkdiv, &twi->clkdiv);
/* Don't turn it on */
writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
return 0;
}
/**
* i2c_get_bus_speed - get i2c bus speed
* @speed: bus speed (in HZ)
*/
unsigned int i2c_get_bus_speed(void)
{
u16 clkdiv = readw(&twi->clkdiv) & 0xff;
/* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
return 5000000 / clkdiv;
}
/**
* i2c_init - initialize the i2c bus
* @speed: bus speed (in HZ)
* @slaveaddr: address of device in slave mode (0 - not slave)
*
* Slave mode isn't actually implemented. It'll stay that way until
* we get a real request for it.
*/
void i2c_init(int speed, int slaveaddr)
{
u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
/* Set TWI internal clock as 10MHz */
writew(prescale, &twi->control);
/* Set TWI interface clock as specified */
i2c_set_bus_speed(speed);
/* Enable it */
writew(TWI_ENA | prescale, &twi->control);
debugi("CONTROL:0x%04x CLKDIV:0x%04x", readw(&twi->control),
readw(&twi->clkdiv));
#if CONFIG_SYS_I2C_SLAVE
# error I2C slave support not tested/supported
#endif
}
/**
* i2c_probe - test if a chip exists at a given i2c address
* @chip: i2c chip addr to search for
* @return: 0 if found, non-0 if not found
*/
int i2c_probe(uchar chip)
{
u8 byte;
return i2c_read(chip, 0, 0, &byte, 1);
}
/**
* i2c_read - read data from an i2c device
* @chip: i2c chip addr
* @addr: memory (register) address in the chip
* @alen: byte size of address
* @buffer: buffer to store data read from chip
* @len: how many bytes to read
* @return: 0 on success, non-0 on failure
*/
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
return i2c_transfer(chip, addr, alen, buffer,
len, (alen ? I2C_M_COMBO : I2C_M_READ));
}
/**
* i2c_write - write data to an i2c device
* @chip: i2c chip addr
* @addr: memory (register) address in the chip
* @alen: byte size of address
* @buffer: buffer holding data to write to chip
* @len: how many bytes to write
* @return: 0 on success, non-0 on failure
*/
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
return i2c_transfer(chip, addr, alen, buffer, len, 0);
}
/**
* i2c_set_bus_num - change active I2C bus
* @bus: bus index, zero based
* @returns: 0 on success, non-0 on failure
*/
int i2c_set_bus_num(unsigned int bus)
{
switch (bus) {
#if CONFIG_SYS_MAX_I2C_BUS > 0
case 0:
twi = (void *)TWI0_CLKDIV;
return 0;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 1
case 1:
twi = (void *)TWI1_CLKDIV;
return 0;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 2
case 2:
twi = (void *)TWI2_CLKDIV;
return 0;
#endif
default: return -1;
}
}
/**
* i2c_get_bus_num - returns index of active I2C bus
*/
unsigned int i2c_get_bus_num(void)
{
switch ((unsigned long)twi) {
#if CONFIG_SYS_MAX_I2C_BUS > 0
case TWI0_CLKDIV:
return 0;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 1
case TWI1_CLKDIV:
return 1;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 2
case TWI2_CLKDIV:
return 2;
#endif
default: return -1;
}
}

50
drivers/mmc/arm_pl180_mmci.c
View File

@ -287,9 +287,9 @@ static void host_set_ios(struct mmc *dev)
u32 clkdiv = 0;
u32 tmp_clock;
if (dev->clock >= dev->f_max) {
if (dev->clock >= dev->cfg->f_max) {
clkdiv = 0;
dev->clock = dev->f_max;
dev->clock = dev->cfg->f_max;
} else {
clkdiv = (host->clock_in / dev->clock) - 2;
}
@ -335,6 +335,12 @@ static void host_set_ios(struct mmc *dev)
udelay(CLK_CHANGE_DELAY);
}
static const struct mmc_ops arm_pl180_mmci_ops = {
.send_cmd = host_request,
.set_ios = host_set_ios,
.init = mmc_host_reset,
};
/*
* mmc_host_init - initialize the mmc controller.
* Set initial clock and power for mmc slot.
@ -342,16 +348,9 @@ static void host_set_ios(struct mmc *dev)
*/
int arm_pl180_mmci_init(struct pl180_mmc_host *host)
{
struct mmc *dev;
struct mmc *mmc;
u32 sdi_u32;
dev = malloc(sizeof(struct mmc));
if (!dev)
return -ENOMEM;
memset(dev, 0, sizeof(struct mmc));
dev->priv = host;
writel(host->pwr_init, &host->base->power);
writel(host->clkdiv_init, &host->base->clock);
udelay(CLK_CHANGE_DELAY);
@ -359,19 +358,24 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host)
/* Disable mmc interrupts */
sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
writel(sdi_u32, &host->base->mask0);
strncpy(dev->name, host->name, sizeof(dev->name));
dev->send_cmd = host_request;
dev->set_ios = host_set_ios;
dev->init = mmc_host_reset;
dev->getcd = NULL;
dev->getwp = NULL;
dev->host_caps = host->caps;
dev->voltages = host->voltages;
dev->f_min = host->clock_min;
dev->f_max = host->clock_max;
dev->b_max = host->b_max;
mmc_register(dev);
debug("registered mmc interface number is:%d\n", dev->block_dev.dev);
host->cfg.name = host->name;
host->cfg.ops = &arm_pl180_mmci_ops;
/* TODO remove the duplicates */
host->cfg.host_caps = host->caps;
host->cfg.voltages = host->voltages;
host->cfg.f_min = host->clock_min;
host->cfg.f_max = host->clock_max;
if (host->b_max != 0)
host->cfg.b_max = host->b_max;
else
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
mmc = mmc_create(&host->cfg, host);
if (mmc == NULL)
return -1;
debug("registered mmc interface number is:%d\n", mmc->block_dev.dev);
return 0;
}

4
drivers/mmc/arm_pl180_mmci.h
View File

@ -13,6 +13,9 @@
#ifndef __ARM_PL180_MMCI_H__
#define __ARM_PL180_MMCI_H__
/* need definition of struct mmc_config */
#include <mmc.h>
#define COMMAND_REG_DELAY 300
#define DATA_REG_DELAY 1000
#define CLK_CHANGE_DELAY 2000
@ -184,6 +187,7 @@ struct pl180_mmc_host {
unsigned int clkdiv_init;
unsigned int pwr_init;
int version2;
struct mmc_config cfg;
};
int arm_pl180_mmci_init(struct pl180_mmc_host *);

38
drivers/mmc/bfin_sdh.c
View File

@ -274,30 +274,30 @@ static int bfin_sdh_init(struct mmc *mmc)
return 0;
}
static const struct mmc_ops bfin_mmc_ops = {
.send_cmd = bfin_sdh_request,
.set_ios = bfin_sdh_set_ios,
.init = bfin_sdh_init,
};
static struct mmc_config bfin_mmc_cfg = {
.name = "Blackfin SDH",
.ops = &bfin_mmc_ops,
.host_caps = MMC_MODE_4BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
int bfin_mmc_init(bd_t *bis)
{
struct mmc *mmc = NULL;
struct mmc *mmc;
mmc = malloc(sizeof(struct mmc));
bfin_mmc_cfg.f_max = get_sclk();
bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9;
if (!mmc)
return -ENOMEM;
sprintf(mmc->name, "Blackfin SDH");
mmc->send_cmd = bfin_sdh_request;
mmc->set_ios = bfin_sdh_set_ios;
mmc->init = bfin_sdh_init;
mmc->getcd = NULL;
mmc->getwp = NULL;
mmc->host_caps = MMC_MODE_4BIT;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_max = get_sclk();
mmc->f_min = mmc->f_max >> 9;
mmc->b_max = 0;
mmc_register(mmc);
mmc = mmc_create(&bfin_mmc_cfg, NULL);
if (mmc == NULL)
return -1;
return 0;
}

41
drivers/mmc/davinci_mmc.c
View File

@ -30,10 +30,10 @@ static void dmmc_set_clock(struct mmc *mmc, uint clock)
struct davinci_mmc_regs *regs = host->reg_base;
uint clkrt, sysclk2, act_clock;
if (clock < mmc->f_min)
clock = mmc->f_min;
if (clock > mmc->f_max)
clock = mmc->f_max;
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
if (clock > mmc->cfg->f_max)
clock = mmc->cfg->f_max;
set_val(&regs->mmcclk, 0);
sysclk2 = host->input_clk;
@ -363,32 +363,27 @@ static void dmmc_set_ios(struct mmc *mmc)
dmmc_set_clock(mmc, mmc->clock);
}
static const struct mmc_ops dmmc_ops = {
.send_cmd = dmmc_send_cmd,
.set_ios = dmmc_set_ios,
.init = dmmc_init,
};
/* Called from board_mmc_init during startup. Can be called multiple times
* depending on the number of slots available on board and controller
*/
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
{
struct mmc *mmc;
host->cfg.name = "davinci";
host->cfg.ops = &dmmc_ops;
host->cfg.f_min = 200000;
host->cfg.f_max = 25000000;
host->cfg.voltages = host->voltages;
host->cfg.host_caps = host->host_caps;
mmc = malloc(sizeof(struct mmc));
memset(mmc, 0, sizeof(struct mmc));
host->cfg.b_max = DAVINCI_MAX_BLOCKS;
sprintf(mmc->name, "davinci");
mmc->priv = host;
mmc->send_cmd = dmmc_send_cmd;
mmc->set_ios = dmmc_set_ios;
mmc->init = dmmc_init;
mmc->getcd = NULL;
mmc->getwp = NULL;
mmc->f_min = 200000;
mmc->f_max = 25000000;
mmc->voltages = host->voltages;
mmc->host_caps = host->host_caps;
mmc->b_max = DAVINCI_MAX_BLOCKS;
mmc_register(mmc);
mmc_create(&host->cfg, host);
return 0;
}

58
drivers/mmc/dw_mmc.c
View File

@ -107,7 +107,7 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host,
static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
struct dwmci_host *host = mmc->priv;
ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
data ? DIV_ROUND_UP(data->blocks, 8) : 0);
int flags = 0, i;
@ -284,7 +284,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
static void dwmci_set_ios(struct mmc *mmc)
{
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
struct dwmci_host *host = mmc->priv;
u32 ctype;
debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
@ -310,7 +310,7 @@ static void dwmci_set_ios(struct mmc *mmc)
static int dwmci_init(struct mmc *mmc)
{
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
struct dwmci_host *host = mmc->priv;
if (host->board_init)
host->board_init(host);
@ -323,7 +323,7 @@ static int dwmci_init(struct mmc *mmc)
}
/* Enumerate at 400KHz */
dwmci_setup_bus(host, mmc->f_min);
dwmci_setup_bus(host, mmc->cfg->f_min);
dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
dwmci_writel(host, DWMCI_INTMASK, 0);
@ -343,41 +343,37 @@ static int dwmci_init(struct mmc *mmc)
return 0;
}
static const struct mmc_ops dwmci_ops = {
.send_cmd = dwmci_send_cmd,
.set_ios = dwmci_set_ios,
.init = dwmci_init,
};
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
struct mmc *mmc;
int err = 0;
host->cfg.name = host->name;
host->cfg.ops = &dwmci_ops;
host->cfg.f_min = min_clk;
host->cfg.f_max = max_clk;
mmc = calloc(sizeof(struct mmc), 1);
if (!mmc) {
printf("mmc calloc fail!\n");
return -1;
}
host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->priv = host;
host->mmc = mmc;
sprintf(mmc->name, "%s", host->name);
mmc->send_cmd = dwmci_send_cmd;
mmc->set_ios = dwmci_set_ios;
mmc->init = dwmci_init;
mmc->f_min = min_clk;
mmc->f_max = max_clk;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = host->caps;
host->cfg.host_caps = host->caps;
if (host->buswidth == 8) {
mmc->host_caps |= MMC_MODE_8BIT;
mmc->host_caps &= ~MMC_MODE_4BIT;
host->cfg.host_caps |= MMC_MODE_8BIT;
host->cfg.host_caps &= ~MMC_MODE_4BIT;
} else {
mmc->host_caps |= MMC_MODE_4BIT;
mmc->host_caps &= ~MMC_MODE_8BIT;
host->cfg.host_caps |= MMC_MODE_4BIT;
host->cfg.host_caps &= ~MMC_MODE_8BIT;
}
mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
err = mmc_register(mmc);
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
return err;
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL)
return -1;
return 0;
}

143
drivers/mmc/fsl_esdhc.c
View File

@ -172,7 +172,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
int timeout;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
uint wml_value;
@ -221,16 +221,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
* 2)Timeout period should be minimum 0.250sec as per SD Card spec
* So, Number of SD Clock cycles for 0.25sec should be minimum
* (SD Clock/sec * 0.25 sec) SD Clock cycles
* = (mmc->tran_speed * 1/4) SD Clock cycles
* = (mmc->clock * 1/4) SD Clock cycles
* As 1) >= 2)
* => (2^(timeout+13)) >= mmc->tran_speed * 1/4
* => (2^(timeout+13)) >= mmc->clock * 1/4
* Taking log2 both the sides
* => timeout + 13 >= log2(mmc->tran_speed/4)
* => timeout + 13 >= log2(mmc->clock/4)
* Rounding up to next power of 2
* => timeout + 13 = log2(mmc->tran_speed/4) + 1
* => timeout + 13 = fls(mmc->tran_speed/4)
* => timeout + 13 = log2(mmc->clock/4) + 1
* => timeout + 13 = fls(mmc->clock/4)
*/
timeout = fls(mmc->tran_speed/4);
timeout = fls(mmc->clock/4);
timeout -= 13;
if (timeout > 14)
@ -244,6 +244,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
timeout++;
#endif
#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
timeout = 0xE;
#endif
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
return 0;
@ -265,9 +268,10 @@ static void check_and_invalidate_dcache_range
static int
esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
int err = 0;
uint xfertyp;
uint irqstat;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc_cfg *cfg = mmc->priv;
volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -296,8 +300,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
/* Set up for a data transfer if we have one */
if (data) {
int err;
err = esdhc_setup_data(mmc, data);
if(err)
return err;
@ -325,27 +327,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
irqstat = esdhc_read32(&regs->irqstat);
/* Reset CMD and DATA portions on error */
if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
SYSCTL_RSTC);
while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
;
if (data) {
esdhc_write32(&regs->sysctl,
esdhc_read32(&regs->sysctl) |
SYSCTL_RSTD);
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
;
}
if (irqstat & CMD_ERR) {
err = COMM_ERR;
goto out;
}
if (irqstat & CMD_ERR)
return COMM_ERR;
if (irqstat & IRQSTAT_CTOE)
return TIMEOUT;
if (irqstat & IRQSTAT_CTOE) {
err = TIMEOUT;
goto out;
}
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
@ -360,7 +350,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
if (timeout <= 0) {
printf("Timeout waiting for DAT0 to go high!\n");
return TIMEOUT;
err = TIMEOUT;
goto out;
}
}
@ -387,32 +378,53 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
do {
irqstat = esdhc_read32(&regs->irqstat);
if (irqstat & IRQSTAT_DTOE)
return TIMEOUT;
if (irqstat & IRQSTAT_DTOE) {
err = TIMEOUT;
goto out;
}
if (irqstat & DATA_ERR)
return COMM_ERR;
if (irqstat & DATA_ERR) {
err = COMM_ERR;
goto out;
}
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
#endif
if (data->flags & MMC_DATA_READ)
check_and_invalidate_dcache_range(cmd, data);
}
out:
/* Reset CMD and DATA portions on error */
if (err) {
esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
SYSCTL_RSTC);
while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
;
if (data) {
esdhc_write32(&regs->sysctl,
esdhc_read32(&regs->sysctl) |
SYSCTL_RSTD);
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
;
}
}
esdhc_write32(&regs->irqstat, -1);
return 0;
return err;
}
static void set_sysctl(struct mmc *mmc, uint clock)
{
int div, pre_div;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc_cfg *cfg = mmc->priv;
volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
int sdhc_clk = cfg->sdhc_clk;
uint clk;
if (clock < mmc->f_min)
clock = mmc->f_min;
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
if (sdhc_clk / 16 > clock) {
for (pre_div = 2; pre_div < 256; pre_div *= 2)
@ -443,7 +455,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
static void esdhc_set_ios(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
/* Set the clock speed */
@ -461,7 +473,7 @@ static void esdhc_set_ios(struct mmc *mmc)
static int esdhc_init(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
int timeout = 1000;
@ -496,7 +508,7 @@ static int esdhc_init(struct mmc *mmc)
static int esdhc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
int timeout = 1000;
@ -524,6 +536,13 @@ static void esdhc_reset(struct fsl_esdhc *regs)
printf("MMC/SD: Reset never completed.\n");
}
static const struct mmc_ops esdhc_ops = {
.send_cmd = esdhc_send_cmd,
.set_ios = esdhc_set_ios,
.init = esdhc_init,
.getcd = esdhc_getcd,
};
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
struct fsl_esdhc *regs;
@ -533,12 +552,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
if (!cfg)
return -1;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
memset(mmc, 0, sizeof(struct mmc));
sprintf(mmc->name, "FSL_SDHC");
regs = (struct fsl_esdhc *)cfg->esdhc_base;
/* First reset the eSDHC controller */
@ -547,12 +560,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
mmc->priv = cfg;
mmc->send_cmd = esdhc_send_cmd;
mmc->set_ios = esdhc_set_ios;
mmc->init = esdhc_init;
mmc->getcd = esdhc_getcd;
mmc->getwp = NULL;
memset(&cfg->cfg, 0, sizeof(cfg->cfg));
voltage_caps = 0;
caps = regs->hostcapblt;
@ -574,38 +582,43 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
if (caps & ESDHC_HOSTCAPBLT_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->cfg.name = "FSL_SDHC";
cfg->cfg.ops = &esdhc_ops;
#ifdef CONFIG_SYS_SD_VOLTAGE
mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
#else
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
if ((mmc->voltages & voltage_caps) == 0) {
if ((cfg->cfg.voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
return -1;
}
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
if (cfg->max_bus_width > 0) {
if (cfg->max_bus_width < 8)
mmc->host_caps &= ~MMC_MODE_8BIT;
cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
if (cfg->max_bus_width < 4)
mmc->host_caps &= ~MMC_MODE_4BIT;
cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
}
if (caps & ESDHC_HOSTCAPBLT_HSS)
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
mmc->host_caps &= ~MMC_MODE_8BIT;
cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
#endif
mmc->f_min = 400000;
mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
cfg->cfg.f_min = 400000;
cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000);
mmc->b_max = 0;
mmc_register(mmc);
cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
mmc = mmc_create(&cfg->cfg, cfg);
if (mmc == NULL)
return -1;
return 0;
}

73
drivers/mmc/ftsdc010_mci.c
View File

@ -27,6 +27,7 @@ struct ftsdc010_chip {
uint32_t sclk; /* FTSDC010 source clock in Hz */
uint32_t fifo; /* fifo depth in bytes */
uint32_t acmd;
struct mmc_config cfg; /* mmc configuration */
};
static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
@ -123,14 +124,6 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
}
}
static inline int ftsdc010_is_ro(struct mmc *mmc)
{
struct ftsdc010_chip *chip = mmc->priv;
const uint8_t *csd = (const uint8_t *)mmc->csd;
return chip->wprot || (csd[1] & 0x30);
}
static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
{
int ret = TIMEOUT;
@ -316,6 +309,12 @@ static int ftsdc010_init(struct mmc *mmc)
return 0;
}
static const struct mmc_ops ftsdc010_ops = {
.send_cmd = ftsdc010_request,
.set_ios = ftsdc010_set_ios,
.init = ftsdc010_init,
};
int ftsdc010_mmc_init(int devid)
{
struct mmc *mmc;
@ -331,50 +330,44 @@ int ftsdc010_mmc_init(int devid)
regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
#endif
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
memset(mmc, 0, sizeof(struct mmc));
chip = malloc(sizeof(struct ftsdc010_chip));
if (!chip) {
free(mmc);
if (!chip)
return -ENOMEM;
}
memset(chip, 0, sizeof(struct ftsdc010_chip));
chip->regs = regs;
mmc->priv = chip;
sprintf(mmc->name, "ftsdc010");
mmc->send_cmd = ftsdc010_request;
mmc->set_ios = ftsdc010_set_ios;
mmc->init = ftsdc010_init;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
case FTSDC010_BWR_CAPS_4BIT:
mmc->host_caps |= MMC_MODE_4BIT;
break;
case FTSDC010_BWR_CAPS_8BIT:
mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
break;
default:
break;
}
#ifdef CONFIG_SYS_CLK_FREQ
chip->sclk = CONFIG_SYS_CLK_FREQ;
#else
chip->sclk = clk_get_rate("SDC");
#endif
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_max = chip->sclk / 2;
mmc->f_min = chip->sclk / 0x100;
mmc->block_dev.part_type = PART_TYPE_DOS;
chip->cfg.name = "ftsdc010";
chip->cfg.ops = &ftsdc010_ops;
chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
case FTSDC010_BWR_CAPS_4BIT:
chip->cfg.host_caps |= MMC_MODE_4BIT;
break;
case FTSDC010_BWR_CAPS_8BIT:
chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
break;
default:
break;
}
mmc_register(mmc);
chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
chip->cfg.f_max = chip->sclk / 2;
chip->cfg.f_min = chip->sclk / 0x100;
chip->cfg.part_type = PART_TYPE_DOS;
chip->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
mmc = mmc_create(&chip->cfg, chip);
if (mmc == NULL) {
free(chip);
return -ENOMEM;
}
return 0;
}

53
drivers/mmc/gen_atmel_mci.c
View File

@ -55,7 +55,7 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
/* Setup for MCI Clock and Block Size */
static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
{
atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
atmel_mci_t *mci = mmc->priv;
u32 bus_hz = get_mci_clk_rate();
u32 clkdiv = 255;
@ -165,7 +165,7 @@ io_fail:
static int
mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
atmel_mci_t *mci = mmc->priv;
u32 cmdr;
u32 error_flags = 0;
u32 status;
@ -289,7 +289,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
/* Entered into mmc structure during driver init */
static void mci_set_ios(struct mmc *mmc)
{
atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
atmel_mci_t *mci = mmc->priv;
int bus_width = mmc->bus_width;
unsigned int version = atmel_mci_get_version(mci);
int busw;
@ -325,7 +325,7 @@ static void mci_set_ios(struct mmc *mmc)
/* Entered into mmc structure during driver init */
static int mci_init(struct mmc *mmc)
{
atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
atmel_mci_t *mci = mmc->priv;
/* Initialize controller */
writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
@ -344,6 +344,12 @@ static int mci_init(struct mmc *mmc)
return 0;
}
static const struct mmc_ops atmel_mci_ops = {
.send_cmd = mci_send_cmd,
.set_ios = mci_set_ios,
.init = mci_init,
};
/*
* This is the only exported function
*
@ -351,40 +357,45 @@ static int mci_init(struct mmc *mmc)
*/
int atmel_mci_init(void *regs)
{
struct mmc *mmc = malloc(sizeof(struct mmc));
struct mmc *mmc;
struct mmc_config *cfg;
struct atmel_mci *mci;
unsigned int version;
if (!mmc)
cfg = malloc(sizeof(*cfg));
if (cfg == NULL)
return -1;
memset(cfg, 0, sizeof(*cfg));
strcpy(mmc->name, "mci");
mmc->priv = regs;
mmc->send_cmd = mci_send_cmd;
mmc->set_ios = mci_set_ios;
mmc->init = mci_init;
mmc->getcd = NULL;
mmc->getwp = NULL;
mci = (struct atmel_mci *)regs;
cfg->name = "mci";
cfg->ops = &atmel_mci_ops;
/* need to be able to pass these in on a board by board basis */
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mci = (struct atmel_mci *)mmc->priv;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
version = atmel_mci_get_version(mci);
if ((version & 0xf00) >= 0x300)
mmc->host_caps = MMC_MODE_8BIT;
cfg->host_caps = MMC_MODE_8BIT;
mmc->host_caps |= MMC_MODE_4BIT;
cfg->host_caps |= MMC_MODE_4BIT;
/*
* min and max frequencies determined by
* max and min of clock divider
*/
mmc->f_min = get_mci_clk_rate() / (2*256);
mmc->f_max = get_mci_clk_rate() / (2*1);
cfg->f_min = get_mci_clk_rate() / (2*256);
cfg->f_max = get_mci_clk_rate() / (2*1);
mmc->b_max = 0;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
mmc_register(mmc);
mmc = mmc_create(cfg, regs);
if (mmc == NULL) {
free(cfg);
return -1;
}
/* NOTE: possibly leaking the cfg structure */
return 0;
}

111
drivers/mmc/mmc.c
View File

@ -17,11 +17,6 @@
#include <div64.h>
#include "mmc_private.h"
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
#endif
static struct list_head mmc_devices;
static int cur_dev_num = -1;
@ -37,8 +32,8 @@ int mmc_getwp(struct mmc *mmc)
wp = board_mmc_getwp(mmc);
if (wp < 0) {
if (mmc->getwp)
wp = mmc->getwp(mmc);
if (mmc->cfg->ops->getwp)
wp = mmc->cfg->ops->getwp(mmc);
else
wp = 0;
}
@ -63,7 +58,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
printf("CMD_SEND:%d\n", cmd->cmdidx);
printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
ret = mmc->send_cmd(mmc, cmd, data);
ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
switch (cmd->resp_type) {
case MMC_RSP_NONE:
printf("\t\tMMC_RSP_NONE\n");
@ -106,7 +101,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
break;
}
#else
ret = mmc->send_cmd(mmc, cmd, data);
ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
#endif
return ret;
}
@ -253,7 +248,8 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
return 0;
do {
cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo;
cur = (blocks_todo > mmc->cfg->b_max) ?
mmc->cfg->b_max : blocks_todo;
if(mmc_read_blocks(mmc, dst, start, cur) != cur)
return 0;
blocks_todo -= cur;
@ -312,7 +308,7 @@ static int sd_send_op_cond(struct mmc *mmc)
* specified.
*/
cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
(mmc->voltages & 0xff8000);
(mmc->cfg->voltages & 0xff8000);
if (mmc->version == SD_VERSION_2)
cmd.cmdarg |= OCR_HCS;
@ -361,11 +357,11 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
cmd->cmdarg = 0;
if (use_arg && !mmc_host_is_spi(mmc)) {
cmd->cmdarg =
(mmc->voltages &
(mmc->cfg->voltages &
(mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
(mmc->op_cond_response & OCR_ACCESS_MODE);
if (mmc->host_caps & MMC_MODE_HC)
if (mmc->cfg->host_caps & MMC_MODE_HC)
cmd->cmdarg |= OCR_HCS;
}
err = mmc_send_cmd(mmc, cmd, NULL);
@ -578,8 +574,8 @@ int mmc_getcd(struct mmc *mmc)
cd = board_mmc_getcd(mmc);
if (cd < 0) {
if (mmc->getcd)
cd = mmc->getcd(mmc);
if (mmc->cfg->ops->getcd)
cd = mmc->cfg->ops->getcd(mmc);
else
cd = 1;
}
@ -703,8 +699,8 @@ retry_scr:
* This can avoid furthur problem when the card runs in different
* mode between the host.
*/
if (!((mmc->host_caps & MMC_MODE_HS_52MHz) &&
(mmc->host_caps & MMC_MODE_HS)))
if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
(mmc->cfg->host_caps & MMC_MODE_HS)))
return 0;
err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
@ -751,16 +747,17 @@ static const int multipliers[] = {
static void mmc_set_ios(struct mmc *mmc)
{
mmc->set_ios(mmc);
if (mmc->cfg->ops->set_ios)
mmc->cfg->ops->set_ios(mmc);
}
void mmc_set_clock(struct mmc *mmc, uint clock)
{
if (clock > mmc->f_max)
clock = mmc->f_max;
if (clock > mmc->cfg->f_max)
clock = mmc->cfg->f_max;
if (clock < mmc->f_min)
clock = mmc->f_min;
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
mmc->clock = clock;
@ -1026,7 +1023,7 @@ static int mmc_startup(struct mmc *mmc)
return err;
/* Restrict card's capabilities by what the host can do */
mmc->card_caps &= mmc->host_caps;
mmc->card_caps &= mmc->cfg->host_caps;
if (IS_SD(mmc)) {
if (mmc->card_caps & MMC_MODE_4BIT) {
@ -1081,7 +1078,7 @@ static int mmc_startup(struct mmc *mmc)
* this bus width, if it's more than 1
*/
if (extw != EXT_CSD_BUS_WIDTH_1 &&
!(mmc->host_caps & ext_to_hostcaps[extw]))
!(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
continue;
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
@ -1154,7 +1151,7 @@ static int mmc_send_if_cond(struct mmc *mmc)
cmd.cmdidx = SD_CMD_SEND_IF_COND;
/* We set the bit if the host supports voltages between 2.7 and 3.6 V */
cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa;
cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
cmd.resp_type = MMC_RSP_R7;
err = mmc_send_cmd(mmc, &cmd, NULL);
@ -1170,8 +1167,33 @@ static int mmc_send_if_cond(struct mmc *mmc)
return 0;
}
int mmc_register(struct mmc *mmc)
/* not used any more */
int __deprecated mmc_register(struct mmc *mmc)
{
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("%s is deprecated! use mmc_create() instead.\n", __func__);
#endif
return -1;
}
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
{
struct mmc *mmc;
/* quick validation */
if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
return NULL;
mmc = calloc(1, sizeof(*mmc));
if (mmc == NULL)
return NULL;
mmc->cfg = cfg;
mmc->priv = priv;
/* the following chunk was mmc_register() */
/* Setup dsr related values */
mmc->dsr_imp = 0;
mmc->dsr = 0xffffffff;
@ -1182,14 +1204,21 @@ int mmc_register(struct mmc *mmc)
mmc->block_dev.block_read = mmc_bread;
mmc->block_dev.block_write = mmc_bwrite;
mmc->block_dev.block_erase = mmc_berase;
if (!mmc->b_max)
mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
INIT_LIST_HEAD (&mmc->link);
/* setup initial part type */
mmc->block_dev.part_type = mmc->cfg->part_type;
list_add_tail (&mmc->link, &mmc_devices);
INIT_LIST_HEAD(&mmc->link);
return 0;
list_add_tail(&mmc->link, &mmc_devices);
return mmc;
}
void mmc_destroy(struct mmc *mmc)
{
/* only freeing memory for now */
free(mmc);
}
#ifdef CONFIG_PARTITIONS
@ -1207,7 +1236,8 @@ int mmc_start_init(struct mmc *mmc)
{
int err;
if (mmc_getcd(mmc) == 0) {
/* we pretend there's no card when init is NULL */
if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
mmc->has_init = 0;
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC: no card present\n");
@ -1218,7 +1248,8 @@ int mmc_start_init(struct mmc *mmc)
if (mmc->has_init)
return 0;
err = mmc->init(mmc);
/* made sure it's not NULL earlier */
err = mmc->cfg->ops->init(mmc);
if (err)
return err;
@ -1320,7 +1351,7 @@ void print_mmc_devices(char separator)
list_for_each(entry, &mmc_devices) {
m = list_entry(entry, struct mmc, link);
printf("%s: %d", m->name, m->block_dev.dev);
printf("%s: %d", m->cfg->name, m->block_dev.dev);
if (entry->next != &mmc_devices)
printf("%c ", separator);
@ -1482,4 +1513,16 @@ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
return err;
return 0;
}
/*
* Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
* for enable. Note that this is a write-once field for non-zero values.
*
* Returns 0 on success.
*/
int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
{
return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
enable);
}
#endif

50
drivers/mmc/mmc_spi.c
View File

@ -92,7 +92,7 @@ static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf,
spi_xfer(spi, 2 * 8, NULL, &crc, 0);
#ifdef CONFIG_MMC_SPI_CRC_ON
if (swab16(cyg_crc16(buf, bsize)) != crc) {
debug("%s: CRC error\n", mmc->name);
debug("%s: CRC error\n", mmc->cfg->name);
r1 = R1_SPI_COM_CRC;
break;
}
@ -238,6 +238,7 @@ done:
static void mmc_spi_set_ios(struct mmc *mmc)
{
struct spi_slave *spi = mmc->priv;
debug("%s: clock %u\n", __func__, mmc->clock);
if (mmc->clock)
spi_set_speed(spi, mmc->clock);
@ -246,7 +247,6 @@ static void mmc_spi_set_ios(struct mmc *mmc)
static int mmc_spi_init_p(struct mmc *mmc)
{
struct spi_slave *spi = mmc->priv;
mmc->clock = 0;
spi_set_speed(spi, MMC_SPI_MIN_CLOCK);
spi_claim_bus(spi);
/* cs deactivated for 100+ clock */
@ -255,33 +255,37 @@ static int mmc_spi_init_p(struct mmc *mmc)
return 0;
}
static const struct mmc_ops mmc_spi_ops = {
.send_cmd = mmc_spi_request,
.set_ios = mmc_spi_set_ios,
.init = mmc_spi_init_p,
};
static struct mmc_config mmc_spi_cfg = {
.name = "MMC_SPI",
.ops = &mmc_spi_ops,
.host_caps = MMC_MODE_SPI,
.voltages = MMC_SPI_VOLTAGE,
.f_min = MMC_SPI_MIN_CLOCK,
.part_type = PART_TYPE_DOS,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
{
struct mmc *mmc;
struct spi_slave *spi;
mmc = malloc(sizeof(*mmc));
if (!mmc)
spi = spi_setup_slave(bus, cs, speed, mode);
if (spi == NULL)
return NULL;
memset(mmc, 0, sizeof(*mmc));
mmc->priv = spi_setup_slave(bus, cs, speed, mode);
if (!mmc->priv) {
free(mmc);
mmc_spi_cfg.f_max = speed;
mmc = mmc_create(&mmc_spi_cfg, spi);
if (mmc == NULL) {
spi_free_slave(spi);
return NULL;
}
sprintf(mmc->name, "MMC_SPI");
mmc->send_cmd = mmc_spi_request;
mmc->set_ios = mmc_spi_set_ios;
mmc->init = mmc_spi_init_p;
mmc->getcd = NULL;
mmc->getwp = NULL;
mmc->host_caps = MMC_MODE_SPI;
mmc->voltages = MMC_SPI_VOLTAGE;
mmc->f_max = speed;
mmc->f_min = MMC_SPI_MIN_CLOCK;
mmc->block_dev.part_type = PART_TYPE_DOS;
mmc_register(mmc);
return mmc;
}

3
drivers/mmc/mmc_write.c
View File

@ -167,7 +167,8 @@ ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src)
return 0;
do {
cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo;
cur = (blocks_todo > mmc->cfg->b_max) ?
mmc->cfg->b_max : blocks_todo;
if (mmc_write_blocks(mmc, start, cur, src) != cur)
return 0;
blocks_todo -= cur;

45
drivers/mmc/mxcmmc.c
View File

@ -122,6 +122,8 @@ struct mxcmci_host {
};
static struct mxcmci_host mxcmci_host;
/* maintainer note: do we really want to have a global host pointer? */
static struct mxcmci_host *host = &mxcmci_host;
static inline int mxcmci_use_dma(struct mxcmci_host *host)
@ -485,35 +487,30 @@ static int mxcmci_init(struct mmc *mmc)
return 0;
}
static const struct mmc_ops mxcmci_ops = {
.send_cmd = mxcmci_request,
.set_ios = mxcmci_set_ios,
.init = mxcmci_init,
};
static struct mmc_config mxcmci_cfg = {
.name = "MXC MCI",
.ops = &mxcmci_ops,
.host_caps = MMC_MODE_4BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
static int mxcmci_initialize(bd_t *bis)
{
struct mmc *mmc = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
sprintf(mmc->name, "MXC MCI");
mmc->send_cmd = mxcmci_request;
mmc->set_ios = mxcmci_set_ios;
mmc->init = mxcmci_init;
mmc->getcd = NULL;
mmc->getwp = NULL;
mmc->host_caps = MMC_MODE_4BIT;
host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
mmc->priv = host;
host->mmc = mmc;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
mmc->f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
mmc->f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
mmc->b_max = 0;
mmc_register(mmc);
host->mmc = mmc_create(&mxcmci_cfg, host);
if (host->mmc == NULL)
return -1;
return 0;
}

48
drivers/mmc/mxsmmc.c
View File

@ -35,6 +35,7 @@ struct mxsmmc_priv {
int (*mmc_is_wp)(int);
int (*mmc_cd)(int);
struct mxs_dma_desc *desc;
struct mmc_config cfg; /* mmc configuration */
};
#define MXSMMC_MAX_TIMEOUT 10000
@ -134,7 +135,7 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
static int
mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mxsmmc_priv *priv = mmc->priv;
struct mxs_ssp_regs *ssp_regs = priv->regs;
uint32_t reg;
int timeout;
@ -305,7 +306,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
static void mxsmmc_set_ios(struct mmc *mmc)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mxsmmc_priv *priv = mmc->priv;
struct mxs_ssp_regs *ssp_regs = priv->regs;
/* Set the clock speed */
@ -334,7 +335,7 @@ static void mxsmmc_set_ios(struct mmc *mmc)
static int mxsmmc_init(struct mmc *mmc)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mxsmmc_priv *priv = mmc->priv;
struct mxs_ssp_regs *ssp_regs = priv->regs;
/* Reset SSP */
@ -363,6 +364,12 @@ static int mxsmmc_init(struct mmc *mmc)
return 0;
}
static const struct mmc_ops mxsmmc_ops = {
.send_cmd = mxsmmc_send_cmd,
.set_ios = mxsmmc_set_ios,
.init = mxsmmc_init,
};
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
{
struct mmc *mmc = NULL;
@ -373,20 +380,13 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
if (!mxs_ssp_bus_id_valid(id))
return -ENODEV;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
priv = malloc(sizeof(struct mxsmmc_priv));
if (!priv) {
free(mmc);
if (!priv)
return -ENOMEM;
}
priv->desc = mxs_dma_desc_alloc();
if (!priv->desc) {
free(priv);
free(mmc);
return -ENOMEM;
}
@ -399,17 +399,12 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
priv->id = id;
priv->regs = mxs_ssp_regs_by_bus(id);
sprintf(mmc->name, "MXS MMC");
mmc->send_cmd = mxsmmc_send_cmd;
mmc->set_ios = mxsmmc_set_ios;
mmc->init = mxsmmc_init;
mmc->getcd = NULL;
mmc->getwp = NULL;
mmc->priv = priv;
priv->cfg.name = "MXS MMC";
priv->cfg.ops = &mxsmmc_ops;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC;
@ -419,10 +414,15 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
* CLOCK_DIVIDE has to be an even value from 2 to 254, and
* CLOCK_RATE could be any integer from 0 to 255.
*/
mmc->f_min = 400000;
mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
mmc->b_max = 0x20;
priv->cfg.f_min = 400000;
priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
priv->cfg.b_max = 0x20;
mmc_register(mmc);
mmc = mmc_create(&priv->cfg, priv);
if (mmc == NULL) {
mxs_dma_desc_free(priv->desc);
free(priv);
return -ENOMEM;
}
return 0;
}

142
drivers/mmc/omap_hsmmc.c
View File

@ -24,6 +24,7 @@
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
@ -35,14 +36,25 @@
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
/* simplify defines to OMAP_HSMMC_USE_GPIO */
#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
#define OMAP_HSMMC_USE_GPIO
#else
#undef OMAP_HSMMC_USE_GPIO
#endif
/* common definitions for all OMAPs */
#define SYSCTL_SRC (1 << 25)
#define SYSCTL_SRD (1 << 26)
struct omap_hsmmc_data {
struct hsmmc *base_addr;
struct mmc_config cfg;
#ifdef OMAP_HSMMC_USE_GPIO
int cd_gpio;
int wp_gpio;
#endif
};
/* If we fail after 1 second wait, something is really bad */
@ -51,11 +63,8 @@ struct omap_hsmmc_data {
static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int siz);
static struct mmc hsmmc_dev[3];
static struct omap_hsmmc_data hsmmc_dev_data[3];
#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
#ifdef OMAP_HSMMC_USE_GPIO
static int omap_mmc_setup_gpio_in(int gpio, const char *label)
{
if (!gpio_is_valid(gpio))
@ -69,26 +78,6 @@ static int omap_mmc_setup_gpio_in(int gpio, const char *label)
return gpio;
}
static int omap_mmc_getcd(struct mmc *mmc)
{
int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
return gpio_get_value(cd_gpio);
}
static int omap_mmc_getwp(struct mmc *mmc)
{
int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio;
return gpio_get_value(wp_gpio);
}
#else
static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
{
return -1;
}
#define omap_mmc_getcd NULL
#define omap_mmc_getwp NULL
#endif
#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
@ -158,7 +147,7 @@ unsigned char mmc_board_init(struct mmc *mmc)
&t2_base->devconf1);
/* Change from default of 52MHz to 26MHz if necessary */
if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
&t2_base->ctl_prog_io1);
@ -213,7 +202,7 @@ void mmc_init_stream(struct hsmmc *mmc_base)
}
static int mmc_init_setup(struct mmc *mmc)
static int omap_hsmmc_init_setup(struct mmc *mmc)
{
struct hsmmc *mmc_base;
unsigned int reg_val;
@ -322,7 +311,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
}
}
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct hsmmc *mmc_base;
@ -552,7 +541,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
return 0;
}
static void mmc_set_ios(struct mmc *mmc)
static void omap_hsmmc_set_ios(struct mmc *mmc)
{
struct hsmmc *mmc_base;
unsigned int dsor = 0;
@ -606,19 +595,58 @@ static void mmc_set_ios(struct mmc *mmc)
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}
#ifdef OMAP_HSMMC_USE_GPIO
static int omap_hsmmc_getcd(struct mmc *mmc)
{
struct omap_hsmmc_data *priv_data = mmc->priv;
int cd_gpio;
/* if no CD return as 1 */
cd_gpio = priv_data->cd_gpio;
if (cd_gpio < 0)
return 1;
return gpio_get_value(cd_gpio);
}
static int omap_hsmmc_getwp(struct mmc *mmc)
{
struct omap_hsmmc_data *priv_data = mmc->priv;
int wp_gpio;
/* if no WP return as 0 */
wp_gpio = priv_data->wp_gpio;
if (wp_gpio < 0)
return 0;
return gpio_get_value(wp_gpio);
}
#endif
static const struct mmc_ops omap_hsmmc_ops = {
.send_cmd = omap_hsmmc_send_cmd,
.set_ios = omap_hsmmc_set_ios,
.init = omap_hsmmc_init_setup,
#ifdef OMAP_HSMMC_USE_GPIO
.getcd = omap_hsmmc_getcd,
.getwp = omap_hsmmc_getwp,
#endif
};
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
struct mmc *mmc = &hsmmc_dev[dev_index];
struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC;
struct mmc *mmc;
struct omap_hsmmc_data *priv_data;
struct mmc_config *cfg;
uint host_caps_val;
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
mmc->priv = priv_data;
priv_data = malloc(sizeof(*priv_data));
if (priv_data == NULL)
return -1;
host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC;
switch (dev_index) {
case 0:
@ -647,42 +675,46 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
#ifdef OMAP_HSMMC_USE_GPIO
/* on error gpio values are set to -1, which is what we want */
priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
if (priv_data->cd_gpio != -1)
mmc->getcd = omap_mmc_getcd;
priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
if (priv_data->wp_gpio != -1)
mmc->getwp = omap_mmc_getwp;
#endif
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = host_caps_val & ~host_caps_mask;
cfg = &priv_data->cfg;
mmc->f_min = 400000;
cfg->name = "OMAP SD/MMC";
cfg->ops = &omap_hsmmc_ops;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = host_caps_val & ~host_caps_mask;
cfg->f_min = 400000;
if (f_max != 0)
mmc->f_max = f_max;
cfg->f_max = f_max;
else {
if (mmc->host_caps & MMC_MODE_HS) {
if (mmc->host_caps & MMC_MODE_HS_52MHz)
mmc->f_max = 52000000;
if (cfg->host_caps & MMC_MODE_HS) {
if (cfg->host_caps & MMC_MODE_HS_52MHz)
cfg->f_max = 52000000;
else
mmc->f_max = 26000000;
cfg->f_max = 26000000;
} else
mmc->f_max = 20000000;
cfg->f_max = 20000000;
}
mmc->b_max = 0;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
mmc->b_max = 1;
cfg->b_max = 1;
#endif
mmc_register(mmc);
mmc = mmc_create(cfg, priv_data);
if (mmc == NULL)
return -1;
return 0;
}

70
drivers/mmc/pxa_mmc_gen.c
View File

@ -52,7 +52,7 @@ struct pxa_mmc_priv {
/* Wait for bit to be set */
static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
unsigned int timeout = PXA_MMC_TIMEOUT;
@ -71,7 +71,7 @@ static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
static int pxa_mmc_stop_clock(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
unsigned int timeout = PXA_MMC_TIMEOUT;
@ -100,7 +100,7 @@ static int pxa_mmc_stop_clock(struct mmc *mmc)
static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
uint32_t cmdat)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
int ret;
@ -143,7 +143,7 @@ static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t a, b, c;
int i;
@ -185,7 +185,7 @@ static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t len;
uint32_t *buf = (uint32_t *)data->dest;
@ -221,7 +221,7 @@ static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t len;
uint32_t *buf = (uint32_t *)data->src;
@ -264,7 +264,7 @@ static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t cmdat = 0;
int ret;
@ -317,7 +317,7 @@ static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
static void pxa_mmc_set_ios(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t tmp;
uint32_t pxa_mmc_clock;
@ -335,7 +335,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc)
/* Set clock to the card the usual way. */
pxa_mmc_clock = 0;
tmp = mmc->f_max / mmc->clock;
tmp = mmc->cfg->f_max / mmc->clock;
tmp += tmp % 2;
while (tmp > 1) {
@ -348,7 +348,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc)
static int pxa_mmc_init(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
/* Make sure the clock are stopped */
@ -366,6 +366,22 @@ static int pxa_mmc_init(struct mmc *mmc)
return 0;
}
static const struct mmc_ops pxa_mmc_ops = {
.send_cmd = pxa_mmc_request,
.set_ios = pxa_mmc_set_ios,
.init = pxa_mmc_init,
};
static struct mmc_config pxa_mmc_cfg = {
.name = "PXA MMC",
.ops = &pxa_mmc_ops,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.f_max = PXAMMC_MAX_SPEED,
.f_min = PXAMMC_MIN_SPEED,
.host_caps = PXAMMC_HOST_CAPS,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
int pxa_mmc_register(int card_index)
{
struct mmc *mmc;
@ -373,13 +389,11 @@ int pxa_mmc_register(int card_index)
uint32_t reg;
int ret = -ENOMEM;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
goto err0;
priv = malloc(sizeof(struct pxa_mmc_priv));
if (!priv)
goto err1;
goto err0;
memset(priv, 0, sizeof(*priv));
switch (card_index) {
case 0:
@ -389,26 +403,12 @@ int pxa_mmc_register(int card_index)
priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
break;
default:
ret = -EINVAL;
printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
card_index);
goto err2;
goto err1;
}
mmc->priv = priv;
sprintf(mmc->name, "PXA MMC");
mmc->send_cmd = pxa_mmc_request;
mmc->set_ios = pxa_mmc_set_ios;
mmc->init = pxa_mmc_init;
mmc->getcd = NULL;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_max = PXAMMC_MAX_SPEED;
mmc->f_min = PXAMMC_MIN_SPEED;
mmc->host_caps = PXAMMC_HOST_CAPS;
mmc->b_max = 0;
#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
reg = readl(CKEN);
reg |= CKEN12_MMC;
@ -419,14 +419,14 @@ int pxa_mmc_register(int card_index)
writel(reg, CKENA);
#endif
mmc_register(mmc);
mmc = mmc_create(&pxa_mmc_cfg, priv);
if (mmc == NULL)
goto err1;
return 0;
err2:
free(priv);
err1:
free(mmc);
free(priv);
err0:
return ret;
}

84
drivers/mmc/sdhci.c
View File

@ -127,7 +127,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
struct sdhci_host *host = mmc->priv;
unsigned int stat = 0;
int ret = 0;
int trans_bytes = 0, is_aligned = 1;
@ -268,7 +268,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
struct sdhci_host *host = mmc->priv;
unsigned int div, clk, timeout;
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
@ -278,18 +278,18 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
/* Version 3.00 divisors must be a multiple of 2. */
if (mmc->f_max <= clock)
if (mmc->cfg->f_max <= clock)
div = 1;
else {
for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
if ((mmc->f_max / div) <= clock)
if ((mmc->cfg->f_max / div) <= clock)
break;
}
}
} else {
/* Version 2.00 divisors must be a power of 2. */
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
if ((mmc->f_max / div) <= clock)
if ((mmc->cfg->f_max / div) <= clock)
break;
}
}
@ -358,7 +358,7 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
void sdhci_set_ios(struct mmc *mmc)
{
u32 ctrl;
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
struct sdhci_host *host = mmc->priv;
if (host->set_control_reg)
host->set_control_reg(host);
@ -395,7 +395,7 @@ void sdhci_set_ios(struct mmc *mmc)
int sdhci_init(struct mmc *mmc)
{
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
struct sdhci_host *host = mmc->priv;
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
aligned_buffer = memalign(8, 512*1024);
@ -406,7 +406,7 @@ int sdhci_init(struct mmc *mmc)
}
}
sdhci_set_power(host, fls(mmc->voltages) - 1);
sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
if (host->quirks & SDHCI_QUIRK_NO_CD) {
unsigned int status;
@ -430,26 +430,19 @@ int sdhci_init(struct mmc *mmc)
return 0;
}
static const struct mmc_ops sdhci_ops = {
.send_cmd = sdhci_send_command,
.set_ios = sdhci_set_ios,
.init = sdhci_init,
};
int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
struct mmc *mmc;
unsigned int caps;
mmc = malloc(sizeof(struct mmc));
if (!mmc) {
printf("%s: mmc malloc fail!\n", __func__);
return -1;
}
mmc->priv = host;
host->mmc = mmc;
sprintf(mmc->name, "%s", host->name);
mmc->send_cmd = sdhci_send_command;
mmc->set_ios = sdhci_set_ios;
mmc->init = sdhci_init;
mmc->getcd = NULL;
mmc->getwp = NULL;
host->cfg.name = host->name;
host->cfg.ops = &sdhci_ops;
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDMA
@ -461,51 +454,60 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
#endif
if (max_clk)
mmc->f_max = max_clk;
host->cfg.f_max = max_clk;
else {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
else
mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
mmc->f_max *= 1000000;
host->cfg.f_max *= 1000000;
}
if (mmc->f_max == 0) {
if (host->cfg.f_max == 0) {
printf("%s: Hardware doesn't specify base clock frequency\n",
__func__);
return -1;
}
if (min_clk)
mmc->f_min = min_clk;
host->cfg.f_min = min_clk;
else {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
host->cfg.f_min = host->cfg.f_max /
SDHCI_MAX_DIV_SPEC_300;
else
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
host->cfg.f_min = host->cfg.f_max /
SDHCI_MAX_DIV_SPEC_200;
}
mmc->voltages = 0;
host->cfg.voltages = 0;
if (caps & SDHCI_CAN_VDD_330)
mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
if (caps & SDHCI_CAN_VDD_300)
mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
if (caps & SDHCI_CAN_VDD_180)
mmc->voltages |= MMC_VDD_165_195;
host->cfg.voltages |= MMC_VDD_165_195;
if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
mmc->voltages |= host->voltages;
host->cfg.voltages |= host->voltages;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
if (caps & SDHCI_CAN_DO_8BIT)
mmc->host_caps |= MMC_MODE_8BIT;
host->cfg.host_caps |= MMC_MODE_8BIT;
}
if (host->host_caps)
mmc->host_caps |= host->host_caps;
host->cfg.host_caps |= host->host_caps;
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
sdhci_reset(host, SDHCI_RESET_ALL);
mmc_register(mmc);
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL) {
printf("%s: mmc create fail!\n", __func__);
return -1;
}
return 0;
}

55
drivers/mmc/sh_mmcif.c
View File

@ -20,11 +20,6 @@
#define DRIVER_NAME "sh_mmcif"
static void *mmc_priv(struct mmc *mmc)
{
return (void *)mmc->priv;
}
static int sh_mmcif_intr(void *dev_id)
{
struct sh_mmcif_host *host = dev_id;
@ -522,7 +517,7 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct sh_mmcif_host *host = mmc_priv(mmc);
struct sh_mmcif_host *host = mmc->priv;
int ret;
WATCHDOG_RESET();
@ -550,7 +545,7 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
static void sh_mmcif_set_ios(struct mmc *mmc)
{
struct sh_mmcif_host *host = mmc_priv(mmc);
struct sh_mmcif_host *host = mmc->priv;
if (mmc->clock)
sh_mmcif_clock_control(host, mmc->clock);
@ -567,44 +562,48 @@ static void sh_mmcif_set_ios(struct mmc *mmc)
static int sh_mmcif_init(struct mmc *mmc)
{
struct sh_mmcif_host *host = mmc_priv(mmc);
struct sh_mmcif_host *host = mmc->priv;
sh_mmcif_sync_reset(host);
sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
return 0;
}
static const struct mmc_ops sh_mmcif_ops = {
.send_cmd = sh_mmcif_request,
.set_ios = sh_mmcif_set_ios,
.init = sh_mmcif_init,
};
static struct mmc_config sh_mmcif_cfg = {
.name = DRIVER_NAME,
.ops = &sh_mmcif_ops,
.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
MMC_MODE_8BIT | MMC_MODE_HC,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.f_min = CLKDEV_MMC_INIT,
.f_max = CLKDEV_EMMC_DATA,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
int mmcif_mmc_init(void)
{
int ret = 0;
struct mmc *mmc;
struct sh_mmcif_host *host = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
ret = -ENOMEM;
memset(mmc, 0, sizeof(*mmc));
host = malloc(sizeof(struct sh_mmcif_host));
if (!host)
ret = -ENOMEM;
return -ENOMEM;
memset(host, 0, sizeof(*host));
mmc->f_min = CLKDEV_MMC_INIT;
mmc->f_max = CLKDEV_EMMC_DATA;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
MMC_MODE_8BIT | MMC_MODE_HC;
memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
mmc->send_cmd = sh_mmcif_request;
mmc->set_ios = sh_mmcif_set_ios;
mmc->init = sh_mmcif_init;
mmc->getcd = NULL;
mmc->getwp = NULL;
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
host->clk = CONFIG_SH_MMCIF_CLK;
mmc->priv = host;
mmc_register(mmc);
mmc = mmc_create(&sh_mmcif_cfg, host);
if (mmc == NULL) {
free(host);
return -ENOMEM;
}
return ret;
return 0;
}

53
drivers/mmc/tegra_mmc.c
View File

@ -18,7 +18,6 @@
DECLARE_GLOBAL_DATA_PTR;
struct mmc mmc_dev[MAX_HOSTS];
struct mmc_host mmc_host[MAX_HOSTS];
#ifndef CONFIG_OF_CONTROL
@ -145,7 +144,7 @@ static int mmc_wait_inhibit(struct mmc_host *host,
static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data, struct bounce_buffer *bbstate)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
struct mmc_host *host = mmc->priv;
int flags, i;
int result;
unsigned int mask = 0;
@ -314,7 +313,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
return 0;
}
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
void *buf;
@ -396,7 +395,7 @@ out:
host->clock = clock;
}
static void mmc_set_ios(struct mmc *mmc)
static void tegra_mmc_set_ios(struct mmc *mmc)
{
struct mmc_host *host = mmc->priv;
unsigned char ctrl;
@ -456,7 +455,7 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
}
/* Set SD bus voltage & enable bus power */
mmc_set_power(host, fls(mmc->voltages) - 1);
mmc_set_power(host, fls(mmc->cfg->voltages) - 1);
debug("%s: power control = %02X, host control = %02X\n", __func__,
readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
@ -464,9 +463,9 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
pad_init_mmc(host);
}
static int mmc_core_init(struct mmc *mmc)
static int tegra_mmc_core_init(struct mmc *mmc)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
struct mmc_host *host = mmc->priv;
unsigned int mask;
debug(" mmc_core_init called\n");
@ -511,7 +510,7 @@ static int mmc_core_init(struct mmc *mmc)
int tegra_mmc_getcd(struct mmc *mmc)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
struct mmc_host *host = mmc->priv;
debug("tegra_mmc_getcd called\n");
@ -521,6 +520,13 @@ int tegra_mmc_getcd(struct mmc *mmc)
return 1;
}
static const struct mmc_ops tegra_mmc_ops = {
.send_cmd = tegra_mmc_send_cmd,
.set_ios = tegra_mmc_set_ios,
.init = tegra_mmc_core_init,
.getcd = tegra_mmc_getcd,
};
static int do_mmc_init(int dev_index)
{
struct mmc_host *host;
@ -554,23 +560,18 @@ static int do_mmc_init(int dev_index)
debug(" CD GPIO name = %s\n", host->cd_gpio.name);
}
mmc = &mmc_dev[dev_index];
memset(&host->cfg, 0, sizeof(host->cfg));
sprintf(mmc->name, "Tegra SD/MMC");
mmc->priv = host;
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
mmc->getcd = tegra_mmc_getcd;
mmc->getwp = NULL;
host->cfg.name = "Tegra SD/MMC";
host->cfg.ops = &tegra_mmc_ops;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = 0;
host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->cfg.host_caps = 0;
if (host->width == 8)
mmc->host_caps |= MMC_MODE_8BIT;
host->cfg.host_caps |= MMC_MODE_8BIT;
if (host->width >= 4)
mmc->host_caps |= MMC_MODE_4BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
host->cfg.host_caps |= MMC_MODE_4BIT;
host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
/*
* min freq is for card identification, and is the highest
@ -578,10 +579,14 @@ static int do_mmc_init(int dev_index)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
*/
mmc->f_min = 375000;
mmc->f_max = 48000000;
host->cfg.f_min = 375000;
host->cfg.f_max = 48000000;
mmc_register(mmc);
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
mmc = mmc_create(&host->cfg, host);
if (mmc == NULL)
return -1;
return 0;
}

2
drivers/net/designware.h
View File

@ -110,7 +110,7 @@ struct dmamacdescr {
u32 dmamac_cntl;
void *dmamac_addr;
struct dmamacdescr *dmamac_next;
} __aligned(16);
} __aligned(ARCH_DMA_MINALIGN);
/*
* txrx_status definitions

48
drivers/usb/gadget/f_dfu.c
View File

@ -164,9 +164,14 @@ static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req)
dfu_write(dfu_get_entity(f_dfu->altsetting), req->buf,
req->length, f_dfu->blk_seq_num);
}
if (req->length == 0)
puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n");
static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req)
{
struct f_dfu *f_dfu = req->context;
dfu_flush(dfu_get_entity(f_dfu->altsetting), req->buf,
req->length, f_dfu->blk_seq_num);
}
static void handle_getstatus(struct usb_request *req)
@ -174,19 +179,22 @@ static void handle_getstatus(struct usb_request *req)
struct dfu_status *dstat = (struct dfu_status *)req->buf;
struct f_dfu *f_dfu = req->context;
dfu_set_poll_timeout(dstat, 0);
switch (f_dfu->dfu_state) {
case DFU_STATE_dfuDNLOAD_SYNC:
case DFU_STATE_dfuDNBUSY:
f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_IDLE;
break;
case DFU_STATE_dfuMANIFEST_SYNC:
f_dfu->dfu_state = DFU_STATE_dfuMANIFEST;
break;
case DFU_STATE_dfuMANIFEST:
dfu_set_poll_timeout(dstat, DFU_MANIFEST_POLL_TIMEOUT);
default:
break;
}
dfu_set_poll_timeout(dstat, 0);
if (f_dfu->poll_timeout)
if (!(f_dfu->blk_seq_num %
(dfu_get_buf_size() / DFU_USB_BUFSIZ)))
@ -446,10 +454,11 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu,
switch (ctrl->bRequest) {
case USB_REQ_DFU_GETSTATUS:
/* We're MainfestationTolerant */
f_dfu->dfu_state = DFU_STATE_dfuIDLE;
f_dfu->dfu_state = DFU_STATE_dfuMANIFEST;
handle_getstatus(req);
f_dfu->blk_seq_num = 0;
value = RET_STAT_LEN;
req->complete = dnload_request_flush;
break;
case USB_REQ_DFU_GETSTATE:
handle_getstate(req);
@ -463,6 +472,33 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu,
return value;
}
static int state_dfu_manifest(struct f_dfu *f_dfu,
const struct usb_ctrlrequest *ctrl,
struct usb_gadget *gadget,
struct usb_request *req)
{
int value = 0;
switch (ctrl->bRequest) {
case USB_REQ_DFU_GETSTATUS:
/* We're MainfestationTolerant */
f_dfu->dfu_state = DFU_STATE_dfuIDLE;
handle_getstatus(req);
f_dfu->blk_seq_num = 0;
value = RET_STAT_LEN;
puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n");
break;
case USB_REQ_DFU_GETSTATE:
handle_getstate(req);
break;
default:
f_dfu->dfu_state = DFU_STATE_dfuERROR;
value = RET_STALL;
break;
}
return value;
}
static int state_dfu_upload_idle(struct f_dfu *f_dfu,
const struct usb_ctrlrequest *ctrl,
struct usb_gadget *gadget,
@ -539,7 +575,7 @@ static dfu_state_fn dfu_state[] = {
state_dfu_dnbusy, /* DFU_STATE_dfuDNBUSY */
state_dfu_dnload_idle, /* DFU_STATE_dfuDNLOAD_IDLE */
state_dfu_manifest_sync, /* DFU_STATE_dfuMANIFEST_SYNC */
NULL, /* DFU_STATE_dfuMANIFEST */
state_dfu_manifest, /* DFU_STATE_dfuMANIFEST */
NULL, /* DFU_STATE_dfuMANIFEST_WAIT_RST */
state_dfu_upload_idle, /* DFU_STATE_dfuUPLOAD_IDLE */
state_dfu_error /* DFU_STATE_dfuERROR */

2
dts/Makefile
View File

@ -44,4 +44,4 @@ dtbs: $(obj)/dt.dtb
clean-files := dt.dtb.S
# Let clean descend into dts directories
subdir- += ../arch/*/dts
subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts

7
include/common.h
View File

@ -822,8 +822,7 @@ void udelay (unsigned long);
void mdelay(unsigned long);
/* lib/uuid.c */
void uuid_str_to_bin(const char *uuid, unsigned char *out);
int uuid_str_valid(const char *uuid);
#include <uuid.h>
/* lib/vsprintf.c */
#include <vsprintf.h>
@ -835,9 +834,7 @@ char * strmhz(char *buf, unsigned long hz);
#include <u-boot/crc.h>
/* lib/rand.c */
#if defined(CONFIG_RANDOM_MACADDR) || \
defined(CONFIG_BOOTP_RANDOM_DELAY) || \
defined(CONFIG_CMD_LINK_LOCAL)
#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND)
#define RAND_MAX -1U
void srand(unsigned int seed);
unsigned int rand(void);

16
include/config_fallbacks.h
View File

@ -55,6 +55,22 @@
#define HAVE_BLOCK_DEVICE
#endif
#if (defined(CONFIG_PARTITION_UUIDS) || \
defined(CONFIG_EFI_PARTITION) || \
defined(CONFIG_RANDOM_UUID) || \
defined(CONFIG_CMD_UUID) || \
defined(CONFIG_BOOTP_PXE)) && \
!defined(CONFIG_LIB_UUID)
#define CONFIG_LIB_UUID
#endif
#if (defined(CONFIG_RANDOM_UUID) || \
defined(CONFIG_CMD_UUID)) && \
(!defined(CONFIG_LIB_RAND) && \
!defined(CONFIG_LIB_HW_RAND))
#define CONFIG_LIB_RAND
#endif
#ifndef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> "
#endif

1
include/configs/MERGERBOX.h
View File

@ -312,6 +312,7 @@
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_RANDOM_DELAY
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_LIB_RAND
/*
* Command line configuration.

1
include/configs/MVBC_P.h
View File

@ -104,6 +104,7 @@
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_RANDOM_DELAY
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_LIB_RAND
/*
* Autoboot

1
include/configs/MVBLM7.h
View File

@ -227,6 +227,7 @@
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_RANDOM_DELAY
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_LIB_RAND
/* USB */
#define CONFIG_SYS_USB_HOST

1
include/configs/MVSMR.h
View File

@ -92,6 +92,7 @@
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_VENDOREX
#define CONFIG_LIB_RAND
/*
* Autoboot

1
include/configs/a3m071.h
View File

@ -58,6 +58,7 @@
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_NET_RETRY_COUNT 3
#define CONFIG_CMD_LINK_LOCAL
#define CONFIG_LIB_RAND
#define CONFIG_NETCONSOLE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_CMD_PING

3
include/configs/am335x_evm.h
View File

@ -208,9 +208,6 @@
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_AM33XX
/* CPSW support */
#define CONFIG_SPL_ETH_SUPPORT
/* USB gadget RNDIS */
#define CONFIG_SPL_MUSB_NEW_SUPPORT

1
include/configs/bfin_adi_common.h
View File

@ -17,6 +17,7 @@
# define CONFIG_BOOTP_DNS
# define CONFIG_BOOTP_NTPSERVER
# define CONFIG_BOOTP_RANDOM_DELAY
# define CONFIG_LIB_RAND
# define CONFIG_KEEP_SERVERADDR
# define CONFIG_CMD_DNS
# define CONFIG_CMD_PING

1
include/configs/lsxl.h
View File

@ -37,6 +37,7 @@
#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_RANDOM_MACADDR
#define CONFIG_LIB_RAND
#define CONFIG_KIRKWOOD_GPIO
#define CONFIG_OF_LIBFDT

1
include/configs/sacsng.h
View File

@ -457,6 +457,7 @@
#endif /* CONFIG_BOOT_ROOT_NFS */
#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
#define CONFIG_LIB_RAND
/*
* BOOTP options

2
include/configs/sandbox.h
View File

@ -169,4 +169,6 @@
#define CONFIG_TPM_TIS_SANDBOX
#define CONFIG_CMD_LZMADEC
#endif

1
include/configs/siemens-am33x-common.h
View File

@ -265,6 +265,7 @@
#define CONFIG_DFU_NAND
#define CONFIG_CMD_DFU
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#endif /* CONFIG_SPL_BUILD */

7
include/configs/trats.h
View File

@ -187,6 +187,9 @@
#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
/* GPT */
#define CONFIG_RANDOM_UUID
/* I2C */
#include <asm/arch/gpio.h>
@ -219,6 +222,10 @@
#define CONFIG_POWER_BATTERY
#define CONFIG_POWER_BATTERY_TRATS
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_LIB_HW_RAND
/* Common misc for Samsung */
#define CONFIG_MISC_COMMON

7
include/configs/trats2.h
View File

@ -166,6 +166,9 @@
"setenv spl_addr_tmp;\0" \
"fdtaddr=40800000\0" \
/* GPT */
#define CONFIG_RANDOM_UUID
/* I2C */
#include <asm/arch/gpio.h>
@ -201,6 +204,10 @@ int get_soft_i2c_sda_pin(void);
#define CONFIG_POWER_FG_MAX77693
#define CONFIG_POWER_BATTERY_TRATS2
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_LIB_HW_RAND
/* Common misc for Samsung */
#define CONFIG_MISC_COMMON

4
include/dfu.h
View File

@ -80,6 +80,9 @@ static inline unsigned int get_mmc_blk_size(int dev)
#ifndef DFU_DEFAULT_POLL_TIMEOUT
#define DFU_DEFAULT_POLL_TIMEOUT 0
#endif
#ifndef DFU_MANIFEST_POLL_TIMEOUT
#define DFU_MANIFEST_POLL_TIMEOUT DFU_DEFAULT_POLL_TIMEOUT
#endif
struct dfu_entity {
char name[DFU_NAME_SIZE];
@ -138,6 +141,7 @@ unsigned long dfu_get_buf_size(void);
int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
/* Device specific */
#ifdef CONFIG_DFU_MMC
extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s);

2
include/dwmmc.h
View File

@ -143,6 +143,8 @@ struct dwmci_host {
void (*clksel)(struct dwmci_host *host);
void (*board_init)(struct dwmci_host *host);
unsigned int (*get_mmc_clk)(struct dwmci_host *host);
struct mmc_config cfg;
};
struct dwmci_idmac {

4
include/fsl_esdhc.h
View File

@ -13,6 +13,9 @@
#include <asm/errno.h>
#include <asm/byteorder.h>
/* needed for the mmc_cfg definition */
#include <mmc.h>
/* FSL eSDHC-specific constants */
#define SYSCTL 0x0002e02c
#define SYSCTL_INITA 0x08000000
@ -155,6 +158,7 @@ struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
struct mmc_config cfg;
};
/* Select the correct accessors depending on endianess */

53
include/mmc.h
View File

@ -150,6 +150,7 @@
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
#define EXT_CSD_BOOT_BUS_WIDTH 177
@ -250,20 +251,40 @@ struct mmc_data {
uint blocksize;
};
struct mmc {
struct list_head link;
char name[32];
void *priv;
/* forward decl. */
struct mmc;
struct mmc_ops {
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
int (*getcd)(struct mmc *mmc);
int (*getwp)(struct mmc *mmc);
};
struct mmc_config {
const char *name;
const struct mmc_ops *ops;
uint host_caps;
uint voltages;
uint version;
uint has_init;
uint f_min;
uint f_max;
uint b_max;
unsigned char part_type;
};
/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
struct mmc {
struct list_head link;
const struct mmc_config *cfg; /* provided configuration */
uint version;
void *priv;
uint has_init;
int high_capacity;
uint bus_width;
uint clock;
uint card_caps;
uint host_caps;
uint ocr;
uint dsr;
uint dsr_imp;
@ -283,13 +304,6 @@ struct mmc {
u64 capacity_rpmb;
u64 capacity_gp[4];
block_dev_desc_t block_dev;
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
int (*getcd)(struct mmc *mmc);
int (*getwp)(struct mmc *mmc);
uint b_max;
char op_cond_pending; /* 1 if we are waiting on an op_cond command */
char init_in_progress; /* 1 if we have done mmc_start_init() */
char preinit; /* start init as early as possible */
@ -297,6 +311,8 @@ struct mmc {
};
int mmc_register(struct mmc *mmc);
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
void mmc_destroy(struct mmc *mmc);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
@ -317,6 +333,8 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
/**
* Start device initialization and return immediately; it does not block on
@ -345,7 +363,7 @@ void mmc_set_preinit(struct mmc *mmc, int preinit);
#ifdef CONFIG_GENERIC_MMC
#ifdef CONFIG_MMC_SPI
#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
#else
#define mmc_host_is_spi(mmc) 0
#endif
@ -356,4 +374,9 @@ int mmc_legacy_init(int verbose);
int board_mmc_init(bd_t *bis);
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
#endif
#endif /* _MMC_H_ */

2
include/sdhci.h
View File

@ -252,6 +252,8 @@ struct sdhci_host {
void (*set_control_reg)(struct sdhci_host *host);
void (*set_clock)(int dev_index, unsigned int div);
uint voltages;
struct mmc_config cfg;
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS

41
include/uuid.h Normal file
View File

@ -0,0 +1,41 @@
/*
* Copyright (C) 2014 Samsung Electronics
* Przemyslaw Marczak <p.marczak@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __UUID_H__
#define __UUID_H__
/* This is structure is in big-endian */
struct uuid {
unsigned int time_low;
unsigned short time_mid;
unsigned short time_hi_and_version;
unsigned char clock_seq_hi_and_reserved;
unsigned char clock_seq_low;
unsigned char node[6];
} __packed;
enum {
UUID_STR_FORMAT_STD,
UUID_STR_FORMAT_GUID
};
#define UUID_STR_LEN 36
#define UUID_BIN_LEN sizeof(struct uuid)
#define UUID_VERSION_MASK 0xf000
#define UUID_VERSION_SHIFT 12
#define UUID_VERSION 0x4
#define UUID_VARIANT_MASK 0xc0
#define UUID_VARIANT_SHIFT 7
#define UUID_VARIANT 0x1
int uuid_str_valid(const char *uuid);
int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format);
void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format);
void gen_rand_uuid(unsigned char *uuid_bin);
void gen_rand_uuid_str(char *uuid_str, int str_format);
#endif

6
lib/Makefile
View File

@ -60,10 +60,8 @@ obj-$(CONFIG_REGEX) += slre.o
obj-y += string.o
obj-y += time.o
obj-$(CONFIG_TRACE) += trace.o
obj-$(CONFIG_BOOTP_PXE) += uuid.o
obj-$(CONFIG_LIB_UUID) += uuid.o
obj-y += vsprintf.o
obj-$(CONFIG_RANDOM_MACADDR) += rand.o
obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o
obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o
obj-$(CONFIG_LIB_RAND) += rand.o
subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2

15334
lib/tizen/tizen_logo_16bpp.h
View File

File diff suppressed because it is too large Load Diff

1351
lib/tizen/tizen_logo_16bpp_gzip.h
View File

File diff suppressed because it is too large Load Diff

226
lib/uuid.c
View File

@ -4,21 +4,58 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/ctype.h>
#include "common.h"
#include <errno.h>
#include <common.h>
#include <asm/io.h>
#include <part_efi.h>
#include <malloc.h>
/*
* This is what a UUID string looks like.
* UUID - Universally Unique IDentifier - 128 bits unique number.
* There are 5 versions and one variant of UUID defined by RFC4122
* specification. A UUID contains a set of fields. The set varies
* depending on the version of the UUID, as shown below:
* - time, MAC address(v1),
* - user ID(v2),
* - MD5 of name or URL(v3),
* - random data(v4),
* - SHA-1 of name or URL(v5),
*
* x is a hexadecimal character. fields are separated by '-'s. When converting
* to a binary UUID, le means the field should be converted to little endian,
* and be means it should be converted to big endian.
* Layout of UUID:
* timestamp - 60-bit: time_low, time_mid, time_hi_and_version
* version - 4 bit (bit 4 through 7 of the time_hi_and_version)
* clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
* variant: - bit 6 and 7 of clock_seq_hi_and_reserved
* node - 48 bit
*
* source: https://www.ietf.org/rfc/rfc4122.txt
*
* UUID binary format (16 bytes):
*
* 4B-2B-2B-2B-6B (big endian - network byte order)
*
* UUID string is 36 length of characters (36 bytes):
*
* 0 9 14 19 24
* xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
* be be be be be
*
* where x is a hexadecimal character. Fields are separated by '-'s.
* When converting to a binary UUID, le means the field should be converted
* to little endian and be means it should be converted to big endian.
*
* UUID is also used as GUID (Globally Unique Identifier) with the same binary
* format but it differs in string format like below.
*
* GUID:
* 0 9 14 19 24
* xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
* le le le be be
*
* GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id.
*/
int uuid_str_valid(const char *uuid)
{
int i, valid;
@ -37,33 +74,182 @@ int uuid_str_valid(const char *uuid)
}
}
if (i != 36 || !valid)
if (i != UUID_STR_LEN || !valid)
return 0;
return 1;
}
void uuid_str_to_bin(const char *uuid, unsigned char *out)
/*
* uuid_str_to_bin() - convert string UUID or GUID to big endian binary data.
*
* @param uuid_str - pointer to UUID or GUID string [37B]
* @param uuid_bin - pointer to allocated array for big endian output [16B]
* @str_format - UUID string format: 0 - UUID; 1 - GUID
*/
int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format)
{
uint16_t tmp16;
uint32_t tmp32;
uint64_t tmp64;
if (!uuid || !out)
return;
if (!uuid_str_valid(uuid_str))
return -EINVAL;
tmp32 = cpu_to_le32(simple_strtoul(uuid, NULL, 16));
memcpy(out, &tmp32, 4);
if (str_format == UUID_STR_FORMAT_STD) {
tmp32 = cpu_to_be32(simple_strtoul(uuid_str, NULL, 16));
memcpy(uuid_bin, &tmp32, 4);
tmp16 = cpu_to_le16(simple_strtoul(uuid + 9, NULL, 16));
memcpy(out + 4, &tmp16, 2);
tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 9, NULL, 16));
memcpy(uuid_bin + 4, &tmp16, 2);
tmp16 = cpu_to_le16(simple_strtoul(uuid + 14, NULL, 16));
memcpy(out + 6, &tmp16, 2);
tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 14, NULL, 16));
memcpy(uuid_bin + 6, &tmp16, 2);
} else {
tmp32 = cpu_to_le32(simple_strtoul(uuid_str, NULL, 16));
memcpy(uuid_bin, &tmp32, 4);
tmp16 = cpu_to_be16(simple_strtoul(uuid + 19, NULL, 16));
memcpy(out + 8, &tmp16, 2);
tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 9, NULL, 16));
memcpy(uuid_bin + 4, &tmp16, 2);
tmp64 = cpu_to_be64(simple_strtoull(uuid + 24, NULL, 16));
memcpy(out + 10, (char *)&tmp64 + 2, 6);
tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 14, NULL, 16));
memcpy(uuid_bin + 6, &tmp16, 2);
}
tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 19, NULL, 16));
memcpy(uuid_bin + 8, &tmp16, 2);
tmp64 = cpu_to_be64(simple_strtoull(uuid_str + 24, NULL, 16));
memcpy(uuid_bin + 10, (char *)&tmp64 + 2, 6);
return 0;
}
/*
* uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
*
* @param uuid_bin - pointer to binary data of UUID (big endian) [16B]
* @param uuid_str - pointer to allocated array for output string [37B]
* @str_format - UUID string format: 0 - UUID; 1 - GUID
*/
void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format)
{
const u8 uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13, 14, 15};
const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8,
9, 10, 11, 12, 13, 14, 15};
const u8 *char_order;
int i;
/*
* UUID and GUID bin data - always in big endian:
* 4B-2B-2B-2B-6B
* be be be be be
*/
if (str_format == UUID_STR_FORMAT_STD)
char_order = uuid_char_order;
else
char_order = guid_char_order;
for (i = 0; i < 16; i++) {
sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]);
uuid_str += 2;
switch (i) {
case 3:
case 5:
case 7:
case 9:
*uuid_str++ = '-';
break;
}
}
}
/*
* gen_rand_uuid() - this function generates a random binary UUID version 4.
* In this version all fields beside 4 bits of version and
* 2 bits of variant are randomly generated.
*
* @param uuid_bin - pointer to allocated array [16B]. Output is in big endian.
*/
#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID)
void gen_rand_uuid(unsigned char *uuid_bin)
{
struct uuid uuid;
unsigned int *ptr = (unsigned int *)&uuid;
int i;
/* Set all fields randomly */
for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++)
*(ptr + i) = cpu_to_be32(rand());
clrsetbits_be16(&uuid.time_hi_and_version,
UUID_VERSION_MASK,
UUID_VERSION << UUID_VERSION_SHIFT);
clrsetbits_8(&uuid.clock_seq_hi_and_reserved,
UUID_VARIANT_MASK,
UUID_VARIANT << UUID_VARIANT_SHIFT);
memcpy(uuid_bin, &uuid, sizeof(struct uuid));
}
/*
* gen_rand_uuid_str() - this function generates UUID v4 (random) in two string
* formats UUID or GUID.
*
* @param uuid_str - pointer to allocated array [37B].
* @param - uuid output type: UUID - 0, GUID - 1
*/
void gen_rand_uuid_str(char *uuid_str, int str_format)
{
unsigned char uuid_bin[UUID_BIN_LEN];
/* Generate UUID (big endian) */
gen_rand_uuid(uuid_bin);
/* Convert UUID bin to UUID or GUID formated STRING */
uuid_bin_to_str(uuid_bin, uuid_str, str_format);
}
#ifdef CONFIG_CMD_UUID
int do_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char uuid[UUID_STR_LEN + 1];
int str_format;
if (!strcmp(argv[0], "uuid"))
str_format = UUID_STR_FORMAT_STD;
else
str_format = UUID_STR_FORMAT_GUID;
if (argc > 2)
return CMD_RET_USAGE;
gen_rand_uuid_str(uuid, str_format);
if (argc == 1)
printf("%s\n", uuid);
else
setenv(argv[1], uuid);
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(uuid, CONFIG_SYS_MAXARGS, 1, do_uuid,
"UUID - generate random Universally Unique Identifier",
"[<varname>]\n"
"Argument:\n"
"varname: for set result in a environment variable\n"
"e.g. uuid uuid_env"
);
U_BOOT_CMD(guid, CONFIG_SYS_MAXARGS, 1, do_uuid,
"GUID - generate Globally Unique Identifier based on random UUID",
"[<varname>]\n"
"Argument:\n"
"varname: for set result in a environment variable\n"
"e.g. guid guid_env"
);
#endif /* CONFIG_CMD_UUID */
#endif /* CONFIG_RANDOM_UUID || CONFIG_CMD_UUID */

2
net/bootp.c
View File

@ -439,7 +439,7 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID,
*e++ = 17;
*e++ = 0; /* type 0 - UUID */
uuid_str_to_bin(uuid, e);
uuid_str_to_bin(uuid, e, UUID_STR_FORMAT_STD);
e += 16;
} else {
printf("Invalid pxeuuid: %s\n", uuid);

3
scripts/Makefile.clean
View File

@ -39,7 +39,8 @@ subdir-ymn := $(addprefix $(obj)/,$(subdir-ymn))
# Temporal work-around for U-Boot
subdir-ymn := $(foreach f, $(subdir-ymn), $(if $(wildcard $f/Makefile),$f))
subdir-ymn := $(foreach f, $(subdir-ymn), \
$(if $(wildcard $(srctree)/$f/Makefile),$f))
# build a list of files to remove, usually relative to the current
# directory

2
spl/Makefile
View File

@ -171,7 +171,7 @@ LDPPFLAGS += \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
quiet_cmd_mkimage = UIMAGE $@
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)

21
tools/patman/README
View File

@ -217,8 +217,10 @@ Series-changes: n
to update the log there and then, knowing that the script will
do the rest.
Cc: Their Name <email>
This copies a single patch to another email address.
Patch-cc: Their Name <email>
This copies a single patch to another email address. Note that the
Cc: used by git send-email is ignored by patman, but will be
interpreted by git send-email if you use it.
Series-process-log: sort, uniq
This tells patman to sort and/or uniq the change logs. It is
@ -246,8 +248,9 @@ Where Patches Are Sent
Once the patches are created, patman sends them using git send-email. The
whole series is sent to the recipients in Series-to: and Series-cc.
You can Cc individual patches to other people with the Cc: tag. Tags in the
subject are also picked up to Cc patches. For example, a commit like this:
You can Cc individual patches to other people with the Patch-cc: tag. Tags
in the subject are also picked up to Cc patches. For example, a commit like
this:
>>>>
commit 10212537b85ff9b6e09c82045127522c0f0db981
@ -258,16 +261,16 @@ Date: Mon Nov 7 23:18:44 2011 -0500
This should make sending out e-mails to the right people easier.
Cc: sandbox, mikef, ag
Cc: afleming
Patch-cc: sandbox, mikef, ag
Patch-cc: afleming
<<<<
will create a patch which is copied to x86, arm, sandbox, mikef, ag and
afleming.
If you have a cover letter it will get sent to the union of the CC lists of
all of the other patches. If you want to sent it to additional people you
can add a tag:
If you have a cover letter it will get sent to the union of the Patch-cc
lists of all of the other patches. If you want to sent it to additional
people you can add a tag:
Cover-letter-cc: <list of addresses>

4
tools/patman/patchstream.py
View File

@ -36,7 +36,7 @@ re_series_tag = re.compile('^Series-([a-z-]*): *(.*)')
re_commit_tag = re.compile('^Commit-([a-z-]*): *(.*)')
# Commit tags that we want to collect and keep
re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Cc): (.*)')
re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Patch-cc): (.*)')
# The start of a new commit in the git log
re_commit = re.compile('^commit ([0-9a-f]*)$')
@ -267,7 +267,7 @@ class PatchStream:
if (tag_match.group(1) == 'Tested-by' and
tag_match.group(2).find(os.getenv('USER') + '@') != -1):
self.warn.append("Ignoring %s" % line)
elif tag_match.group(1) == 'Cc':
elif tag_match.group(1) == 'Patch-cc':
self.commit.AddCc(tag_match.group(2).split(','))
else:
self.tags.append(line);