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https://github.com/brain-hackers/u-boot-brain
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ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS
These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
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66e399b68d
commit
51370d5618
@ -482,17 +482,17 @@ static void dump_spd_ddr_reg(void)
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int i, j, k, m;
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int i, j, k, m;
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u8 *p_8;
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u8 *p_8;
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u32 *p_32;
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u32 *p_32;
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struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
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struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
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generic_spd_eeprom_t
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generic_spd_eeprom_t
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spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
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spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
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for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
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fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
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fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
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puts("SPD data of all dimms (zero value is omitted)...\n");
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puts("SPD data of all dimms (zero value is omitted)...\n");
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puts("Byte (hex) ");
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puts("Byte (hex) ");
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k = 1;
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k = 1;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
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printf("Dimm%d ", k++);
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printf("Dimm%d ", k++);
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}
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}
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@ -500,7 +500,7 @@ static void dump_spd_ddr_reg(void)
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for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
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for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
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m = 0;
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m = 0;
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printf("%3d (0x%02x) ", k, k);
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printf("%3d (0x%02x) ", k, k);
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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p_8 = (u8 *) &spd[i][j];
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p_8 = (u8 *) &spd[i][j];
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if (p_8[k]) {
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if (p_8[k]) {
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@ -516,22 +516,22 @@ static void dump_spd_ddr_reg(void)
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puts("\r");
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puts("\r");
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}
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}
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
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switch (i) {
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switch (i) {
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case 0:
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case 0:
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ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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break;
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break;
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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case 1:
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case 1:
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ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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break;
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break;
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#endif
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#endif
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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case 2:
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case 2:
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ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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break;
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break;
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#endif
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#endif
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
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case 3:
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case 3:
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ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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break;
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break;
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@ -545,13 +545,13 @@ static void dump_spd_ddr_reg(void)
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printf("DDR registers dump for all controllers "
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printf("DDR registers dump for all controllers "
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"(zero value is omitted)...\n");
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"(zero value is omitted)...\n");
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puts("Offset (hex) ");
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puts("Offset (hex) ");
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
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for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
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printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
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printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
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puts("\n");
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puts("\n");
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for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
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for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
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m = 0;
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m = 0;
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printf("%6d (0x%04x)", k * 4, k * 4);
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printf("%6d (0x%04x)", k * 4, k * 4);
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
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p_32 = (u32 *) ddr[i];
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p_32 = (u32 *) ddr[i];
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if (p_32[k]) {
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if (p_32[k]) {
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printf(" 0x%08x", p_32[k]);
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printf(" 0x%08x", p_32[k]);
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@ -378,10 +378,10 @@ void fsl_erratum_a007212_workaround(void)
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u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
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u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
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u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
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u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
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u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
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u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
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#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
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u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
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u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
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u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
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#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
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u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
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u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
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u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
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u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
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#endif
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#endif
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@ -409,25 +409,25 @@ void fsl_erratum_a007212_workaround(void)
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ddr_pll_ratio >>= 1;
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ddr_pll_ratio >>= 1;
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setbits_be32(plldadcr1, 0x02000001);
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setbits_be32(plldadcr1, 0x02000001);
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#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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setbits_be32(plldadcr2, 0x02000001);
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setbits_be32(plldadcr2, 0x02000001);
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#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
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setbits_be32(plldadcr3, 0x02000001);
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setbits_be32(plldadcr3, 0x02000001);
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#endif
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#endif
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#endif
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#endif
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setbits_be32(dpdovrcr4, 0xe0000000);
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setbits_be32(dpdovrcr4, 0xe0000000);
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out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
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out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
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#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
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out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
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#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
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out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
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out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
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#endif
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#endif
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#endif
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#endif
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udelay(100);
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udelay(100);
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clrbits_be32(plldadcr1, 0x02000001);
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clrbits_be32(plldadcr1, 0x02000001);
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#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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clrbits_be32(plldadcr2, 0x02000001);
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clrbits_be32(plldadcr2, 0x02000001);
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#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
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clrbits_be32(plldadcr3, 0x02000001);
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clrbits_be32(plldadcr3, 0x02000001);
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#endif
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#endif
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#endif
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#endif
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@ -213,7 +213,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
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debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
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debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
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rank_density, ctlr_density);
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rank_density, ctlr_density);
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for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
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for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
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switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
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switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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case FSL_DDR_PAGE_INTERLEAVING:
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case FSL_DDR_PAGE_INTERLEAVING:
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@ -237,7 +237,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
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* Simple linear assignment if memory
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* Simple linear assignment if memory
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* controllers are not interleaved.
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* controllers are not interleaved.
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*/
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*/
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for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
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for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
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total_ctlr_mem = 0;
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total_ctlr_mem = 0;
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pinfo->common_timing_params[i].base_address =
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pinfo->common_timing_params[i].base_address =
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current_mem_base;
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current_mem_base;
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@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
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* Fixed sdram init -- doesn't use serial presence detect.
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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*/
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extern fixed_ddr_parm_t fixed_ddr_parm_0[];
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extern fixed_ddr_parm_t fixed_ddr_parm_0[];
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
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extern fixed_ddr_parm_t fixed_ddr_parm_1[];
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extern fixed_ddr_parm_t fixed_ddr_parm_1[];
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#endif
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#endif
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@ -56,7 +56,7 @@ phys_size_t fixed_sdram(void)
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ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
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ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
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memcpy(&ddr_cfg_regs,
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memcpy(&ddr_cfg_regs,
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fixed_ddr_parm_1[i].ddr_settings,
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fixed_ddr_parm_1[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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sizeof(ddr_cfg_regs));
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@ -76,7 +76,7 @@ phys_size_t fixed_sdram(void)
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return 0;
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return 0;
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}
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}
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} else {
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} else {
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
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/* We require both controllers have identical DIMMs */
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/* We require both controllers have identical DIMMs */
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lawbar1_target_id = LAW_TRGT_IF_DDR_1;
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lawbar1_target_id = LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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@ -23,7 +23,7 @@ config SYS_FSL_DDR_LE
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menu "Freescale DDR controllers"
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menu "Freescale DDR controllers"
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depends on SYS_FSL_DDR
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depends on SYS_FSL_DDR
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config NUM_DDR_CONTROLLERS
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config SYS_NUM_DDR_CTLRS
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int "Maximum DDR controllers"
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int "Maximum DDR controllers"
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default 3 if ARCH_LS2080A || \
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default 3 if ARCH_LS2080A || \
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ARCH_T4240
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ARCH_T4240
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@ -40,17 +40,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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case 0:
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case 0:
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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break;
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break;
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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case 1:
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case 1:
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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break;
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break;
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#endif
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#endif
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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case 2:
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case 2:
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ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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break;
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break;
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#endif
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#endif
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
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case 3:
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case 3:
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ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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break;
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break;
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@ -2318,17 +2318,17 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
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case 0:
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case 0:
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ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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break;
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break;
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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case 1:
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case 1:
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ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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break;
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break;
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#endif
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#endif
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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case 2:
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case 2:
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ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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break;
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break;
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#endif
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#endif
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
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case 3:
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case 3:
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ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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break;
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break;
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@ -68,17 +68,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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case 0:
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case 0:
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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break;
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break;
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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case 1:
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case 1:
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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break;
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break;
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#endif
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#endif
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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case 2:
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case 2:
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ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
|
||||||
case 3:
|
case 3:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
||||||
break;
|
break;
|
||||||
|
@ -763,7 +763,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
|
|||||||
debug("fsl_ddr_regs_edit: ctrl_num = %u, "
|
debug("fsl_ddr_regs_edit: ctrl_num = %u, "
|
||||||
"regname = %s, value = %s\n",
|
"regname = %s, value = %s\n",
|
||||||
ctrl_num, regname, value_str);
|
ctrl_num, regname, value_str);
|
||||||
if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
|
if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
|
ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
|
||||||
@ -1685,7 +1685,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
|
|||||||
|
|
||||||
/* STEP 1: DIMM SPD data */
|
/* STEP 1: DIMM SPD data */
|
||||||
if (do_mask & STEP_GET_SPD) {
|
if (do_mask & STEP_GET_SPD) {
|
||||||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
|
||||||
if (!(ctrl_mask & (1 << i)))
|
if (!(ctrl_mask & (1 << i)))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
@ -1706,7 +1706,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
|
|||||||
|
|
||||||
/* STEP 2: DIMM Parameters */
|
/* STEP 2: DIMM Parameters */
|
||||||
if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
|
if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
|
||||||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
|
||||||
if (!(ctrl_mask & (1 << i)))
|
if (!(ctrl_mask & (1 << i)))
|
||||||
continue;
|
continue;
|
||||||
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
|
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
|
||||||
@ -1725,7 +1725,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
|
|||||||
|
|
||||||
/* STEP 3: Common Parameters */
|
/* STEP 3: Common Parameters */
|
||||||
if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
|
if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
|
||||||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
|
||||||
if (!(ctrl_mask & (1 << i)))
|
if (!(ctrl_mask & (1 << i)))
|
||||||
continue;
|
continue;
|
||||||
printf("\"lowest common\" DIMM parameters: "
|
printf("\"lowest common\" DIMM parameters: "
|
||||||
@ -1739,7 +1739,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
|
|||||||
|
|
||||||
/* STEP 4: User Configuration Options */
|
/* STEP 4: User Configuration Options */
|
||||||
if (do_mask & STEP_GATHER_OPTS) {
|
if (do_mask & STEP_GATHER_OPTS) {
|
||||||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
|
||||||
if (!(ctrl_mask & (1 << i)))
|
if (!(ctrl_mask & (1 << i)))
|
||||||
continue;
|
continue;
|
||||||
printf("User Config Options: Controller=%u\n", i);
|
printf("User Config Options: Controller=%u\n", i);
|
||||||
@ -1751,7 +1751,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
|
|||||||
|
|
||||||
/* STEP 5: Address assignment */
|
/* STEP 5: Address assignment */
|
||||||
if (do_mask & STEP_ASSIGN_ADDRESSES) {
|
if (do_mask & STEP_ASSIGN_ADDRESSES) {
|
||||||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
|
||||||
if (!(ctrl_mask & (1 << i)))
|
if (!(ctrl_mask & (1 << i)))
|
||||||
continue;
|
continue;
|
||||||
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
|
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
|
||||||
@ -1766,7 +1766,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
|
|||||||
|
|
||||||
/* STEP 6: computed controller register values */
|
/* STEP 6: computed controller register values */
|
||||||
if (do_mask & STEP_COMPUTE_REGS) {
|
if (do_mask & STEP_COMPUTE_REGS) {
|
||||||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
|
||||||
if (!(ctrl_mask & (1 << i)))
|
if (!(ctrl_mask & (1 << i)))
|
||||||
continue;
|
continue;
|
||||||
printf("Computed Register Values: Controller=%u\n", i);
|
printf("Computed Register Values: Controller=%u\n", i);
|
||||||
|
@ -40,35 +40,35 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size);
|
|||||||
#if defined(SPD_EEPROM_ADDRESS) || \
|
#if defined(SPD_EEPROM_ADDRESS) || \
|
||||||
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
|
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
|
||||||
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
|
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
|
||||||
#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
|
#if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
|
||||||
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
||||||
[0][0] = SPD_EEPROM_ADDRESS,
|
[0][0] = SPD_EEPROM_ADDRESS,
|
||||||
};
|
};
|
||||||
#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
|
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
|
||||||
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
||||||
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
||||||
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
|
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
|
||||||
};
|
};
|
||||||
#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
|
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
|
||||||
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
||||||
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
||||||
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
|
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
|
||||||
};
|
};
|
||||||
#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
|
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
|
||||||
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
||||||
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
||||||
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
|
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
|
||||||
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
|
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
|
||||||
[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
|
[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
|
||||||
};
|
};
|
||||||
#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
|
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
|
||||||
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
||||||
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
||||||
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
|
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
|
||||||
[2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
|
[2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
|
||||||
};
|
};
|
||||||
#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
|
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
|
||||||
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
|
||||||
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
|
||||||
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
|
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
|
||||||
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
|
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
|
||||||
@ -146,7 +146,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
|
|||||||
unsigned int i;
|
unsigned int i;
|
||||||
unsigned int i2c_address = 0;
|
unsigned int i2c_address = 0;
|
||||||
|
|
||||||
if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
|
if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
|
||||||
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
|
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -430,7 +430,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
|
|||||||
assert_reset = pinfo->board_need_mem_reset();
|
assert_reset = pinfo->board_need_mem_reset();
|
||||||
|
|
||||||
/* data bus width capacity adjust shift amount */
|
/* data bus width capacity adjust shift amount */
|
||||||
unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
|
unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
|
||||||
|
|
||||||
for (i = first_ctrl; i <= last_ctrl; i++)
|
for (i = first_ctrl; i <= last_ctrl; i++)
|
||||||
dbw_capacity_adjust[i] = 0;
|
dbw_capacity_adjust[i] = 0;
|
||||||
@ -720,7 +720,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
|
|||||||
&pinfo->common_timing_params[i],
|
&pinfo->common_timing_params[i],
|
||||||
law_memctl, i);
|
law_memctl, i);
|
||||||
}
|
}
|
||||||
#if CONFIG_NUM_DDR_CONTROLLERS > 3
|
#if CONFIG_SYS_NUM_DDR_CTLRS > 3
|
||||||
else if (i == 2) {
|
else if (i == 2) {
|
||||||
law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
|
law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
|
||||||
fsl_ddr_set_lawbar(
|
fsl_ddr_set_lawbar(
|
||||||
|
@ -44,17 +44,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
|||||||
case 0:
|
case 0:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||||
break;
|
break;
|
||||||
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
|
||||||
case 1:
|
case 1:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
|
||||||
case 2:
|
case 2:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
|
||||||
case 3:
|
case 3:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
||||||
break;
|
break;
|
||||||
|
@ -1077,7 +1077,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
|
|||||||
* if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
|
* if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
|
||||||
* with 256 Byte is enabled.
|
* with 256 Byte is enabled.
|
||||||
*/
|
*/
|
||||||
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
|
||||||
if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
|
if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
|
||||||
#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
|
#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
|
||||||
;
|
;
|
||||||
@ -1107,39 +1107,39 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
|
|||||||
"ctlr_intlv",
|
"ctlr_intlv",
|
||||||
"cacheline", buf)) {
|
"cacheline", buf)) {
|
||||||
popts->memctl_interleaving_mode =
|
popts->memctl_interleaving_mode =
|
||||||
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
|
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
|
||||||
0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
|
0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
|
||||||
popts->memctl_interleaving =
|
popts->memctl_interleaving =
|
||||||
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
|
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
|
||||||
0 : 1;
|
0 : 1;
|
||||||
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
||||||
"ctlr_intlv",
|
"ctlr_intlv",
|
||||||
"page", buf)) {
|
"page", buf)) {
|
||||||
popts->memctl_interleaving_mode =
|
popts->memctl_interleaving_mode =
|
||||||
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
|
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
|
||||||
0 : FSL_DDR_PAGE_INTERLEAVING;
|
0 : FSL_DDR_PAGE_INTERLEAVING;
|
||||||
popts->memctl_interleaving =
|
popts->memctl_interleaving =
|
||||||
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
|
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
|
||||||
0 : 1;
|
0 : 1;
|
||||||
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
||||||
"ctlr_intlv",
|
"ctlr_intlv",
|
||||||
"bank", buf)) {
|
"bank", buf)) {
|
||||||
popts->memctl_interleaving_mode =
|
popts->memctl_interleaving_mode =
|
||||||
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
|
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
|
||||||
0 : FSL_DDR_BANK_INTERLEAVING;
|
0 : FSL_DDR_BANK_INTERLEAVING;
|
||||||
popts->memctl_interleaving =
|
popts->memctl_interleaving =
|
||||||
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
|
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
|
||||||
0 : 1;
|
0 : 1;
|
||||||
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
||||||
"ctlr_intlv",
|
"ctlr_intlv",
|
||||||
"superbank", buf)) {
|
"superbank", buf)) {
|
||||||
popts->memctl_interleaving_mode =
|
popts->memctl_interleaving_mode =
|
||||||
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
|
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
|
||||||
0 : FSL_DDR_SUPERBANK_INTERLEAVING;
|
0 : FSL_DDR_SUPERBANK_INTERLEAVING;
|
||||||
popts->memctl_interleaving =
|
popts->memctl_interleaving =
|
||||||
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
|
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
|
||||||
0 : 1;
|
0 : 1;
|
||||||
#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
|
#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
|
||||||
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
||||||
"ctlr_intlv",
|
"ctlr_intlv",
|
||||||
"3way_1KB", buf)) {
|
"3way_1KB", buf)) {
|
||||||
@ -1155,7 +1155,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
|
|||||||
"3way_8KB", buf)) {
|
"3way_8KB", buf)) {
|
||||||
popts->memctl_interleaving_mode =
|
popts->memctl_interleaving_mode =
|
||||||
FSL_DDR_3WAY_8KB_INTERLEAVING;
|
FSL_DDR_3WAY_8KB_INTERLEAVING;
|
||||||
#elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
|
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
|
||||||
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
|
||||||
"ctlr_intlv",
|
"ctlr_intlv",
|
||||||
"4way_1KB", buf)) {
|
"4way_1KB", buf)) {
|
||||||
@ -1178,7 +1178,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
|
|||||||
}
|
}
|
||||||
#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
|
#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
|
||||||
done:
|
done:
|
||||||
#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
|
#endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
|
||||||
if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
|
if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
|
||||||
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
|
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
|
||||||
/* test null first. if CONFIG_HWCONFIG is not defined,
|
/* test null first. if CONFIG_HWCONFIG is not defined,
|
||||||
@ -1356,10 +1356,10 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
|
|||||||
case FSL_DDR_PAGE_INTERLEAVING:
|
case FSL_DDR_PAGE_INTERLEAVING:
|
||||||
case FSL_DDR_BANK_INTERLEAVING:
|
case FSL_DDR_BANK_INTERLEAVING:
|
||||||
case FSL_DDR_SUPERBANK_INTERLEAVING:
|
case FSL_DDR_SUPERBANK_INTERLEAVING:
|
||||||
#if (3 == CONFIG_NUM_DDR_CONTROLLERS)
|
#if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
|
||||||
k = 2;
|
k = 2;
|
||||||
#else
|
#else
|
||||||
k = CONFIG_NUM_DDR_CONTROLLERS;
|
k = CONFIG_SYS_NUM_DDR_CTLRS;
|
||||||
#endif
|
#endif
|
||||||
break;
|
break;
|
||||||
case FSL_DDR_3WAY_1KB_INTERLEAVING:
|
case FSL_DDR_3WAY_1KB_INTERLEAVING:
|
||||||
@ -1369,7 +1369,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
|
|||||||
case FSL_DDR_4WAY_4KB_INTERLEAVING:
|
case FSL_DDR_4WAY_4KB_INTERLEAVING:
|
||||||
case FSL_DDR_4WAY_8KB_INTERLEAVING:
|
case FSL_DDR_4WAY_8KB_INTERLEAVING:
|
||||||
default:
|
default:
|
||||||
k = CONFIG_NUM_DDR_CONTROLLERS;
|
k = CONFIG_SYS_NUM_DDR_CTLRS;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
debug("%d of %d controllers are interleaving.\n", j, k);
|
debug("%d of %d controllers are interleaving.\n", j, k);
|
||||||
|
@ -30,17 +30,17 @@ u32 fsl_ddr_get_version(unsigned int ctrl_num)
|
|||||||
case 0:
|
case 0:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||||
break;
|
break;
|
||||||
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
|
||||||
case 1:
|
case 1:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
|
||||||
case 2:
|
case 2:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
|
||||||
case 3:
|
case 3:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
||||||
break;
|
break;
|
||||||
@ -174,23 +174,23 @@ void print_ddr_info(unsigned int start_ctrl)
|
|||||||
struct ccsr_ddr __iomem *ddr =
|
struct ccsr_ddr __iomem *ddr =
|
||||||
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
|
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
|
||||||
|
|
||||||
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
|
#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
|
||||||
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
|
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
|
||||||
#endif
|
#endif
|
||||||
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
|
||||||
uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
|
uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
|
||||||
#endif
|
#endif
|
||||||
uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
|
uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
|
||||||
int cas_lat;
|
int cas_lat;
|
||||||
|
|
||||||
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
|
#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
|
||||||
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
|
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
|
||||||
(start_ctrl == 1)) {
|
(start_ctrl == 1)) {
|
||||||
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
|
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
|
||||||
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
|
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
|
#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
|
||||||
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
|
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
|
||||||
(start_ctrl == 2)) {
|
(start_ctrl == 2)) {
|
||||||
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
|
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
|
||||||
@ -246,7 +246,7 @@ void print_ddr_info(unsigned int start_ctrl)
|
|||||||
else
|
else
|
||||||
puts(", ECC off)");
|
puts(", ECC off)");
|
||||||
|
|
||||||
#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
|
#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
|
||||||
#ifdef CONFIG_E6500
|
#ifdef CONFIG_E6500
|
||||||
if (*mcintl3r & 0x80000000) {
|
if (*mcintl3r & 0x80000000) {
|
||||||
puts("\n");
|
puts("\n");
|
||||||
@ -268,7 +268,7 @@ void print_ddr_info(unsigned int start_ctrl)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
|
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
|
||||||
if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
|
if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
|
||||||
puts("\n");
|
puts("\n");
|
||||||
puts(" DDR Controller Interleaving Mode: ");
|
puts(" DDR Controller Interleaving Mode: ");
|
||||||
@ -337,8 +337,8 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
|
|||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
u32 ddrc_debug20;
|
u32 ddrc_debug20;
|
||||||
u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
|
u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
|
||||||
u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
|
u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
|
||||||
struct ccsr_ddr __iomem *ddr;
|
struct ccsr_ddr __iomem *ddr;
|
||||||
|
|
||||||
for (i = first_ctrl; i <= last_ctrl; i++) {
|
for (i = first_ctrl; i <= last_ctrl; i++) {
|
||||||
@ -346,17 +346,17 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
|
|||||||
case 0:
|
case 0:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||||
break;
|
break;
|
||||||
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
|
||||||
case 1:
|
case 1:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
|
||||||
case 2:
|
case 2:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
|
||||||
case 3:
|
case 3:
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
||||||
break;
|
break;
|
||||||
|
@ -62,7 +62,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||||
|
@ -40,7 +40,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||||
|
@ -22,7 +22,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
@ -22,7 +22,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
@ -53,7 +53,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||||
|
@ -164,7 +164,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||||
|
@ -32,7 +32,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
@ -26,7 +26,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
@ -72,7 +72,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||||
|
@ -58,7 +58,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||||
|
@ -48,7 +48,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
||||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||||
#define CONFIG_PCIE2 /* PCIE controller 2 */
|
#define CONFIG_PCIE2 /* PCIE controller 2 */
|
||||||
|
@ -34,7 +34,7 @@
|
|||||||
#define CONFIG_MP /* support multiple processors */
|
#define CONFIG_MP /* support multiple processors */
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
||||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||||
#define CONFIG_PCIE3 /* PCIE controller 3 */
|
#define CONFIG_PCIE3 /* PCIE controller 3 */
|
||||||
|
@ -25,7 +25,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||||
#define CONFIG_PCIE2 /* PCIE controller 2 */
|
#define CONFIG_PCIE2 /* PCIE controller 2 */
|
||||||
|
@ -15,7 +15,7 @@
|
|||||||
|
|
||||||
#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
|
#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
|
||||||
/* All controllers are for main memory */
|
/* All controllers are for main memory */
|
||||||
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_FSL_DDR_LE
|
#ifdef CONFIG_SYS_FSL_DDR_LE
|
||||||
@ -54,7 +54,6 @@ compute_dimm_parameters(const unsigned int ctrl_num,
|
|||||||
*
|
*
|
||||||
* All data structures have to be on the stack
|
* All data structures have to be on the stack
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
|
|
||||||
#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
|
#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
|
@ -6628,7 +6628,6 @@ CONFIG_SYS_NS87308_UART2
|
|||||||
CONFIG_SYS_NS87308_UART2_BASE
|
CONFIG_SYS_NS87308_UART2_BASE
|
||||||
CONFIG_SYS_NUM_ADDR_MAP
|
CONFIG_SYS_NUM_ADDR_MAP
|
||||||
CONFIG_SYS_NUM_CPC
|
CONFIG_SYS_NUM_CPC
|
||||||
CONFIG_SYS_NUM_DDR_CTLRS
|
|
||||||
CONFIG_SYS_NUM_FM1_10GEC
|
CONFIG_SYS_NUM_FM1_10GEC
|
||||||
CONFIG_SYS_NUM_FM1_DTSEC
|
CONFIG_SYS_NUM_FM1_DTSEC
|
||||||
CONFIG_SYS_NUM_FM2_10GEC
|
CONFIG_SYS_NUM_FM2_10GEC
|
||||||
|
Loading…
Reference in New Issue
Block a user