mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-23 05:00:24 +09:00
arm: dts: imx8mn: sync dts from Linux Kernel
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
6489dac3ab
commit
50d0953127
@ -6,216 +6,151 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mn.dtsi"
|
||||
#include "imx8mn-evk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP i.MX8MNano DDR4 EVK board";
|
||||
compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
at803x,led-act-blind-workaround;
|
||||
at803x,eee-disabled;
|
||||
at803x,vddio-1p8v;
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&ddrc {
|
||||
operating-points-v2 = <&ddrc_opp_table>;
|
||||
|
||||
ddrc_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-25M {
|
||||
opp-hz = /bits/ 64 <25000000>;
|
||||
};
|
||||
|
||||
opp-100M {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
|
||||
opp-600M {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
&i2c1 {
|
||||
pmic@4b {
|
||||
compatible = "rohm,bd71847";
|
||||
reg = <0x4b>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
rohm,reset-snvs-powered;
|
||||
|
||||
&uart2 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
regulators {
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "buck1";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "buck2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
buck3_reg: BUCK3 {
|
||||
// BUCK5 in datasheet
|
||||
regulator-name = "buck3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
buck4_reg: BUCK4 {
|
||||
// BUCK6 in datasheet
|
||||
regulator-name = "buck4";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
// BUCK7 in datasheet
|
||||
regulator-name = "buck5";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
// BUCK8 in datasheet
|
||||
regulator-name = "buck6";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "ldo6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
360
arch/arm/dts/imx8mn-evk.dtsi
Normal file
360
arch/arm/dts/imx8mn-evk.dtsi
Normal file
@ -0,0 +1,360 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
#include "imx8mn.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_led>;
|
||||
|
||||
status {
|
||||
label = "yellow:status";
|
||||
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
ir-receiver {
|
||||
compatible = "gpio-ir-receiver";
|
||||
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ir>;
|
||||
linux,autosuspend-period = <125>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
ptn5110: tcpc@50 {
|
||||
compatible = "nxp,ptn5110";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_typec1>;
|
||||
reg = <0x50>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
typec1_dr_sw: endpoint {
|
||||
remote-endpoint = <&usb1_drd_sw>;
|
||||
};
|
||||
};
|
||||
|
||||
typec1_con: connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
try-power-role = "sink";
|
||||
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
|
||||
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
|
||||
PDO_VAR(5000, 20000, 3000)>;
|
||||
op-sink-microwatt = <15000000>;
|
||||
self-powered;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
pca6416: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
dr_mode = "otg";
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
usb-role-switch;
|
||||
samsung,picophy-pre-emp-curr-control = <3>;
|
||||
samsung,picophy-dc-vol-level-adjust = <7>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usb1_drd_sw: endpoint {
|
||||
remote-endpoint = <&typec1_dr_sw>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_led: gpioledgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ir: irgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicirqgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_typec1: typec1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
|
||||
>;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@ -7,11 +7,11 @@
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
#include "imx8mn-pinfunc.h"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,imx8mn";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@ -43,6 +43,19 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
cpu_pd_wait: cpu-pd-wait {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010033>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <700>;
|
||||
min-residency-us = <2700>;
|
||||
};
|
||||
};
|
||||
|
||||
A53_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
@ -51,6 +64,11 @@
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
nvmem-cells = <&cpu_speed_grade>;
|
||||
nvmem-cell-names = "speed_grade";
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
@ -61,6 +79,9 @@
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
@ -71,6 +92,9 @@
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
@ -81,6 +105,9 @@
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
@ -88,9 +115,33 @@
|
||||
};
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0x80000000>;
|
||||
a53_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <850000>;
|
||||
opp-supported-hw = <0xb00>, <0x7>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-microvolt = <950000>;
|
||||
opp-supported-hw = <0x300>, <0x7>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
opp-supported-hw = <0x100>, <0x3>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
osc_32k: clock-osc-32k {
|
||||
@ -135,17 +186,56 @@
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tmu>;
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit0: trip1 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <8000000>;
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
@ -163,6 +253,149 @@
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
spba: bus@30000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000000 0x100000>;
|
||||
ranges;
|
||||
|
||||
sai2: sai@30020000 {
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x30020000 0x10000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
|
||||
<&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_SAI2_ROOT>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
||||
dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai3: sai@30030000 {
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x30030000 0x10000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
|
||||
<&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_SAI3_ROOT>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
||||
dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai5: sai@30050000 {
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x30050000 0x10000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
|
||||
<&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_SAI5_ROOT>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
||||
dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,shared-interrupt;
|
||||
fsl,dataline = <0 0xf 0xf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai6: sai@30060000 {
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x30060000 0x10000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
|
||||
<&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_SAI6_ROOT>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
||||
dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
micfil: audio-controller@30080000 {
|
||||
compatible = "fsl,imx8mm-micfil";
|
||||
reg = <0x30080000 0x10000>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PDM_IPG>,
|
||||
<&clk IMX8MN_CLK_PDM_ROOT>,
|
||||
<&clk IMX8MN_AUDIO_PLL1_OUT>,
|
||||
<&clk IMX8MN_AUDIO_PLL2_OUT>,
|
||||
<&clk IMX8MN_CLK_EXT3>;
|
||||
clock-names = "ipg_clk", "ipg_clk_app",
|
||||
"pll8k", "pll11k", "clkext3";
|
||||
dmas = <&sdma2 24 25 0x80000000>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spdif1: spdif@30090000 {
|
||||
compatible = "fsl,imx35-spdif";
|
||||
reg = <0x30090000 0x10000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
|
||||
<&clk IMX8MN_CLK_24M>, /* rxtx0 */
|
||||
<&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
|
||||
<&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
|
||||
<&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
|
||||
<&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
|
||||
<&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
|
||||
<&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
|
||||
<&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
|
||||
<&clk IMX8MN_CLK_DUMMY>; /* spba */
|
||||
clock-names = "core", "rxtx0",
|
||||
"rxtx1", "rxtx2",
|
||||
"rxtx3", "rxtx4",
|
||||
"rxtx5", "rxtx6",
|
||||
"rxtx7", "spba";
|
||||
dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai7: sai@300b0000 {
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x300b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
|
||||
<&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_SAI7_ROOT>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
||||
dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
easrc: easrc@300c0000 {
|
||||
compatible = "fsl,imx8mn-easrc";
|
||||
reg = <0x300c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
|
||||
clock-names = "mem";
|
||||
dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
|
||||
<&sdma2 18 23 0> , <&sdma2 19 23 0>,
|
||||
<&sdma2 20 23 0> , <&sdma2 21 23 0>,
|
||||
<&sdma2 22 23 0> , <&sdma2 23 23 0>;
|
||||
dma-names = "ctx0_rx", "ctx0_tx",
|
||||
"ctx1_rx", "ctx1_tx",
|
||||
"ctx2_rx", "ctx2_tx",
|
||||
"ctx3_rx", "ctx3_tx";
|
||||
firmware-name = "imx/easrc/easrc-imx8mn.bin";
|
||||
fsl,asrc-rate = <8000>;
|
||||
fsl,asrc-format = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
@ -173,6 +406,7 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 10 30>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
@ -185,6 +419,7 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 40 21>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
@ -197,6 +432,7 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 61 26>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
@ -209,6 +445,7 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 21 108 11>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
@ -221,6 +458,14 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 119 30>;
|
||||
};
|
||||
|
||||
tmu: tmu@30260000 {
|
||||
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
|
||||
reg = <0x30260000 0x10000>;
|
||||
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
@ -248,7 +493,7 @@
|
||||
};
|
||||
|
||||
sdma3: dma-controller@302b0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x302b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
|
||||
@ -259,7 +504,7 @@
|
||||
};
|
||||
|
||||
sdma2: dma-controller@302c0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
|
||||
@ -279,15 +524,21 @@
|
||||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
|
||||
ocotp: efuse@30350000 {
|
||||
compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpu_speed_grade: speed-grade@10 {
|
||||
reg = <0x10 4>;
|
||||
};
|
||||
};
|
||||
|
||||
anatop: anatop@30360000 {
|
||||
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
|
||||
"syscon", "simple-bus";
|
||||
"syscon";
|
||||
reg = <0x30360000 0x10000>;
|
||||
};
|
||||
|
||||
@ -301,6 +552,7 @@
|
||||
offset = <0x34>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-rtc";
|
||||
};
|
||||
|
||||
@ -308,6 +560,8 @@
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-pwrkey";
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
@ -322,10 +576,24 @@
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
|
||||
<&clk IMX8MN_CLK_A53_CORE>,
|
||||
<&clk IMX8MN_CLK_NOC>,
|
||||
<&clk IMX8MN_CLK_AUDIO_AHB>,
|
||||
<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
|
||||
<&clk IMX8MN_SYS_PLL3>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
|
||||
<&clk IMX8MN_ARM_PLL_OUT>,
|
||||
<&clk IMX8MN_SYS_PLL3_OUT>,
|
||||
<&clk IMX8MN_SYS_PLL1_800M>;
|
||||
assigned-clock-rates = <0>, <0>, <0>,
|
||||
<400000000>,
|
||||
<400000000>,
|
||||
<600000000>;
|
||||
};
|
||||
|
||||
src: reset-controller@30390000 {
|
||||
compatible = "fsl,imx8mn-src", "syscon";
|
||||
compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
|
||||
reg = <0x30390000 0x10000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
@ -382,6 +650,14 @@
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
system_counter: timer@306a0000 {
|
||||
compatible = "nxp,sysctr-timer";
|
||||
reg = <0x306a0000 0x20000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&osc_24m>;
|
||||
clock-names = "per";
|
||||
};
|
||||
};
|
||||
|
||||
aips3: bus@30800000 {
|
||||
@ -467,6 +743,36 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto: crypto@30900000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30900000 0x40000>;
|
||||
ranges = <0 0x30900000 0x40000>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_AHB>,
|
||||
<&clk IMX8MN_CLK_IPG_ROOT>;
|
||||
clock-names = "aclk", "ipg";
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
@ -519,16 +825,22 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mu: mailbox@30aa0000 {
|
||||
compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
|
||||
reg = <0x30aa0000 0x10000>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_MU_ROOT>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
@ -539,7 +851,7 @@
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
@ -553,12 +865,10 @@
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
@ -566,11 +876,11 @@
|
||||
};
|
||||
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
|
||||
<&clk IMX8MN_CLK_SDMA1_ROOT>;
|
||||
<&clk IMX8MN_CLK_AHB>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
@ -581,7 +891,8 @@
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MN_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MN_CLK_ENET_TIMER>,
|
||||
@ -617,10 +928,8 @@
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
|
||||
clock-names = "usb1_ctrl_root_clk";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
|
||||
<&clk IMX8MN_CLK_USB_CORE_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
|
||||
<&clk IMX8MN_SYS_PLL1_100M>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
|
||||
fsl,usbphy = <&usbphynop1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
status = "disabled";
|
||||
@ -631,28 +940,6 @@
|
||||
#index-cells = <1>;
|
||||
reg = <0x32e40200 0x200>;
|
||||
};
|
||||
|
||||
usbotg2: usb@32e50000 {
|
||||
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
|
||||
reg = <0x32e50000 0x200>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
|
||||
clock-names = "usb1_ctrl_root_clk";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
|
||||
<&clk IMX8MN_CLK_USB_CORE_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
|
||||
<&clk IMX8MN_SYS_PLL1_100M>;
|
||||
fsl,usbphy = <&usbphynop2>;
|
||||
fsl,usbmisc = <&usbmisc2 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc2: usbmisc@32e50200 {
|
||||
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
|
||||
#index-cells = <1>;
|
||||
reg = <0x32e50200 0x200>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
dma_apbh: dma-controller@33000000 {
|
||||
@ -692,6 +979,22 @@
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ddrc: memory-controller@3d400000 {
|
||||
compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
|
||||
reg = <0x3d400000 0x400000>;
|
||||
clock-names = "core", "pll", "alt", "apb";
|
||||
clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
|
||||
<&clk IMX8MN_DRAM_PLL>,
|
||||
<&clk IMX8MN_CLK_DRAM_ALT>,
|
||||
<&clk IMX8MN_CLK_DRAM_APB>;
|
||||
};
|
||||
|
||||
ddr-pmu@3d800000 {
|
||||
compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
|
||||
reg = <0x3d800000 0x400000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
@ -701,12 +1004,4 @@
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbphynop2: usbphynop2 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
||||
|
||||
@ -122,8 +122,8 @@
|
||||
#define IMX8MN_CLK_I2C1 105
|
||||
#define IMX8MN_CLK_I2C2 106
|
||||
#define IMX8MN_CLK_I2C3 107
|
||||
#define IMX8MN_CLK_I2C4 118
|
||||
#define IMX8MN_CLK_UART1 119
|
||||
#define IMX8MN_CLK_I2C4 108
|
||||
#define IMX8MN_CLK_UART1 109
|
||||
#define IMX8MN_CLK_UART2 110
|
||||
#define IMX8MN_CLK_UART3 111
|
||||
#define IMX8MN_CLK_UART4 112
|
||||
@ -209,7 +209,31 @@
|
||||
#define IMX8MN_CLK_ARM 191
|
||||
#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
|
||||
#define IMX8MN_CLK_GPU_CORE_ROOT 193
|
||||
#define IMX8MN_CLK_GIC 194
|
||||
|
||||
#define IMX8MN_CLK_END 194
|
||||
#define IMX8MN_SYS_PLL1_40M_CG 195
|
||||
#define IMX8MN_SYS_PLL1_80M_CG 196
|
||||
#define IMX8MN_SYS_PLL1_100M_CG 197
|
||||
#define IMX8MN_SYS_PLL1_133M_CG 198
|
||||
#define IMX8MN_SYS_PLL1_160M_CG 199
|
||||
#define IMX8MN_SYS_PLL1_200M_CG 200
|
||||
#define IMX8MN_SYS_PLL1_266M_CG 201
|
||||
#define IMX8MN_SYS_PLL1_400M_CG 202
|
||||
#define IMX8MN_SYS_PLL2_50M_CG 203
|
||||
#define IMX8MN_SYS_PLL2_100M_CG 204
|
||||
#define IMX8MN_SYS_PLL2_125M_CG 205
|
||||
#define IMX8MN_SYS_PLL2_166M_CG 206
|
||||
#define IMX8MN_SYS_PLL2_200M_CG 207
|
||||
#define IMX8MN_SYS_PLL2_250M_CG 208
|
||||
#define IMX8MN_SYS_PLL2_333M_CG 209
|
||||
#define IMX8MN_SYS_PLL2_500M_CG 210
|
||||
|
||||
#define IMX8MN_CLK_SNVS_ROOT 211
|
||||
#define IMX8MN_CLK_GPU_CORE 212
|
||||
#define IMX8MN_CLK_GPU_SHADER 213
|
||||
|
||||
#define IMX8MN_CLK_A53_CORE 214
|
||||
|
||||
#define IMX8MN_CLK_END 215
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user