mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
This is a framebuffer driver for ATI video card, can work for PCI9200,
X300, X700, X800 ATI video cards. Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
This commit is contained in:
Jason Jin
Wolfgang Denk
parent
5728be389e
commit
5072188aca
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@ -52,7 +52,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
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ks8695eth.o \
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pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
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rpx_pcmcia.o \
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fsl_i2c.o fsl_pci_init.o
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fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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212
drivers/ati_ids.h
Normal file
212
drivers/ati_ids.h
Normal file
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@ -0,0 +1,212 @@
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/*
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* ATI PCI IDs from XFree86, kept here to make sync'ing with
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* XFree much simpler. Currently, this list is only used by
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* radeonfb
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*/
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#define PCI_CHIP_RV380_3150 0x3150
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#define PCI_CHIP_RV380_3151 0x3151
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#define PCI_CHIP_RV380_3152 0x3152
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#define PCI_CHIP_RV380_3153 0x3153
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#define PCI_CHIP_RV380_3154 0x3154
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#define PCI_CHIP_RV380_3156 0x3156
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#define PCI_CHIP_RV380_3E50 0x3E50
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#define PCI_CHIP_RV380_3E51 0x3E51
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#define PCI_CHIP_RV380_3E52 0x3E52
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#define PCI_CHIP_RV380_3E53 0x3E53
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#define PCI_CHIP_RV380_3E54 0x3E54
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#define PCI_CHIP_RV380_3E56 0x3E56
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#define PCI_CHIP_RS100_4136 0x4136
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#define PCI_CHIP_RS200_4137 0x4137
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#define PCI_CHIP_R300_AD 0x4144
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#define PCI_CHIP_R300_AE 0x4145
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#define PCI_CHIP_R300_AF 0x4146
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#define PCI_CHIP_R300_AG 0x4147
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#define PCI_CHIP_R350_AH 0x4148
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#define PCI_CHIP_R350_AI 0x4149
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#define PCI_CHIP_R350_AJ 0x414A
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#define PCI_CHIP_R350_AK 0x414B
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#define PCI_CHIP_RV350_AP 0x4150
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#define PCI_CHIP_RV350_AQ 0x4151
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#define PCI_CHIP_RV360_AR 0x4152
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#define PCI_CHIP_RV350_AS 0x4153
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#define PCI_CHIP_RV350_AT 0x4154
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#define PCI_CHIP_RV350_AV 0x4156
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#define PCI_CHIP_MACH32 0x4158
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#define PCI_CHIP_RS250_4237 0x4237
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#define PCI_CHIP_R200_BB 0x4242
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#define PCI_CHIP_R200_BC 0x4243
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#define PCI_CHIP_RS100_4336 0x4336
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#define PCI_CHIP_RS200_4337 0x4337
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#define PCI_CHIP_MACH64CT 0x4354
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#define PCI_CHIP_MACH64CX 0x4358
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#define PCI_CHIP_RS250_4437 0x4437
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#define PCI_CHIP_MACH64ET 0x4554
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#define PCI_CHIP_MACH64GB 0x4742
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#define PCI_CHIP_MACH64GD 0x4744
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#define PCI_CHIP_MACH64GI 0x4749
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#define PCI_CHIP_MACH64GL 0x474C
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#define PCI_CHIP_MACH64GM 0x474D
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#define PCI_CHIP_MACH64GN 0x474E
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#define PCI_CHIP_MACH64GO 0x474F
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#define PCI_CHIP_MACH64GP 0x4750
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#define PCI_CHIP_MACH64GQ 0x4751
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#define PCI_CHIP_MACH64GR 0x4752
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#define PCI_CHIP_MACH64GS 0x4753
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#define PCI_CHIP_MACH64GT 0x4754
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#define PCI_CHIP_MACH64GU 0x4755
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#define PCI_CHIP_MACH64GV 0x4756
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#define PCI_CHIP_MACH64GW 0x4757
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#define PCI_CHIP_MACH64GX 0x4758
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#define PCI_CHIP_MACH64GY 0x4759
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#define PCI_CHIP_MACH64GZ 0x475A
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#define PCI_CHIP_RV250_Id 0x4964
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#define PCI_CHIP_RV250_Ie 0x4965
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#define PCI_CHIP_RV250_If 0x4966
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#define PCI_CHIP_RV250_Ig 0x4967
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#define PCI_CHIP_R420_JH 0x4A48
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#define PCI_CHIP_R420_JI 0x4A49
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#define PCI_CHIP_R420_JJ 0x4A4A
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#define PCI_CHIP_R420_JK 0x4A4B
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#define PCI_CHIP_R420_JL 0x4A4C
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#define PCI_CHIP_R420_JM 0x4A4D
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#define PCI_CHIP_R420_JN 0x4A4E
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#define PCI_CHIP_R420_JP 0x4A50
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#define PCI_CHIP_MACH64LB 0x4C42
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#define PCI_CHIP_MACH64LD 0x4C44
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#define PCI_CHIP_RAGE128LE 0x4C45
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#define PCI_CHIP_RAGE128LF 0x4C46
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#define PCI_CHIP_MACH64LG 0x4C47
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#define PCI_CHIP_MACH64LI 0x4C49
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#define PCI_CHIP_MACH64LM 0x4C4D
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#define PCI_CHIP_MACH64LN 0x4C4E
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#define PCI_CHIP_MACH64LP 0x4C50
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#define PCI_CHIP_MACH64LQ 0x4C51
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#define PCI_CHIP_MACH64LR 0x4C52
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#define PCI_CHIP_MACH64LS 0x4C53
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#define PCI_CHIP_MACH64LT 0x4C54
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#define PCI_CHIP_RADEON_LW 0x4C57
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#define PCI_CHIP_RADEON_LX 0x4C58
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#define PCI_CHIP_RADEON_LY 0x4C59
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#define PCI_CHIP_RADEON_LZ 0x4C5A
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#define PCI_CHIP_RV250_Ld 0x4C64
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#define PCI_CHIP_RV250_Le 0x4C65
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#define PCI_CHIP_RV250_Lf 0x4C66
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#define PCI_CHIP_RV250_Lg 0x4C67
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#define PCI_CHIP_RV250_Ln 0x4C6E
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#define PCI_CHIP_RAGE128MF 0x4D46
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#define PCI_CHIP_RAGE128ML 0x4D4C
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#define PCI_CHIP_R300_ND 0x4E44
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#define PCI_CHIP_R300_NE 0x4E45
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#define PCI_CHIP_R300_NF 0x4E46
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#define PCI_CHIP_R300_NG 0x4E47
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#define PCI_CHIP_R350_NH 0x4E48
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#define PCI_CHIP_R350_NI 0x4E49
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#define PCI_CHIP_R360_NJ 0x4E4A
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#define PCI_CHIP_R350_NK 0x4E4B
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#define PCI_CHIP_RV350_NP 0x4E50
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#define PCI_CHIP_RV350_NQ 0x4E51
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#define PCI_CHIP_RV350_NR 0x4E52
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#define PCI_CHIP_RV350_NS 0x4E53
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#define PCI_CHIP_RV350_NT 0x4E54
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#define PCI_CHIP_RV350_NV 0x4E56
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#define PCI_CHIP_RAGE128PA 0x5041
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#define PCI_CHIP_RAGE128PB 0x5042
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#define PCI_CHIP_RAGE128PC 0x5043
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#define PCI_CHIP_RAGE128PD 0x5044
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#define PCI_CHIP_RAGE128PE 0x5045
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#define PCI_CHIP_RAGE128PF 0x5046
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#define PCI_CHIP_RAGE128PG 0x5047
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#define PCI_CHIP_RAGE128PH 0x5048
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#define PCI_CHIP_RAGE128PI 0x5049
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#define PCI_CHIP_RAGE128PJ 0x504A
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#define PCI_CHIP_RAGE128PK 0x504B
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#define PCI_CHIP_RAGE128PL 0x504C
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#define PCI_CHIP_RAGE128PM 0x504D
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#define PCI_CHIP_RAGE128PN 0x504E
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#define PCI_CHIP_RAGE128PO 0x504F
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#define PCI_CHIP_RAGE128PP 0x5050
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#define PCI_CHIP_RAGE128PQ 0x5051
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#define PCI_CHIP_RAGE128PR 0x5052
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#define PCI_CHIP_RAGE128PS 0x5053
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#define PCI_CHIP_RAGE128PT 0x5054
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#define PCI_CHIP_RAGE128PU 0x5055
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#define PCI_CHIP_RAGE128PV 0x5056
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#define PCI_CHIP_RAGE128PW 0x5057
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#define PCI_CHIP_RAGE128PX 0x5058
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#define PCI_CHIP_RADEON_QD 0x5144
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#define PCI_CHIP_RADEON_QE 0x5145
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#define PCI_CHIP_RADEON_QF 0x5146
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#define PCI_CHIP_RADEON_QG 0x5147
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#define PCI_CHIP_R200_QH 0x5148
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#define PCI_CHIP_R200_QI 0x5149
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#define PCI_CHIP_R200_QJ 0x514A
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#define PCI_CHIP_R200_QK 0x514B
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#define PCI_CHIP_R200_QL 0x514C
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#define PCI_CHIP_R200_QM 0x514D
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#define PCI_CHIP_R200_QN 0x514E
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#define PCI_CHIP_R200_QO 0x514F
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#define PCI_CHIP_RV200_QW 0x5157
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#define PCI_CHIP_RV200_QX 0x5158
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#define PCI_CHIP_RV100_QY 0x5159
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#define PCI_CHIP_RV100_QZ 0x515A
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#define PCI_CHIP_RN50 0x515E
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#define PCI_CHIP_RAGE128RE 0x5245
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#define PCI_CHIP_RAGE128RF 0x5246
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#define PCI_CHIP_RAGE128RG 0x5247
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#define PCI_CHIP_RAGE128RK 0x524B
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#define PCI_CHIP_RAGE128RL 0x524C
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#define PCI_CHIP_RAGE128SE 0x5345
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#define PCI_CHIP_RAGE128SF 0x5346
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#define PCI_CHIP_RAGE128SG 0x5347
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#define PCI_CHIP_RAGE128SH 0x5348
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#define PCI_CHIP_RAGE128SK 0x534B
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#define PCI_CHIP_RAGE128SL 0x534C
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#define PCI_CHIP_RAGE128SM 0x534D
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#define PCI_CHIP_RAGE128SN 0x534E
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#define PCI_CHIP_RAGE128TF 0x5446
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#define PCI_CHIP_RAGE128TL 0x544C
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#define PCI_CHIP_RAGE128TR 0x5452
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#define PCI_CHIP_RAGE128TS 0x5453
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#define PCI_CHIP_RAGE128TT 0x5454
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#define PCI_CHIP_RAGE128TU 0x5455
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#define PCI_CHIP_RV370_5460 0x5460
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#define PCI_CHIP_RV370_5461 0x5461
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#define PCI_CHIP_RV370_5462 0x5462
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#define PCI_CHIP_RV370_5463 0x5463
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#define PCI_CHIP_RV370_5464 0x5464
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#define PCI_CHIP_RV370_5465 0x5465
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#define PCI_CHIP_RV370_5466 0x5466
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#define PCI_CHIP_RV370_5467 0x5467
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#define PCI_CHIP_R423_UH 0x5548
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#define PCI_CHIP_R423_UI 0x5549
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#define PCI_CHIP_R423_UJ 0x554A
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#define PCI_CHIP_R423_UK 0x554B
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#define PCI_CHIP_R423_UQ 0x5551
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#define PCI_CHIP_R423_UR 0x5552
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#define PCI_CHIP_R423_UT 0x5554
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#define PCI_CHIP_MACH64VT 0x5654
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#define PCI_CHIP_MACH64VU 0x5655
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#define PCI_CHIP_MACH64VV 0x5656
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#define PCI_CHIP_RS300_5834 0x5834
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#define PCI_CHIP_RS300_5835 0x5835
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#define PCI_CHIP_RS300_5836 0x5836
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#define PCI_CHIP_RS300_5837 0x5837
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#define PCI_CHIP_RV370_5B60 0x5B60
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#define PCI_CHIP_RV370_5B61 0x5B61
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#define PCI_CHIP_RV370_5B62 0x5B62
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#define PCI_CHIP_RV370_5B63 0x5B63
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#define PCI_CHIP_RV370_5B64 0x5B64
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#define PCI_CHIP_RV370_5B65 0x5B65
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#define PCI_CHIP_RV370_5B66 0x5B66
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#define PCI_CHIP_RV370_5B67 0x5B67
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#define PCI_CHIP_RV280_5960 0x5960
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#define PCI_CHIP_RV280_5961 0x5961
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#define PCI_CHIP_RV280_5962 0x5962
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#define PCI_CHIP_RV280_5964 0x5964
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#define PCI_CHIP_RV280_5C61 0x5C61
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#define PCI_CHIP_RV280_5C63 0x5C63
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#define PCI_CHIP_R423_5D57 0x5D57
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#define PCI_CHIP_RS350_7834 0x7834
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#define PCI_CHIP_RS350_7835 0x7835
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486
drivers/ati_radeon_fb.c
Normal file
486
drivers/ati_radeon_fb.c
Normal file
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@ -0,0 +1,486 @@
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/*
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* ATI Radeon Video card Framebuffer driver.
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* Zhang Wei <wei.zhang@freescale.com>
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* Jason Jin <jason.jin@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Some codes of this file is partly ported from Linux kernel
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* ATI video framebuffer driver.
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*
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* Now the driver is tested on below ATI chips:
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* 9200
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* X300
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* X700
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*
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*/
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#include <common.h>
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#ifdef CONFIG_ATI_RADEON_FB
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <video_fb.h>
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#include <radeon.h>
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#include "ati_ids.h"
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#include "ati_radeon_fb.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DPRINT(x...) printf(x)
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#else
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#define DPRINT(x...) do{}while(0)
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#endif
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#ifndef min_t
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#define min_t(type,x,y) \
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({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
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#endif
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#define MAX_MAPPED_VRAM (2048*2048*4)
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#define MIN_MAPPED_VRAM (1024*768*1)
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/*#define PCI_VENDOR_ID_ATI*/
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#define PCI_CHIP_RV280_5960 0x5960
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#define PCI_CHIP_RV280_5961 0x5961
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#define PCI_CHIP_RV280_5962 0x5962
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#define PCI_CHIP_RV280_5964 0x5964
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#define PCI_CHIP_RV370_5B60 0x5B60
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#define PCI_CHIP_RV380_5657 0x5657
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#define PCI_CHIP_R420_554d 0x554d
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static struct pci_device_id ati_radeon_pci_ids[] = {
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d},
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{0, 0}
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};
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static u16 ati_radeon_id_family_table[][2] = {
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{PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380},
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{PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380},
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{PCI_CHIP_R420_554d, CHIP_FAMILY_R420},
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{0, 0}
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};
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u16 get_radeon_id_family(u16 device)
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{
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int i;
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for (i=0; ati_radeon_id_family_table[0][i]; i+=2)
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if (ati_radeon_id_family_table[0][i] == device)
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return ati_radeon_id_family_table[0][i + 1];
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return 0;
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}
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struct radeonfb_info *rinfo;
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static void radeon_identify_vram(struct radeonfb_info *rinfo)
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{
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u32 tmp;
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/* framebuffer size */
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if ((rinfo->family == CHIP_FAMILY_RS100) ||
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(rinfo->family == CHIP_FAMILY_RS200) ||
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(rinfo->family == CHIP_FAMILY_RS300)) {
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u32 tom = INREG(NB_TOM);
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tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
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radeon_fifo_wait(6);
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OUTREG(MC_FB_LOCATION, tom);
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OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
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OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
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OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
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/* This is supposed to fix the crtc2 noise problem. */
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OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
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|
||||
if ((rinfo->family == CHIP_FAMILY_RS100) ||
|
||||
(rinfo->family == CHIP_FAMILY_RS200)) {
|
||||
/* This is to workaround the asic bug for RMX, some versions
|
||||
of BIOS dosen't have this register initialized correctly.
|
||||
*/
|
||||
OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
|
||||
~CRTC_H_CUTOFF_ACTIVE_EN);
|
||||
}
|
||||
} else {
|
||||
tmp = INREG(CONFIG_MEMSIZE);
|
||||
}
|
||||
|
||||
/* mem size is bits [28:0], mask off the rest */
|
||||
rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
|
||||
|
||||
/*
|
||||
* Hack to get around some busted production M6's
|
||||
* reporting no ram
|
||||
*/
|
||||
if (rinfo->video_ram == 0) {
|
||||
switch (rinfo->pdev.device) {
|
||||
case PCI_CHIP_RADEON_LY:
|
||||
case PCI_CHIP_RADEON_LZ:
|
||||
rinfo->video_ram = 8192 * 1024;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Now try to identify VRAM type
|
||||
*/
|
||||
if ((rinfo->family >= CHIP_FAMILY_R300) ||
|
||||
(INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
|
||||
rinfo->vram_ddr = 1;
|
||||
else
|
||||
rinfo->vram_ddr = 0;
|
||||
|
||||
tmp = INREG(MEM_CNTL);
|
||||
if (IS_R300_VARIANT(rinfo)) {
|
||||
tmp &= R300_MEM_NUM_CHANNELS_MASK;
|
||||
switch (tmp) {
|
||||
case 0: rinfo->vram_width = 64; break;
|
||||
case 1: rinfo->vram_width = 128; break;
|
||||
case 2: rinfo->vram_width = 256; break;
|
||||
default: rinfo->vram_width = 128; break;
|
||||
}
|
||||
} else if ((rinfo->family == CHIP_FAMILY_RV100) ||
|
||||
(rinfo->family == CHIP_FAMILY_RS100) ||
|
||||
(rinfo->family == CHIP_FAMILY_RS200)){
|
||||
if (tmp & RV100_MEM_HALF_MODE)
|
||||
rinfo->vram_width = 32;
|
||||
else
|
||||
rinfo->vram_width = 64;
|
||||
} else {
|
||||
if (tmp & MEM_NUM_CHANNELS_MASK)
|
||||
rinfo->vram_width = 128;
|
||||
else
|
||||
rinfo->vram_width = 64;
|
||||
}
|
||||
|
||||
/* This may not be correct, as some cards can have half of channel disabled
|
||||
* ToDo: identify these cases
|
||||
*/
|
||||
|
||||
DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n",
|
||||
rinfo->video_ram / 1024,
|
||||
rinfo->vram_ddr ? "DDR" : "SDRAM",
|
||||
rinfo->vram_width);
|
||||
|
||||
}
|
||||
|
||||
static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
|
||||
{
|
||||
int i;
|
||||
|
||||
radeon_fifo_wait(20);
|
||||
|
||||
#if 0
|
||||
/* Workaround from XFree */
|
||||
if (rinfo->is_mobility) {
|
||||
/* A temporal workaround for the occational blanking on certain laptop
|
||||
* panels. This appears to related to the PLL divider registers
|
||||
* (fail to lock?). It occurs even when all dividers are the same
|
||||
* with their old settings. In this case we really don't need to
|
||||
* fiddle with PLL registers. By doing this we can avoid the blanking
|
||||
* problem with some panels.
|
||||
*/
|
||||
if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
|
||||
(mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
|
||||
(PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
|
||||
/* We still have to force a switch to selected PPLL div thanks to
|
||||
* an XFree86 driver bug which will switch it away in some cases
|
||||
* even when using UseFDev */
|
||||
OUTREGP(CLOCK_CNTL_INDEX,
|
||||
mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
|
||||
~PPLL_DIV_SEL_MASK);
|
||||
radeon_pll_errata_after_index(rinfo);
|
||||
radeon_pll_errata_after_data(rinfo);
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return;
|
||||
|
||||
/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
|
||||
OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
|
||||
|
||||
/* Reset PPLL & enable atomic update */
|
||||
OUTPLLP(PPLL_CNTL,
|
||||
PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
|
||||
~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
|
||||
|
||||
/* Switch to selected PPLL divider */
|
||||
OUTREGP(CLOCK_CNTL_INDEX,
|
||||
mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
|
||||
~PPLL_DIV_SEL_MASK);
|
||||
|
||||
/* Set PPLL ref. div */
|
||||
if (rinfo->family == CHIP_FAMILY_R300 ||
|
||||
rinfo->family == CHIP_FAMILY_RS300 ||
|
||||
rinfo->family == CHIP_FAMILY_R350 ||
|
||||
rinfo->family == CHIP_FAMILY_RV350) {
|
||||
if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
|
||||
/* When restoring console mode, use saved PPLL_REF_DIV
|
||||
* setting.
|
||||
*/
|
||||
OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
|
||||
} else {
|
||||
/* R300 uses ref_div_acc field as real ref divider */
|
||||
OUTPLLP(PPLL_REF_DIV,
|
||||
(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
|
||||
~R300_PPLL_REF_DIV_ACC_MASK);
|
||||
}
|
||||
} else
|
||||
OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
|
||||
|
||||
/* Set PPLL divider 3 & post divider*/
|
||||
OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
|
||||
OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
|
||||
|
||||
/* Write update */
|
||||
while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
|
||||
;
|
||||
OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
|
||||
|
||||
/* Wait read update complete */
|
||||
/* FIXME: Certain revisions of R300 can't recover here. Not sure of
|
||||
the cause yet, but this workaround will mask the problem for now.
|
||||
Other chips usually will pass at the very first test, so the
|
||||
workaround shouldn't have any effect on them. */
|
||||
for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
|
||||
;
|
||||
|
||||
OUTPLL(HTOTAL_CNTL, 0);
|
||||
|
||||
/* Clear reset & atomic update */
|
||||
OUTPLLP(PPLL_CNTL, 0,
|
||||
~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
|
||||
|
||||
/* We may want some locking ... oh well */
|
||||
udelay(5000);
|
||||
|
||||
/* Switch back VCLK source to PPLL */
|
||||
OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
u16 reg;
|
||||
u32 val;
|
||||
} reg_val;
|
||||
|
||||
|
||||
/* these common regs are cleared before mode setting so they do not
|
||||
* interfere with anything
|
||||
*/
|
||||
static reg_val common_regs[] = {
|
||||
{ OVR_CLR, 0 },
|
||||
{ OVR_WID_LEFT_RIGHT, 0 },
|
||||
{ OVR_WID_TOP_BOTTOM, 0 },
|
||||
{ OV0_SCALE_CNTL, 0 },
|
||||
{ SUBPIC_CNTL, 0 },
|
||||
{ VIPH_CONTROL, 0 },
|
||||
{ I2C_CNTL_1, 0 },
|
||||
{ GEN_INT_CNTL, 0 },
|
||||
{ CAP0_TRIG_CNTL, 0 },
|
||||
{ CAP1_TRIG_CNTL, 0 },
|
||||
};
|
||||
|
||||
|
||||
void radeon_setmode(void)
|
||||
{
|
||||
int i;
|
||||
struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
|
||||
|
||||
mode->crtc_gen_cntl = 0x03000200;
|
||||
mode->crtc_ext_cntl = 0x00008048;
|
||||
mode->dac_cntl = 0xff002100;
|
||||
mode->crtc_h_total_disp = 0x4f0063;
|
||||
mode->crtc_h_sync_strt_wid = 0x8c02a2;
|
||||
mode->crtc_v_total_disp = 0x01df020c;
|
||||
mode->crtc_v_sync_strt_wid = 0x8201ea;
|
||||
mode->crtc_pitch = 0x00500050;
|
||||
|
||||
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
|
||||
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
|
||||
~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
|
||||
OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
|
||||
OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
|
||||
OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
|
||||
OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
|
||||
OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
|
||||
OUTREG(CRTC_OFFSET, 0);
|
||||
OUTREG(CRTC_OFFSET_CNTL, 0);
|
||||
OUTREG(CRTC_PITCH, mode->crtc_pitch);
|
||||
|
||||
mode->clk_cntl_index = 0x300;
|
||||
mode->ppll_ref_div = 0xc;
|
||||
mode->ppll_div_3 = 0x00030059;
|
||||
|
||||
radeon_write_pll_regs(rinfo, mode);
|
||||
}
|
||||
|
||||
int radeon_probe(struct radeonfb_info *rinfo)
|
||||
{
|
||||
pci_dev_t pdev;
|
||||
u16 did;
|
||||
|
||||
pdev = pci_find_devices(ati_radeon_pci_ids, 0);
|
||||
|
||||
if (pdev != -1) {
|
||||
pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
|
||||
printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n",
|
||||
PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff,
|
||||
(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
|
||||
|
||||
strcpy(rinfo->name, "ATI Radeon");
|
||||
rinfo->pdev.vendor = PCI_VENDOR_ID_ATI;
|
||||
rinfo->pdev.device = did;
|
||||
rinfo->family = get_radeon_id_family(rinfo->pdev.device);
|
||||
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
|
||||
&rinfo->fb_base_phys);
|
||||
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2,
|
||||
&rinfo->mmio_base_phys);
|
||||
rinfo->fb_base_phys &= 0xfffff000;
|
||||
rinfo->mmio_base_phys &= ~0x04;
|
||||
|
||||
rinfo->mmio_base = (void *)rinfo->mmio_base_phys;
|
||||
DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base);
|
||||
rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
|
||||
DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base);
|
||||
/* PostBIOS with x86 emulater */
|
||||
BootVideoCardBIOS(pdev, NULL, 0);
|
||||
|
||||
/*
|
||||
* Check for errata
|
||||
* (These will be added in the future for the chipfamily
|
||||
* R300, RV200, RS200, RV100, RS100.)
|
||||
*/
|
||||
|
||||
/* Get VRAM size and type */
|
||||
radeon_identify_vram(rinfo);
|
||||
|
||||
rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM,
|
||||
rinfo->video_ram);
|
||||
rinfo->fb_base = (void *)rinfo->fb_base_phys;
|
||||
|
||||
DPRINT("Radeon: framebuffer base phy address 0x%08x," \
|
||||
"MMIO base phy address 0x%08x," \
|
||||
"framebuffer local base 0x%08x.\n ",
|
||||
rinfo->fb_base_phys, rinfo->mmio_base_phys,
|
||||
rinfo->fb_local_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* The Graphic Device
|
||||
*/
|
||||
GraphicDevice ctfb;
|
||||
|
||||
#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
|
||||
#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
|
||||
#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
|
||||
#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
|
||||
|
||||
void *video_hw_init(void)
|
||||
{
|
||||
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
|
||||
int i;
|
||||
u32 *vm;
|
||||
|
||||
rinfo = malloc(sizeof(struct radeonfb_info));
|
||||
|
||||
if(radeon_probe(rinfo)) {
|
||||
printf("No radeon video card found!\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* fill in Graphic device struct */
|
||||
sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640,
|
||||
480, 16, (1000 / 1000),
|
||||
(2000 / 1000));
|
||||
printf ("%s\n", pGD->modeIdent);
|
||||
|
||||
pGD->winSizeX = 640;
|
||||
pGD->winSizeY = 480;
|
||||
pGD->plnSizeX = 640;
|
||||
pGD->plnSizeY = 480;
|
||||
|
||||
pGD->gdfBytesPP = 1;
|
||||
pGD->gdfIndex = GDF__8BIT_INDEX;
|
||||
|
||||
pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
|
||||
pGD->pciBase = rinfo->fb_base_phys;
|
||||
pGD->frameAdrs = rinfo->fb_base_phys;
|
||||
pGD->memSize = 64 * 1024 * 1024;
|
||||
|
||||
/* Cursor Start Address */
|
||||
pGD->dprBase =
|
||||
(pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys;
|
||||
if ((pGD->dprBase & 0x0fff) != 0) {
|
||||
/* allign it */
|
||||
pGD->dprBase &= 0xfffff000;
|
||||
pGD->dprBase += 0x00001000;
|
||||
}
|
||||
DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
|
||||
PATTERN_ADR);
|
||||
pGD->vprBase = rinfo->fb_base_phys; /* Dummy */
|
||||
pGD->cprBase = rinfo->fb_base_phys; /* Dummy */
|
||||
/* set up Hardware */
|
||||
|
||||
/* Clear video memory */
|
||||
i = pGD->memSize / 4;
|
||||
vm = (unsigned int *) pGD->pciBase;
|
||||
while (i--)
|
||||
*vm++ = 0;
|
||||
/*SetDrawingEngine (bits_per_pixel);*/
|
||||
|
||||
radeon_setmode();
|
||||
|
||||
return ((void *) pGD);
|
||||
}
|
||||
|
||||
void video_set_lut (unsigned int index, /* color number */
|
||||
unsigned char r, /* red */
|
||||
unsigned char g, /* green */
|
||||
unsigned char b /* blue */
|
||||
)
|
||||
{
|
||||
OUTREG(PALETTE_INDEX, index);
|
||||
OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b);
|
||||
}
|
||||
#endif
|
||||
293
drivers/ati_radeon_fb.h
Normal file
293
drivers/ati_radeon_fb.h
Normal file
|
|
@ -0,0 +1,293 @@
|
|||
#ifndef __ATI_RADEON_FB_H
|
||||
#define __ATI_RADEON_FB_H
|
||||
|
||||
/***************************************************************
|
||||
* Most of the definitions here are adapted right from XFree86 *
|
||||
***************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* Chip families. Must fit in the low 16 bits of a long word
|
||||
*/
|
||||
enum radeon_family {
|
||||
CHIP_FAMILY_UNKNOW,
|
||||
CHIP_FAMILY_LEGACY,
|
||||
CHIP_FAMILY_RADEON,
|
||||
CHIP_FAMILY_RV100,
|
||||
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
|
||||
CHIP_FAMILY_RV200,
|
||||
CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
|
||||
RS250 (IGP 7000) */
|
||||
CHIP_FAMILY_R200,
|
||||
CHIP_FAMILY_RV250,
|
||||
CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
|
||||
CHIP_FAMILY_RV280,
|
||||
CHIP_FAMILY_R300,
|
||||
CHIP_FAMILY_R350,
|
||||
CHIP_FAMILY_RV350,
|
||||
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
|
||||
CHIP_FAMILY_R420, /* R420/R423/M18 */
|
||||
CHIP_FAMILY_LAST,
|
||||
};
|
||||
|
||||
#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV200) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS100) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS200) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV250) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV280) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS300))
|
||||
|
||||
|
||||
#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV350) || \
|
||||
((rinfo)->family == CHIP_FAMILY_R350) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV380) || \
|
||||
((rinfo)->family == CHIP_FAMILY_R420))
|
||||
|
||||
|
||||
struct radeonfb_info {
|
||||
char name[20];
|
||||
|
||||
struct pci_device_id pdev;
|
||||
u16 family;
|
||||
|
||||
u32 fb_base_phys;
|
||||
u32 mmio_base_phys;
|
||||
|
||||
void *mmio_base;
|
||||
void *fb_base;
|
||||
|
||||
u32 video_ram;
|
||||
u32 mapped_vram;
|
||||
int vram_width;
|
||||
int vram_ddr;
|
||||
|
||||
u32 fb_local_base;
|
||||
};
|
||||
|
||||
#define INREG8(addr) readb((rinfo->mmio_base)+addr)
|
||||
#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
|
||||
#define INREG16(addr) readw((rinfo->mmio_base)+addr)
|
||||
#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
|
||||
#define INREG(addr) readl((rinfo->mmio_base)+addr)
|
||||
#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
|
||||
|
||||
static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
|
||||
u32 val, u32 mask)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
tmp = INREG(addr);
|
||||
tmp &= (mask);
|
||||
tmp |= (val);
|
||||
OUTREG(addr, tmp);
|
||||
}
|
||||
|
||||
#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
|
||||
|
||||
|
||||
/*
|
||||
* 2D Engine helper routines
|
||||
*/
|
||||
static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* initiate flush */
|
||||
OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
|
||||
~RB2D_DC_FLUSH_ALL);
|
||||
|
||||
for (i=0; i < 2000000; i++) {
|
||||
if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
|
||||
return;
|
||||
udelay(1);
|
||||
}
|
||||
printf("radeonfb: Flush Timeout !\n");
|
||||
}
|
||||
|
||||
|
||||
static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<2000000; i++) {
|
||||
if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
|
||||
return;
|
||||
udelay(1);
|
||||
}
|
||||
printf("radeonfb: FIFO Timeout !\n");
|
||||
}
|
||||
|
||||
|
||||
static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* ensure FIFO is empty before waiting for idle */
|
||||
_radeon_fifo_wait (rinfo, 64);
|
||||
|
||||
for (i=0; i<2000000; i++) {
|
||||
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
|
||||
radeon_engine_flush (rinfo);
|
||||
return;
|
||||
}
|
||||
udelay(1);
|
||||
}
|
||||
printf("radeonfb: Idle Timeout !\n");
|
||||
}
|
||||
|
||||
|
||||
#define radeon_engine_idle() _radeon_engine_idle(rinfo)
|
||||
#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
|
||||
#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
|
||||
|
||||
/*
|
||||
* This structure contains the various registers manipulated by this
|
||||
* driver for setting or restoring a mode. It's mostly copied from
|
||||
* XFree's RADEONSaveRec structure. A few chip settings might still be
|
||||
* tweaked without beeing reflected or saved in these registers though
|
||||
*/
|
||||
struct radeon_regs {
|
||||
/* Common registers */
|
||||
u32 ovr_clr;
|
||||
u32 ovr_wid_left_right;
|
||||
u32 ovr_wid_top_bottom;
|
||||
u32 ov0_scale_cntl;
|
||||
u32 mpp_tb_config;
|
||||
u32 mpp_gp_config;
|
||||
u32 subpic_cntl;
|
||||
u32 viph_control;
|
||||
u32 i2c_cntl_1;
|
||||
u32 gen_int_cntl;
|
||||
u32 cap0_trig_cntl;
|
||||
u32 cap1_trig_cntl;
|
||||
u32 bus_cntl;
|
||||
u32 surface_cntl;
|
||||
u32 bios_5_scratch;
|
||||
|
||||
/* Other registers to save for VT switches or driver load/unload */
|
||||
u32 dp_datatype;
|
||||
u32 rbbm_soft_reset;
|
||||
u32 clock_cntl_index;
|
||||
u32 amcgpio_en_reg;
|
||||
u32 amcgpio_mask;
|
||||
|
||||
/* Surface/tiling registers */
|
||||
u32 surf_lower_bound[8];
|
||||
u32 surf_upper_bound[8];
|
||||
u32 surf_info[8];
|
||||
|
||||
/* CRTC registers */
|
||||
u32 crtc_gen_cntl;
|
||||
u32 crtc_ext_cntl;
|
||||
u32 dac_cntl;
|
||||
u32 crtc_h_total_disp;
|
||||
u32 crtc_h_sync_strt_wid;
|
||||
u32 crtc_v_total_disp;
|
||||
u32 crtc_v_sync_strt_wid;
|
||||
u32 crtc_offset;
|
||||
u32 crtc_offset_cntl;
|
||||
u32 crtc_pitch;
|
||||
u32 disp_merge_cntl;
|
||||
u32 grph_buffer_cntl;
|
||||
u32 crtc_more_cntl;
|
||||
|
||||
/* CRTC2 registers */
|
||||
u32 crtc2_gen_cntl;
|
||||
u32 dac2_cntl;
|
||||
u32 disp_output_cntl;
|
||||
u32 disp_hw_debug;
|
||||
u32 disp2_merge_cntl;
|
||||
u32 grph2_buffer_cntl;
|
||||
u32 crtc2_h_total_disp;
|
||||
u32 crtc2_h_sync_strt_wid;
|
||||
u32 crtc2_v_total_disp;
|
||||
u32 crtc2_v_sync_strt_wid;
|
||||
u32 crtc2_offset;
|
||||
u32 crtc2_offset_cntl;
|
||||
u32 crtc2_pitch;
|
||||
|
||||
/* Flat panel regs */
|
||||
u32 fp_crtc_h_total_disp;
|
||||
u32 fp_crtc_v_total_disp;
|
||||
u32 fp_gen_cntl;
|
||||
u32 fp2_gen_cntl;
|
||||
u32 fp_h_sync_strt_wid;
|
||||
u32 fp2_h_sync_strt_wid;
|
||||
u32 fp_horz_stretch;
|
||||
u32 fp_panel_cntl;
|
||||
u32 fp_v_sync_strt_wid;
|
||||
u32 fp2_v_sync_strt_wid;
|
||||
u32 fp_vert_stretch;
|
||||
u32 lvds_gen_cntl;
|
||||
u32 lvds_pll_cntl;
|
||||
u32 tmds_crc;
|
||||
u32 tmds_transmitter_cntl;
|
||||
|
||||
/* Computed values for PLL */
|
||||
u32 dot_clock_freq;
|
||||
int feedback_div;
|
||||
int post_div;
|
||||
|
||||
/* PLL registers */
|
||||
u32 ppll_div_3;
|
||||
u32 ppll_ref_div;
|
||||
u32 vclk_ecp_cntl;
|
||||
u32 clk_cntl_index;
|
||||
|
||||
/* Computed values for PLL2 */
|
||||
u32 dot_clock_freq_2;
|
||||
int feedback_div_2;
|
||||
int post_div_2;
|
||||
|
||||
/* PLL2 registers */
|
||||
u32 p2pll_ref_div;
|
||||
u32 p2pll_div_0;
|
||||
u32 htotal_cntl2;
|
||||
|
||||
/* Palette */
|
||||
int palette_valid;
|
||||
};
|
||||
|
||||
static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
|
||||
{
|
||||
u32 data;
|
||||
|
||||
OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
|
||||
//radeon_pll_errata_after_index(rinfo);
|
||||
data = INREG(CLOCK_CNTL_DATA);
|
||||
//radeon_pll_errata_after_data(rinfo);
|
||||
return data;
|
||||
}
|
||||
|
||||
static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
|
||||
u32 val)
|
||||
{
|
||||
|
||||
OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
|
||||
//radeon_pll_errata_after_index(rinfo);
|
||||
OUTREG(CLOCK_CNTL_DATA, val);
|
||||
//radeon_pll_errata_after_data(rinfo);
|
||||
}
|
||||
|
||||
|
||||
static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
|
||||
u32 val, u32 mask)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
tmp = __INPLL(rinfo, index);
|
||||
tmp &= (mask);
|
||||
tmp |= (val);
|
||||
__OUTPLL(rinfo, index, tmp);
|
||||
}
|
||||
|
||||
|
||||
#define INPLL(addr) __INPLL(rinfo, addr)
|
||||
#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
|
||||
#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
1986
include/radeon.h
Normal file
1986
include/radeon.h
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user