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net: sun8i_emac: Name magic bits and simplify read-modify-write calls
The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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@ -85,15 +85,30 @@
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/* H3/A64 EMAC Register's offset */
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#define EMAC_CTL0 0x00
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#define EMAC_CTL0_FULL_DUPLEX BIT(0)
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#define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
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#define EMAC_CTL0_SPEED_10 (0x2 << 2)
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#define EMAC_CTL0_SPEED_100 (0x3 << 2)
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#define EMAC_CTL0_SPEED_1000 (0x0 << 2)
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#define EMAC_CTL1 0x04
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#define EMAC_CTL1_SOFT_RST BIT(0)
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#define EMAC_CTL1_BURST_LEN_SHIFT 24
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#define EMAC_INT_STA 0x08
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#define EMAC_INT_EN 0x0c
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#define EMAC_TX_CTL0 0x10
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#define EMAC_TX_CTL0_TX_EN BIT(31)
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#define EMAC_TX_CTL1 0x14
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#define EMAC_TX_CTL1_TX_MD BIT(1)
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#define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
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#define EMAC_TX_CTL1_TX_DMA_START BIT(31)
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#define EMAC_TX_FLOW_CTL 0x1c
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#define EMAC_TX_DMA_DESC 0x20
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#define EMAC_RX_CTL0 0x24
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#define EMAC_RX_CTL0_RX_EN BIT(31)
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#define EMAC_RX_CTL1 0x28
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#define EMAC_RX_CTL1_RX_MD BIT(1)
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#define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
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#define EMAC_RX_CTL1_RX_DMA_START BIT(31)
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#define EMAC_RX_DMA_DESC 0x34
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#define EMAC_MII_CMD 0x48
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#define EMAC_MII_DATA 0x4c
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@ -105,6 +120,11 @@
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#define EMAC_RX_DMA_STA 0xc0
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#define EMAC_RX_CUR_DESC 0xc4
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#define EMAC_DESC_OWN_DMA BIT(31)
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#define EMAC_DESC_LAST_DESC BIT(30)
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#define EMAC_DESC_FIRST_DESC BIT(29)
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#define EMAC_DESC_CHAIN_SECOND BIT(24)
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DECLARE_GLOBAL_DATA_PTR;
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enum emac_variant {
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@ -117,7 +137,7 @@ enum emac_variant {
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struct emac_dma_desc {
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u32 status;
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u32 st;
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u32 ctl_size;
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u32 buf_addr;
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u32 next;
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} __aligned(ARCH_DMA_MINALIGN);
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@ -236,21 +256,21 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
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v = readl(priv->mac_reg + EMAC_CTL0);
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if (phydev->duplex)
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v |= BIT(0);
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v |= EMAC_CTL0_FULL_DUPLEX;
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else
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v &= ~BIT(0);
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v &= ~EMAC_CTL0_FULL_DUPLEX;
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v &= ~0x0C;
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v &= ~EMAC_CTL0_SPEED_MASK;
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switch (phydev->speed) {
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case 1000:
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v |= EMAC_CTL0_SPEED_1000;
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break;
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case 100:
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v |= BIT(2);
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v |= BIT(3);
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v |= EMAC_CTL0_SPEED_100;
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break;
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case 10:
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v |= BIT(3);
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v |= EMAC_CTL0_SPEED_10;
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break;
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}
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writel(v, priv->mac_reg + EMAC_CTL0);
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@ -372,8 +392,8 @@ static void rx_descs_init(struct emac_eth_dev *priv)
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desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
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;
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desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
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desc_p->st |= CONFIG_ETH_RXSIZE;
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desc_p->status = BIT(31);
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desc_p->ctl_size |= CONFIG_ETH_RXSIZE;
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desc_p->status = EMAC_DESC_OWN_DMA;
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}
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/* Correcting the last pointer of the chain */
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@ -399,8 +419,8 @@ static void tx_descs_init(struct emac_eth_dev *priv)
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desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
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;
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desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
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desc_p->ctl_size = 0;
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desc_p->status = 0;
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desc_p->st = 0;
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}
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/* Correcting the last pointer of the chain */
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@ -418,7 +438,7 @@ static void tx_descs_init(struct emac_eth_dev *priv)
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static int sun8i_emac_eth_start(struct udevice *dev)
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{
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struct emac_eth_dev *priv = dev_get_priv(dev);
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u32 reg, v;
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u32 reg;
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int timeout = 100;
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int ret;
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@ -439,20 +459,17 @@ static int sun8i_emac_eth_start(struct udevice *dev)
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/* Rewrite mac address after reset */
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sun8i_eth_write_hwaddr(dev);
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v = readl(priv->mac_reg + EMAC_TX_CTL1);
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/* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
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v |= BIT(1);
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writel(v, priv->mac_reg + EMAC_TX_CTL1);
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/* transmission starts after the full frame arrived in TX DMA FIFO */
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setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
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v = readl(priv->mac_reg + EMAC_RX_CTL1);
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/* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
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/*
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* RX DMA reads data from RX DMA FIFO to host memory after a
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* complete frame has been written to RX DMA FIFO
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*/
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v |= BIT(1);
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writel(v, priv->mac_reg + EMAC_RX_CTL1);
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setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
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/* DMA */
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writel(8 << 24, priv->mac_reg + EMAC_CTL1);
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/* DMA burst length */
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writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
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/* Initialize rx/tx descriptors */
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rx_descs_init(priv);
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@ -465,18 +482,13 @@ static int sun8i_emac_eth_start(struct udevice *dev)
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sun8i_adjust_link(priv, priv->phydev);
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/* Start RX DMA */
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v = readl(priv->mac_reg + EMAC_RX_CTL1);
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v |= BIT(30);
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writel(v, priv->mac_reg + EMAC_RX_CTL1);
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/* Start TX DMA */
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v = readl(priv->mac_reg + EMAC_TX_CTL1);
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v |= BIT(30);
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writel(v, priv->mac_reg + EMAC_TX_CTL1);
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/* Start RX/TX DMA */
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setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
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setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
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/* Enable RX/TX */
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setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
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setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
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setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
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setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
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return 0;
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}
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@ -566,7 +578,7 @@ static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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status = desc_p->status;
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/* Check for DMA own bit */
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if (!(status & BIT(31))) {
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if (!(status & EMAC_DESC_OWN_DMA)) {
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length = (desc_p->status >> 16) & 0x3FFF;
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if (length < 0x40) {
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@ -597,7 +609,7 @@ static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
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{
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struct emac_eth_dev *priv = dev_get_priv(dev);
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u32 v, desc_num = priv->tx_currdescnum;
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u32 desc_num = priv->tx_currdescnum;
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struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
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uintptr_t desc_start = (uintptr_t)desc_p;
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uintptr_t desc_end = desc_start +
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@ -610,22 +622,16 @@ static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
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/* Invalidate entire buffer descriptor */
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invalidate_dcache_range(desc_start, desc_end);
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desc_p->st = length;
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/* Mandatory undocumented bit */
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desc_p->st |= BIT(24);
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desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
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memcpy((void *)data_start, packet, length);
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/* Flush data to be sent */
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flush_dcache_range(data_start, data_end);
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/* frame end */
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desc_p->st |= BIT(30);
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desc_p->st |= BIT(31);
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/*frame begin */
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desc_p->st |= BIT(29);
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desc_p->status = BIT(31);
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/* frame begin and end */
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desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
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desc_p->status = EMAC_DESC_OWN_DMA;
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/*Descriptors st and status field has changed, so FLUSH it */
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flush_dcache_range(desc_start, desc_end);
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@ -636,10 +642,12 @@ static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
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priv->tx_currdescnum = desc_num;
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/* Start the DMA */
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v = readl(priv->mac_reg + EMAC_TX_CTL1);
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v |= BIT(31);/* mandatory */
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v |= BIT(30);/* mandatory */
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writel(v, priv->mac_reg + EMAC_TX_CTL1);
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setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
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/*
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* Since we copied the data above, we return here without waiting
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* for the packet to be actually send out.
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*/
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return 0;
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}
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@ -752,7 +760,7 @@ static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
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roundup(sizeof(u32), ARCH_DMA_MINALIGN);
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/* Make the current descriptor valid again */
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desc_p->status |= BIT(31);
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desc_p->status |= EMAC_DESC_OWN_DMA;
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/* Flush Status field of descriptor */
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flush_dcache_range(desc_start, desc_end);
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@ -770,11 +778,12 @@ static void sun8i_emac_eth_stop(struct udevice *dev)
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struct emac_eth_dev *priv = dev_get_priv(dev);
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/* Stop Rx/Tx transmitter */
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clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
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clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
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clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
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clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
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/* Stop TX DMA */
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clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
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/* Stop RX/TX DMA */
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clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
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clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
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phy_shutdown(priv->phydev);
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}
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