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rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK

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The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.

Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Philipp Tomsich 2017-12-02 00:19:14 +01:00
parent cd401abcd5
commit 4fc495e9e2
1 changed files with 1 additions and 1 deletions
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2
arch/arm/include/asm/arch-rockchip/cru_rk3128.h
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@ -187,7 +187,7 @@ enum {
DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
DCLK_VOP_PLL_SEL_CPLL = 0,
DCLK_VOP_DIV_CON_SHIFT = 8,
DCLK_VOP_DIV_CON_MASK = 0xfff << DCLK_VOP_DIV_CON_SHIFT,
DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
/* CRU_CLKSEL31_CON */
VIO0_PLL_SHIFT = 5,